1 /* $NetBSD: rbus_ppb.c,v 1.42 2012/02/02 19:43:02 tls Exp $ */ 2 3 /* 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Michael Richardson <mcr@sandelman.ottawa.on.ca> 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * CardBus front-end for the Intel/Digital DECchip 21152 PCI-PCI bridge 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: rbus_ppb.c,v 1.42 2012/02/02 19:43:02 tls Exp $"); 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/mbuf.h> 42 #include <sys/malloc.h> 43 #include <sys/kernel.h> 44 #include <sys/socket.h> 45 #include <sys/ioctl.h> 46 #include <sys/errno.h> 47 #include <sys/device.h> 48 #include <sys/kmem.h> 49 50 #include <sys/rnd.h> 51 52 #include <machine/endian.h> 53 54 #include <sys/bus.h> 55 #include <sys/intr.h> 56 57 #include <dev/pci/pcivar.h> 58 #include <dev/pci/pcireg.h> 59 #include <dev/pci/pcidevs.h> 60 #include <dev/pci/ppbreg.h> 61 62 #include <dev/ic/i82365reg.h> 63 64 #include <dev/cardbus/rbus.h> 65 #include <dev/pci/pccbbreg.h> 66 #include <dev/pci/pccbbvar.h> 67 68 #include <dev/cardbus/cardbusvar.h> 69 #include <dev/pci/pcidevs.h> 70 71 #include <x86/pci/pci_addr_fixup.h> 72 #include <x86/pci/pci_bus_fixup.h> 73 #include <i386/pci/pci_intr_fixup.h> 74 #include <i386/pci/pcibios.h> 75 76 struct ppb_softc; 77 78 static int ppb_cardbus_match(device_t, cfdata_t, void *); 79 static void ppb_cardbus_attach(device_t, device_t, void *); 80 static int ppb_activate(device_t, enum devact); 81 int rppbprint(void *, const char *); 82 int rbus_intr_fixup(pci_chipset_tag_t, int, int, int); 83 void rbus_do_header_fixup(pci_chipset_tag_t, pcitag_t, void *); 84 85 static void rbus_pci_phys_allocate(pci_chipset_tag_t, pcitag_t, void *); 86 87 static int rbus_do_phys_allocate(pci_chipset_tag_t, pcitag_t, int, 88 void *, int, bus_addr_t *, bus_size_t); 89 90 static void rbus_pci_phys_countspace(pci_chipset_tag_t, pcitag_t, void *); 91 92 static int rbus_do_phys_countspace(pci_chipset_tag_t, pcitag_t, int, 93 void *, int, bus_addr_t *, bus_size_t); 94 95 unsigned int rbus_round_up(unsigned int, unsigned int); 96 97 98 struct ppb_cardbus_softc { 99 device_t sc_dev; 100 pcitag_t sc_tag; 101 int foo; 102 }; 103 104 CFATTACH_DECL_NEW(rbus_ppb, sizeof(struct ppb_cardbus_softc), 105 ppb_cardbus_match, ppb_cardbus_attach, NULL, ppb_activate); 106 107 #ifdef CBB_DEBUG 108 int rbus_ppb_debug = 0; /* hack with kdb */ 109 #define DPRINTF(X) if(rbus_ppb_debug) printf X 110 #else 111 #define DPRINTF(X) 112 #endif 113 114 static int 115 ppb_cardbus_match(device_t parent, cfdata_t match, void *aux) 116 { 117 struct cardbus_attach_args *ca = aux; 118 119 if (PCI_VENDOR(ca->ca_id) == PCI_VENDOR_DEC && 120 PCI_PRODUCT(ca->ca_id) == PCI_PRODUCT_DEC_21152) 121 return (1); 122 123 if(PCI_CLASS(ca->ca_class) == PCI_CLASS_BRIDGE && 124 PCI_SUBCLASS(ca->ca_class) == PCI_SUBCLASS_BRIDGE_PCI) { 125 /* XXX */ 126 printf("recognizing generic bridge chip\n"); 127 } 128 129 return (0); 130 } 131 132 133 int 134 rppbprint(void *aux, const char *pnp) 135 { 136 struct pcibus_attach_args *pba = aux; 137 138 /* only PCIs can attach to PPBs; easy. */ 139 if (pnp) 140 aprint_normal("pci at %s", pnp); 141 aprint_normal(" bus %d (rbus)", pba->pba_bus); 142 return (UNCONF); 143 } 144 145 int 146 rbus_intr_fixup(pci_chipset_tag_t pc, 147 int minbus, 148 int maxbus, 149 int line) 150 { 151 pci_device_foreach_min(pc, minbus, 152 maxbus, rbus_do_header_fixup, (void *)&line); 153 return 0; 154 } 155 156 void 157 rbus_do_header_fixup(pci_chipset_tag_t pc, pcitag_t tag, void *context) 158 { 159 int pin, irq; 160 int bus, device, function; 161 pcireg_t intr, id; 162 int *pline = (int *)context; 163 int line = *pline; 164 165 pci_decompose_tag(pc, tag, &bus, &device, &function); 166 id = pci_conf_read(pc, tag, PCI_ID_REG); 167 168 intr = pci_conf_read(pc, tag, PCI_INTERRUPT_REG); 169 pin = PCI_INTERRUPT_PIN(intr); 170 irq = PCI_INTERRUPT_LINE(intr); 171 172 #if 0 173 printf("do_header %02x:%02x:%02x pin=%d => line %d\n", 174 bus, device, function, pin, line); 175 #endif 176 177 intr &= ~(PCI_INTERRUPT_LINE_MASK << PCI_INTERRUPT_LINE_SHIFT); 178 intr |= (line << PCI_INTERRUPT_LINE_SHIFT); 179 pci_conf_write(pc, tag, PCI_INTERRUPT_REG, intr); 180 181 } 182 183 /* 184 * This function takes a range of PCI bus numbers and 185 * allocates space for all devices found in this space (the BARs) from 186 * the rbus space maps (I/O and memory). 187 * 188 * It assumes that "rbus" is defined. The whole concept does. 189 * 190 * It uses pci_device_foreach_min() to call rbus_pci_phys_allocate. 191 * This function is mostly stolen from 192 * pci_addr_fixup.c:pciaddr_resource_reserve. 193 * 194 */ 195 struct rbus_pci_addr_fixup_context { 196 struct ppb_cardbus_softc *csc; 197 cardbus_chipset_tag_t ct; 198 struct cardbus_softc *sc; 199 struct cardbus_attach_args *caa; 200 int minbus; 201 int maxbus; 202 bus_size_t *bussize_ioreqs; 203 bus_size_t *bussize_memreqs; 204 rbus_tag_t *iobustags; 205 rbus_tag_t *membustags; 206 }; 207 208 unsigned int 209 rbus_round_up(unsigned int size, unsigned int minval) 210 { 211 unsigned int power2; 212 213 if(size == 0) { 214 return 0; 215 } 216 217 power2=minval; 218 219 while(power2 < (1 << 31) && 220 power2 < size) { 221 power2 = power2 << 1; 222 } 223 224 return power2; 225 } 226 227 static void 228 rbus_pci_addr_fixup(struct ppb_cardbus_softc *csc, 229 cardbus_chipset_tag_t ct, 230 struct cardbus_softc *sc, 231 pci_chipset_tag_t pc, 232 struct cardbus_attach_args *caa, 233 int minbus, const int maxbus) 234 { 235 struct rbus_pci_addr_fixup_context rct; 236 const size_t size = sizeof(bus_size_t[maxbus+1]); 237 int busnum; 238 bus_addr_t start; 239 bus_space_handle_t handle; 240 u_int32_t reg; 241 242 rct.csc=csc; 243 rct.ct=ct; 244 rct.sc=sc; 245 rct.caa=caa; 246 rct.minbus = minbus; 247 rct.maxbus = maxbus; 248 if ((rct.bussize_ioreqs = kmem_zalloc(size, KM_SLEEP)) == NULL || 249 (rct.bussize_memreqs = kmem_zalloc(size, KM_SLEEP)) == NULL || 250 (rct.iobustags = 251 kmem_zalloc(maxbus * sizeof(rbus_tag_t), KM_SLEEP)) == NULL || 252 (rct.membustags = 253 kmem_zalloc(maxbus * sizeof(rbus_tag_t), KM_SLEEP)) == NULL) 254 panic("%s: memory allocation failed", __func__); 255 256 printf("%s: sizing buses %d-%d\n", 257 device_xname(rct.csc->sc_dev), 258 minbus, maxbus); 259 260 pci_device_foreach_min(pc, minbus, maxbus, 261 rbus_pci_phys_countspace, &rct); 262 263 /* 264 * we need to determine amount of address space for each 265 * bus. To do this, we have to roll up amounts and then 266 * we need to divide up the cardbus's extent to allocate 267 * some space to each bus. 268 */ 269 270 for(busnum=maxbus; busnum > minbus; busnum--) { 271 if(pci_bus_parent[busnum] != 0) { 272 if(pci_bus_parent[busnum] < minbus || 273 pci_bus_parent[busnum] >= maxbus) { 274 printf("%s: bus %d has illegal parent %d\n", 275 device_xname(rct.csc->sc_dev), 276 busnum, pci_bus_parent[busnum]); 277 continue; 278 } 279 280 /* first round amount of space up */ 281 rct.bussize_ioreqs[busnum] = 282 rbus_round_up(rct.bussize_ioreqs[busnum], PPB_IO_MIN); 283 rct.bussize_ioreqs[pci_bus_parent[busnum]] += 284 rct.bussize_ioreqs[busnum]; 285 286 rct.bussize_memreqs[busnum] = 287 rbus_round_up(rct.bussize_memreqs[busnum], PPB_MEM_MIN); 288 rct.bussize_memreqs[pci_bus_parent[busnum]] += 289 rct.bussize_memreqs[busnum]; 290 291 } 292 } 293 294 rct.bussize_ioreqs[minbus] = 295 rbus_round_up(rct.bussize_ioreqs[minbus], 4096); 296 rct.bussize_memreqs[minbus] = 297 rbus_round_up(rct.bussize_memreqs[minbus], 8); 298 299 printf("%s: total needs IO %08zx and MEM %08zx\n", 300 device_xname(rct.csc->sc_dev), 301 rct.bussize_ioreqs[minbus], rct.bussize_memreqs[minbus]); 302 303 if(!caa->ca_rbus_iot) { 304 panic("no iot bus"); 305 } 306 307 if(rct.bussize_ioreqs[minbus]) { 308 if(rbus_space_alloc(caa->ca_rbus_iot, 0, 309 rct.bussize_ioreqs[minbus], 310 rct.bussize_ioreqs[minbus]-1 /* mask */, 311 rct.bussize_ioreqs[minbus] /* align */, 312 /* flags */ 0, 313 &start, 314 &handle) != 0) { 315 panic("rbus_ppb: can not allocate %zu bytes in IO bus %d", 316 rct.bussize_ioreqs[minbus], minbus); 317 } 318 rct.iobustags[minbus]=rbus_new(caa->ca_rbus_iot, 319 start, 320 rct.bussize_ioreqs[minbus], 321 0 /* offset to add to physical address 322 to make processor address */, 323 RBUS_SPACE_DEDICATE); 324 } 325 326 if(rct.bussize_memreqs[minbus]) { 327 if(rbus_space_alloc(caa->ca_rbus_memt, 0, 328 rct.bussize_memreqs[minbus], 329 rct.bussize_memreqs[minbus]-1 /* mask */, 330 rct.bussize_memreqs[minbus] /* align */, 331 /* flags */ 0, 332 &start, 333 &handle) != 0) { 334 panic("%s: can not allocate %zu bytes in MEM bus %d", 335 device_xname(rct.csc->sc_dev), 336 rct.bussize_memreqs[minbus], minbus); 337 } 338 rct.membustags[minbus]=rbus_new(caa->ca_rbus_memt, 339 start, 340 rct.bussize_memreqs[minbus], 341 0 /* offset to add to physical 342 address to make processor 343 address */, 344 RBUS_SPACE_DEDICATE); 345 } 346 347 for(busnum=minbus+1; busnum <= maxbus; busnum++) { 348 int busparent; 349 350 busparent = pci_bus_parent[busnum]; 351 352 printf("%s: bus %d (parent=%d) needs IO %08zx and MEM %08zx\n", 353 device_xname(rct.csc->sc_dev), 354 busnum, 355 busparent, 356 rct.bussize_ioreqs[busnum], 357 rct.bussize_memreqs[busnum]); 358 359 if(busparent > maxbus) { 360 panic("rbus_ppb: illegal parent"); 361 } 362 363 if(rct.bussize_ioreqs[busnum]) { 364 if(rbus_space_alloc(rct.iobustags[busparent], 365 0, 366 rct.bussize_ioreqs[busnum], 367 rct.bussize_ioreqs[busnum]-1 /*mask */, 368 rct.bussize_ioreqs[busnum] /* align */, 369 /* flags */ 0, 370 &start, 371 &handle) != 0) { 372 panic("rbus_ppb: can not allocate %zu bytes in IO bus %d", 373 rct.bussize_ioreqs[busnum], busnum); 374 } 375 rct.iobustags[busnum]=rbus_new(rct.iobustags[busparent], 376 start, 377 rct.bussize_ioreqs[busnum], 378 0 /* offset to add to physical 379 address 380 to make processor address */, 381 RBUS_SPACE_DEDICATE); 382 383 /* program the bridge */ 384 385 /* enable I/O space */ 386 reg = pci_conf_read(pc, pci_bus_tag[busnum], 387 PCI_COMMAND_STATUS_REG); 388 reg |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE; 389 pci_conf_write(pc, pci_bus_tag[busnum], 390 PCI_COMMAND_STATUS_REG, reg); 391 392 /* now init the limit register for I/O */ 393 pci_conf_write(pc, pci_bus_tag[busnum], PPB_REG_IOSTATUS, 394 (((start & 0xf000) >> 8) << PPB_IOBASE_SHIFT) | 395 ((((start + 396 rct.bussize_ioreqs[busnum] + 397 4095) & 0xf000) >> 8) << PPB_IOLIMIT_SHIFT)); 398 } 399 400 if(rct.bussize_memreqs[busnum]) { 401 if(rbus_space_alloc(rct.membustags[busparent], 402 0, 403 rct.bussize_memreqs[busnum] /* size */, 404 rct.bussize_memreqs[busnum]-1 /*mask */, 405 rct.bussize_memreqs[busnum] /* align */, 406 /* flags */ 0, 407 &start, 408 &handle) != 0) { 409 panic("rbus_ppb: can not allocate %zu bytes in MEM bus %d", 410 rct.bussize_memreqs[busnum], busnum); 411 } 412 rct.membustags[busnum]=rbus_new(rct.membustags[busparent], 413 start, 414 rct.bussize_memreqs[busnum], 415 0 /* offset to add to physical 416 address to make processor 417 address */, 418 RBUS_SPACE_DEDICATE); 419 420 /* program the bridge */ 421 /* enable memory space */ 422 reg = pci_conf_read(pc, pci_bus_tag[busnum], 423 PCI_COMMAND_STATUS_REG); 424 reg |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 425 pci_conf_write(pc, pci_bus_tag[busnum], 426 PCI_COMMAND_STATUS_REG, reg); 427 428 /* now init the limit register for memory */ 429 pci_conf_write(pc, pci_bus_tag[busnum], PPB_REG_MEM, 430 ((start & PPB_MEM_MASK) 431 >> PPB_MEM_SHIFT) << PPB_MEMBASE_SHIFT | 432 (((start + 433 rct.bussize_memreqs[busnum] + 434 PPB_MEM_MIN-1) >> PPB_MEM_SHIFT) 435 << PPB_MEMLIMIT_SHIFT)); 436 437 /* and set the prefetchable limits as well */ 438 pci_conf_write(pc, pci_bus_tag[busnum], PPB_REG_PREFMEM, 439 ((start & PPB_MEM_MASK) 440 >> PPB_MEM_SHIFT) << PPB_MEMBASE_SHIFT | 441 (((start + 442 rct.bussize_memreqs[busnum] + 443 PPB_MEM_MIN-1) >> PPB_MEM_SHIFT) 444 << PPB_MEMLIMIT_SHIFT)); 445 446 /* pci_conf_print(pc, pci_bus_tag[busnum], NULL); */ 447 } 448 } 449 450 printf("%s: configuring buses %d-%d\n", 451 device_xname(rct.csc->sc_dev), 452 minbus, maxbus); 453 pci_device_foreach_min(pc, minbus, maxbus, 454 rbus_pci_phys_allocate, &rct); 455 456 kmem_free(rct.bussize_ioreqs, size); 457 kmem_free(rct.bussize_memreqs, size); 458 kmem_free(rct.iobustags, maxbus * sizeof(rbus_tag_t)); 459 kmem_free(rct.membustags, maxbus * sizeof(rbus_tag_t)); 460 } 461 462 static void 463 rbus_pci_phys_countspace(pci_chipset_tag_t pc, pcitag_t tag, void *context) 464 { 465 int bus, device, function; 466 struct rbus_pci_addr_fixup_context *rct = 467 (struct rbus_pci_addr_fixup_context *)context; 468 469 pci_decompose_tag(pc, tag, &bus, &device, &function); 470 471 printf("%s: configuring device %02x:%02x:%02x\n", 472 device_xname(rct->csc->sc_dev), 473 bus, device, function); 474 475 pciaddr_resource_manage(pc, tag, 476 rbus_do_phys_countspace, context); 477 } 478 479 480 int 481 rbus_do_phys_countspace(pci_chipset_tag_t pc, pcitag_t tag, int mapreg, void *ctx, int type, bus_addr_t *addr, bus_size_t size) 482 { 483 struct rbus_pci_addr_fixup_context *rct = 484 (struct rbus_pci_addr_fixup_context *)ctx; 485 int bus, device, function; 486 487 pci_decompose_tag(pc, tag, &bus, &device, &function); 488 489 if(size > (1<<24)) { 490 printf("%s: skipping huge space request of size=%08x\n", 491 device_xname(rct->csc->sc_dev), (unsigned int)size); 492 return 0; 493 } 494 495 if(PCI_MAPREG_TYPE(type) == PCI_MAPREG_TYPE_IO) { 496 rct->bussize_ioreqs[bus] += size; 497 } else { 498 rct->bussize_memreqs[bus]+= size; 499 } 500 501 return 0; 502 } 503 504 static void 505 rbus_pci_phys_allocate(pci_chipset_tag_t pc, pcitag_t tag, void *context) 506 { 507 int bus, device, function, command; 508 struct rbus_pci_addr_fixup_context *rct = 509 (struct rbus_pci_addr_fixup_context *)context; 510 511 pci_decompose_tag(pc, tag, &bus, &device, &function); 512 513 printf("%s: configuring device %02x:%02x:%02x\n", 514 device_xname(rct->csc->sc_dev), 515 bus, device, function); 516 517 pciaddr_resource_manage(pc, tag, 518 rbus_do_phys_allocate, context); 519 520 /* now turn the device's memory and I/O on */ 521 command = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 522 command |= PCI_COMMAND_IO_ENABLE|PCI_COMMAND_MEM_ENABLE; 523 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, command); 524 } 525 526 int 527 rbus_do_phys_allocate(pci_chipset_tag_t pc, pcitag_t tag, int mapreg, void *ctx, int type, bus_addr_t *addr, bus_size_t size) 528 { 529 struct rbus_pci_addr_fixup_context *rct = 530 (struct rbus_pci_addr_fixup_context *)ctx; 531 cardbus_chipset_tag_t ct = rct->ct; 532 struct cardbus_softc *sc = rct->sc; 533 cardbus_function_t *cf = sc->sc_cf; 534 rbus_tag_t rbustag; 535 bus_space_tag_t bustag; 536 bus_addr_t mask = size -1; 537 bus_addr_t base = 0; 538 bus_space_handle_t handle; 539 int busflags = 0; 540 int flags = 0; 541 const char *bustype; 542 int bus, device, function; 543 544 pci_decompose_tag(pc, tag, &bus, &device, &function); 545 546 /* 547 * some devices come up with garbage in them (Tulip?) 548 * we are in charge here, so give them address 549 * space anyway. 550 * 551 * XXX this may be due to no secondary PCI reset!!! 552 */ 553 #if 0 554 if (*addr) { 555 printf("Already allocated space at %08x\n", 556 (unsigned int)*addr); 557 return (0); 558 } 559 #endif 560 561 if(size > (1<<24)) { 562 printf("%s: skipping huge space request of size=%08x\n", 563 device_xname(rct->csc->sc_dev), (unsigned int)size); 564 return 0; 565 } 566 567 if(PCI_MAPREG_TYPE(type) == PCI_MAPREG_TYPE_IO) { 568 bustag = sc->sc_iot; 569 rbustag = rct->iobustags[bus]; 570 bustype = "io"; 571 } else { 572 bustag = sc->sc_memt; 573 rbustag = rct->membustags[bus]; 574 bustype = "mem"; 575 } 576 577 if((*cf->cardbus_space_alloc)(ct, rbustag, base, size, 578 mask, size, busflags|flags, 579 addr, &handle)) { 580 printf("%s: no available resources (size=%08x) for bar %2d. fixup failed\n", 581 device_xname(rct->csc->sc_dev), (unsigned int)size, mapreg); 582 583 *addr = 0; 584 pci_conf_write(pc, tag, mapreg, *addr); 585 return (1); 586 } 587 588 printf("%s: alloc %s space of size %08x for %02d:%02d:%02d -> %08x\n", 589 device_xname(rct->csc->sc_dev), 590 bustype, 591 (unsigned int)size, 592 bus, device, function, (unsigned int)*addr); 593 594 /* write new address to PCI device configuration header */ 595 pci_conf_write(pc, tag, mapreg, *addr); 596 597 /* check */ 598 { 599 DPRINTF(("%s: pci_addr_fixup: ", 600 device_xname(rct->csc->sc_dev))); 601 #ifdef CBB_DEBUG 602 if(rbus_ppb_debug) { pciaddr_print_devid(pc, tag); } 603 #endif 604 } 605 606 /* double check that the value got inserted correctly */ 607 if (pciaddr_ioaddr(pci_conf_read(pc, tag, mapreg)) != *addr) { 608 pci_conf_write(pc, tag, mapreg, 0); /* clear */ 609 printf("%s: fixup failed. (new address=%#x)\n", 610 device_xname(rct->csc->sc_dev), 611 (unsigned)*addr); 612 return (1); 613 } 614 615 DPRINTF(("new address 0x%08x\n", 616 (unsigned)*addr)); 617 618 return (0); 619 } 620 621 static void 622 ppb_cardbus_attach(device_t parent, device_t self, void *aux) 623 { 624 struct ppb_cardbus_softc *csc = device_private(self); 625 struct cardbus_softc *parent_sc = device_private(parent); 626 struct cardbus_attach_args *ca = aux; 627 cardbus_devfunc_t ct = ca->ca_ct; 628 cardbus_chipset_tag_t cc = ct->ct_cc; 629 struct pccbb_softc *psc = (struct pccbb_softc *)cc; 630 struct pcibus_attach_args pba; 631 char devinfo[256]; 632 pcireg_t busdata; 633 int mybus, rv; 634 u_int16_t pciirq; 635 int minbus, maxbus; 636 637 csc->sc_dev = self; 638 639 mybus = ct->ct_bus; 640 pciirq = 0; 641 rv = 0; 642 643 pci_devinfo(ca->ca_id, ca->ca_class, 0, devinfo, sizeof(devinfo)); 644 printf(": %s (rev. 0x%02x)\n", devinfo, PCI_REVISION(ca->ca_class)); 645 646 csc->sc_tag = ca->ca_tag; 647 648 busdata = Cardbus_conf_read(ct, ca->ca_tag, PPB_REG_BUSINFO); 649 minbus = pcibios_max_bus; 650 maxbus = minbus; /* XXX; gcc */ 651 652 if (PPB_BUSINFO_SECONDARY(busdata) == 0) { 653 aprint_error_dev(self, "not configured by system firmware calling pci_bus_fixup(%d)\n", 0); 654 655 /* 656 * first, pull the reset wire on the secondary bridge 657 * to clear all devices 658 */ 659 busdata = Cardbus_conf_read(ct, ca->ca_tag, 660 PPB_REG_BRIDGECONTROL); 661 Cardbus_conf_write(ct, ca->ca_tag, PPB_REG_BRIDGECONTROL, 662 busdata | PPB_BC_SECONDARY_RESET); 663 delay(1); 664 Cardbus_conf_write(ct, ca->ca_tag, PPB_REG_BRIDGECONTROL, 665 busdata); 666 667 /* then go initialize the bridge control registers */ 668 maxbus = pci_bus_fixup(psc->sc_pc, 0); 669 } 670 671 busdata = Cardbus_conf_read(ct, ca->ca_tag, PPB_REG_BUSINFO); 672 if(PPB_BUSINFO_SECONDARY(busdata) == 0) { 673 aprint_error_dev(self, "still not configured, not fixable.\n"); 674 return; 675 } 676 677 #if 0 678 minbus = PPB_BUSINFO_SECONDARY(busdata); 679 maxbus = PPB_BUSINFO_SUBORDINATE(busdata); 680 #endif 681 682 /* now, go and assign addresses for the new devices */ 683 rbus_pci_addr_fixup(csc, cc, parent_sc, 684 psc->sc_pc, 685 ca, 686 minbus, maxbus); 687 688 /* 689 * now configure all connected devices to the IRQ which 690 * was assigned to this slot, as they will all arrive from 691 * that IRQ. 692 */ 693 rbus_intr_fixup(psc->sc_pc, minbus, maxbus, 0); 694 695 /* 696 * enable direct routing of interrupts. We do this because 697 * we can not manage to get pccb_intr_establish() called until 698 * PCI subsystem is merged with rbus. The major thing that this 699 * routine does is avoid calling the driver's interrupt routine 700 * when the card has been removed. 701 * 702 * The rbus_ppb.c can not cope with card desertions until the merging 703 * anyway. 704 */ 705 pccbb_intr_route(psc); 706 707 /* 708 * Attach the PCI bus than hangs off of it. 709 * 710 * XXX Don't pass-through Memory Read Multiple. Should we? 711 * XXX Consult the spec... 712 */ 713 pba.pba_iot = ca->ca_iot; 714 pba.pba_memt = ca->ca_memt; 715 pba.pba_dmat = ca->ca_dmat; 716 pba.pba_pc = psc->sc_pc; 717 pba.pba_flags = PCI_FLAGS_IO_OKAY|PCI_FLAGS_MEM_OKAY; 718 pba.pba_bus = PPB_BUSINFO_SECONDARY(busdata); 719 pba.pba_bridgetag = &csc->sc_tag; 720 /*pba.pba_intrswiz = parent_sc->sc_intrswiz; */ 721 pba.pba_intrtag = psc->sc_pa.pa_intrtag; 722 723 config_found_ia(self, "pcibus", &pba, rppbprint); 724 } 725 726 int 727 ppb_activate(device_t self, enum devact act) 728 { 729 printf("ppb_activate called\n"); 730 return 0; 731 } 732 733