1 /* $NetBSD: rbus_ppb.c,v 1.39 2010/03/05 22:47:03 dyoung Exp $ */ 2 3 /* 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Michael Richardson <mcr@sandelman.ottawa.on.ca> 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * CardBus front-end for the Intel/Digital DECchip 21152 PCI-PCI bridge 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: rbus_ppb.c,v 1.39 2010/03/05 22:47:03 dyoung Exp $"); 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/mbuf.h> 42 #include <sys/malloc.h> 43 #include <sys/kernel.h> 44 #include <sys/socket.h> 45 #include <sys/ioctl.h> 46 #include <sys/errno.h> 47 #include <sys/device.h> 48 #include <sys/kmem.h> 49 50 #if NRND > 0 51 #include <sys/rnd.h> 52 #endif 53 54 #include <machine/endian.h> 55 56 #include <sys/bus.h> 57 #include <sys/intr.h> 58 59 #include <dev/pci/pcivar.h> 60 #include <dev/pci/pcireg.h> 61 #include <dev/pci/pcidevs.h> 62 #include <dev/pci/ppbreg.h> 63 64 #include <dev/ic/i82365reg.h> 65 66 #include <dev/pci/pccbbreg.h> 67 #include <dev/pci/pccbbvar.h> 68 69 #include <dev/cardbus/cardbusvar.h> 70 #include <dev/pci/pcidevs.h> 71 72 #include <x86/pci/pci_addr_fixup.h> 73 #include <x86/pci/pci_bus_fixup.h> 74 #include <i386/pci/pci_intr_fixup.h> 75 #include <i386/pci/pcibios.h> 76 77 struct ppb_softc; 78 79 static int ppb_cardbus_match(device_t, cfdata_t, void *); 80 static void ppb_cardbus_attach(device_t, device_t, void *); 81 static int ppb_activate(device_t, enum devact); 82 int rppbprint(void *, const char *); 83 int rbus_intr_fixup(pci_chipset_tag_t, int, int, int); 84 void rbus_do_header_fixup(pci_chipset_tag_t, pcitag_t, void *); 85 86 static void rbus_pci_phys_allocate(pci_chipset_tag_t, pcitag_t, void *); 87 88 static int rbus_do_phys_allocate(pci_chipset_tag_t, pcitag_t, int, 89 void *, int, bus_addr_t *, bus_size_t); 90 91 static void rbus_pci_phys_countspace(pci_chipset_tag_t, pcitag_t, void *); 92 93 static int rbus_do_phys_countspace(pci_chipset_tag_t, pcitag_t, int, 94 void *, int, bus_addr_t *, bus_size_t); 95 96 unsigned int rbus_round_up(unsigned int, unsigned int); 97 98 99 struct ppb_cardbus_softc { 100 device_t sc_dev; 101 pcitag_t sc_tag; 102 int foo; 103 }; 104 105 CFATTACH_DECL_NEW(rbus_ppb, sizeof(struct ppb_cardbus_softc), 106 ppb_cardbus_match, ppb_cardbus_attach, NULL, ppb_activate); 107 108 #ifdef CBB_DEBUG 109 int rbus_ppb_debug = 0; /* hack with kdb */ 110 #define DPRINTF(X) if(rbus_ppb_debug) printf X 111 #else 112 #define DPRINTF(X) 113 #endif 114 115 static int 116 ppb_cardbus_match(device_t parent, cfdata_t match, void *aux) 117 { 118 struct cardbus_attach_args *ca = aux; 119 120 if (PCI_VENDOR(ca->ca_id) == PCI_VENDOR_DEC && 121 PCI_PRODUCT(ca->ca_id) == PCI_PRODUCT_DEC_21152) 122 return (1); 123 124 if(PCI_CLASS(ca->ca_class) == PCI_CLASS_BRIDGE && 125 PCI_SUBCLASS(ca->ca_class) == PCI_SUBCLASS_BRIDGE_PCI) { 126 /* XXX */ 127 printf("recognizing generic bridge chip\n"); 128 } 129 130 return (0); 131 } 132 133 134 int 135 rppbprint(void *aux, const char *pnp) 136 { 137 struct pcibus_attach_args *pba = aux; 138 139 /* only PCIs can attach to PPBs; easy. */ 140 if (pnp) 141 aprint_normal("pci at %s", pnp); 142 aprint_normal(" bus %d (rbus)", pba->pba_bus); 143 return (UNCONF); 144 } 145 146 int 147 rbus_intr_fixup(pci_chipset_tag_t pc, 148 int minbus, 149 int maxbus, 150 int line) 151 { 152 pci_device_foreach_min(pc, minbus, 153 maxbus, rbus_do_header_fixup, (void *)&line); 154 return 0; 155 } 156 157 void 158 rbus_do_header_fixup(pci_chipset_tag_t pc, pcitag_t tag, void *context) 159 { 160 int pin, irq; 161 int bus, device, function; 162 pcireg_t intr, id; 163 int *pline = (int *)context; 164 int line = *pline; 165 166 pci_decompose_tag(pc, tag, &bus, &device, &function); 167 id = pci_conf_read(pc, tag, PCI_ID_REG); 168 169 intr = pci_conf_read(pc, tag, PCI_INTERRUPT_REG); 170 pin = PCI_INTERRUPT_PIN(intr); 171 irq = PCI_INTERRUPT_LINE(intr); 172 173 #if 0 174 printf("do_header %02x:%02x:%02x pin=%d => line %d\n", 175 bus, device, function, pin, line); 176 #endif 177 178 intr &= ~(PCI_INTERRUPT_LINE_MASK << PCI_INTERRUPT_LINE_SHIFT); 179 intr |= (line << PCI_INTERRUPT_LINE_SHIFT); 180 pci_conf_write(pc, tag, PCI_INTERRUPT_REG, intr); 181 182 } 183 184 /* 185 * This function takes a range of PCI bus numbers and 186 * allocates space for all devices found in this space (the BARs) from 187 * the rbus space maps (I/O and memory). 188 * 189 * It assumes that "rbus" is defined. The whole concept does. 190 * 191 * It uses pci_device_foreach_min() to call rbus_pci_phys_allocate. 192 * This function is mostly stolen from 193 * pci_addr_fixup.c:pciaddr_resource_reserve. 194 * 195 */ 196 struct rbus_pci_addr_fixup_context { 197 struct ppb_cardbus_softc *csc; 198 cardbus_chipset_tag_t ct; 199 struct cardbus_softc *sc; 200 struct cardbus_attach_args *caa; 201 int minbus; 202 int maxbus; 203 bus_size_t *bussize_ioreqs; 204 bus_size_t *bussize_memreqs; 205 rbus_tag_t *iobustags; 206 rbus_tag_t *membustags; 207 }; 208 209 unsigned int 210 rbus_round_up(unsigned int size, unsigned int minval) 211 { 212 unsigned int power2; 213 214 if(size == 0) { 215 return 0; 216 } 217 218 power2=minval; 219 220 while(power2 < (1 << 31) && 221 power2 < size) { 222 power2 = power2 << 1; 223 } 224 225 return power2; 226 } 227 228 static void 229 rbus_pci_addr_fixup(struct ppb_cardbus_softc *csc, 230 cardbus_chipset_tag_t ct, 231 struct cardbus_softc *sc, 232 pci_chipset_tag_t pc, 233 struct cardbus_attach_args *caa, 234 int minbus, const int maxbus) 235 { 236 struct rbus_pci_addr_fixup_context rct; 237 const size_t size = sizeof(bus_size_t[maxbus+1]); 238 int busnum; 239 bus_addr_t start; 240 bus_space_handle_t handle; 241 u_int32_t reg; 242 243 rct.csc=csc; 244 rct.ct=ct; 245 rct.sc=sc; 246 rct.caa=caa; 247 rct.minbus = minbus; 248 rct.maxbus = maxbus; 249 if ((rct.bussize_ioreqs = kmem_zalloc(size, KM_SLEEP)) == NULL || 250 (rct.bussize_memreqs = kmem_zalloc(size, KM_SLEEP)) == NULL || 251 (rct.iobustags = 252 kmem_zalloc(maxbus * sizeof(rbus_tag_t), KM_SLEEP)) == NULL || 253 (rct.membustags = 254 kmem_zalloc(maxbus * sizeof(rbus_tag_t), KM_SLEEP)) == NULL) 255 panic("%s: memory allocation failed", __func__); 256 257 printf("%s: sizing buses %d-%d\n", 258 device_xname(rct.csc->sc_dev), 259 minbus, maxbus); 260 261 pci_device_foreach_min(pc, minbus, maxbus, 262 rbus_pci_phys_countspace, &rct); 263 264 /* 265 * we need to determine amount of address space for each 266 * bus. To do this, we have to roll up amounts and then 267 * we need to divide up the cardbus's extent to allocate 268 * some space to each bus. 269 */ 270 271 for(busnum=maxbus; busnum > minbus; busnum--) { 272 if(pci_bus_parent[busnum] != 0) { 273 if(pci_bus_parent[busnum] < minbus || 274 pci_bus_parent[busnum] >= maxbus) { 275 printf("%s: bus %d has illegal parent %d\n", 276 device_xname(rct.csc->sc_dev), 277 busnum, pci_bus_parent[busnum]); 278 continue; 279 } 280 281 /* first round amount of space up */ 282 rct.bussize_ioreqs[busnum] = 283 rbus_round_up(rct.bussize_ioreqs[busnum], PPB_IO_MIN); 284 rct.bussize_ioreqs[pci_bus_parent[busnum]] += 285 rct.bussize_ioreqs[busnum]; 286 287 rct.bussize_memreqs[busnum] = 288 rbus_round_up(rct.bussize_memreqs[busnum], PPB_MEM_MIN); 289 rct.bussize_memreqs[pci_bus_parent[busnum]] += 290 rct.bussize_memreqs[busnum]; 291 292 } 293 } 294 295 rct.bussize_ioreqs[minbus] = 296 rbus_round_up(rct.bussize_ioreqs[minbus], 4096); 297 rct.bussize_memreqs[minbus] = 298 rbus_round_up(rct.bussize_memreqs[minbus], 8); 299 300 printf("%s: total needs IO %08zx and MEM %08zx\n", 301 device_xname(rct.csc->sc_dev), 302 rct.bussize_ioreqs[minbus], rct.bussize_memreqs[minbus]); 303 304 if(!caa->ca_rbus_iot) { 305 panic("no iot bus"); 306 } 307 308 if(rct.bussize_ioreqs[minbus]) { 309 if(rbus_space_alloc(caa->ca_rbus_iot, 0, 310 rct.bussize_ioreqs[minbus], 311 rct.bussize_ioreqs[minbus]-1 /* mask */, 312 rct.bussize_ioreqs[minbus] /* align */, 313 /* flags */ 0, 314 &start, 315 &handle) != 0) { 316 panic("rbus_ppb: can not allocate %zu bytes in IO bus %d", 317 rct.bussize_ioreqs[minbus], minbus); 318 } 319 rct.iobustags[minbus]=rbus_new(caa->ca_rbus_iot, 320 start, 321 rct.bussize_ioreqs[minbus], 322 0 /* offset to add to physical address 323 to make processor address */, 324 RBUS_SPACE_DEDICATE); 325 } 326 327 if(rct.bussize_memreqs[minbus]) { 328 if(rbus_space_alloc(caa->ca_rbus_memt, 0, 329 rct.bussize_memreqs[minbus], 330 rct.bussize_memreqs[minbus]-1 /* mask */, 331 rct.bussize_memreqs[minbus] /* align */, 332 /* flags */ 0, 333 &start, 334 &handle) != 0) { 335 panic("%s: can not allocate %zu bytes in MEM bus %d", 336 device_xname(rct.csc->sc_dev), 337 rct.bussize_memreqs[minbus], minbus); 338 } 339 rct.membustags[minbus]=rbus_new(caa->ca_rbus_memt, 340 start, 341 rct.bussize_memreqs[minbus], 342 0 /* offset to add to physical 343 address to make processor 344 address */, 345 RBUS_SPACE_DEDICATE); 346 } 347 348 for(busnum=minbus+1; busnum <= maxbus; busnum++) { 349 int busparent; 350 351 busparent = pci_bus_parent[busnum]; 352 353 printf("%s: bus %d (parent=%d) needs IO %08zx and MEM %08zx\n", 354 device_xname(rct.csc->sc_dev), 355 busnum, 356 busparent, 357 rct.bussize_ioreqs[busnum], 358 rct.bussize_memreqs[busnum]); 359 360 if(busparent > maxbus) { 361 panic("rbus_ppb: illegal parent"); 362 } 363 364 if(rct.bussize_ioreqs[busnum]) { 365 if(rbus_space_alloc(rct.iobustags[busparent], 366 0, 367 rct.bussize_ioreqs[busnum], 368 rct.bussize_ioreqs[busnum]-1 /*mask */, 369 rct.bussize_ioreqs[busnum] /* align */, 370 /* flags */ 0, 371 &start, 372 &handle) != 0) { 373 panic("rbus_ppb: can not allocate %zu bytes in IO bus %d", 374 rct.bussize_ioreqs[busnum], busnum); 375 } 376 rct.iobustags[busnum]=rbus_new(rct.iobustags[busparent], 377 start, 378 rct.bussize_ioreqs[busnum], 379 0 /* offset to add to physical 380 address 381 to make processor address */, 382 RBUS_SPACE_DEDICATE); 383 384 /* program the bridge */ 385 386 /* enable I/O space */ 387 reg = pci_conf_read(pc, pci_bus_tag[busnum], 388 PCI_COMMAND_STATUS_REG); 389 reg |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE; 390 pci_conf_write(pc, pci_bus_tag[busnum], 391 PCI_COMMAND_STATUS_REG, reg); 392 393 /* now init the limit register for I/O */ 394 pci_conf_write(pc, pci_bus_tag[busnum], PPB_REG_IOSTATUS, 395 (((start & 0xf000) >> 8) << PPB_IOBASE_SHIFT) | 396 ((((start + 397 rct.bussize_ioreqs[busnum] + 398 4095) & 0xf000) >> 8) << PPB_IOLIMIT_SHIFT)); 399 } 400 401 if(rct.bussize_memreqs[busnum]) { 402 if(rbus_space_alloc(rct.membustags[busparent], 403 0, 404 rct.bussize_memreqs[busnum] /* size */, 405 rct.bussize_memreqs[busnum]-1 /*mask */, 406 rct.bussize_memreqs[busnum] /* align */, 407 /* flags */ 0, 408 &start, 409 &handle) != 0) { 410 panic("rbus_ppb: can not allocate %zu bytes in MEM bus %d", 411 rct.bussize_memreqs[busnum], busnum); 412 } 413 rct.membustags[busnum]=rbus_new(rct.membustags[busparent], 414 start, 415 rct.bussize_memreqs[busnum], 416 0 /* offset to add to physical 417 address to make processor 418 address */, 419 RBUS_SPACE_DEDICATE); 420 421 /* program the bridge */ 422 /* enable memory space */ 423 reg = pci_conf_read(pc, pci_bus_tag[busnum], 424 PCI_COMMAND_STATUS_REG); 425 reg |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 426 pci_conf_write(pc, pci_bus_tag[busnum], 427 PCI_COMMAND_STATUS_REG, reg); 428 429 /* now init the limit register for memory */ 430 pci_conf_write(pc, pci_bus_tag[busnum], PPB_REG_MEM, 431 ((start & PPB_MEM_MASK) 432 >> PPB_MEM_SHIFT) << PPB_MEMBASE_SHIFT | 433 (((start + 434 rct.bussize_memreqs[busnum] + 435 PPB_MEM_MIN-1) >> PPB_MEM_SHIFT) 436 << PPB_MEMLIMIT_SHIFT)); 437 438 /* and set the prefetchable limits as well */ 439 pci_conf_write(pc, pci_bus_tag[busnum], PPB_REG_PREFMEM, 440 ((start & PPB_MEM_MASK) 441 >> PPB_MEM_SHIFT) << PPB_MEMBASE_SHIFT | 442 (((start + 443 rct.bussize_memreqs[busnum] + 444 PPB_MEM_MIN-1) >> PPB_MEM_SHIFT) 445 << PPB_MEMLIMIT_SHIFT)); 446 447 /* pci_conf_print(pc, pci_bus_tag[busnum], NULL); */ 448 } 449 } 450 451 printf("%s: configuring buses %d-%d\n", 452 device_xname(rct.csc->sc_dev), 453 minbus, maxbus); 454 pci_device_foreach_min(pc, minbus, maxbus, 455 rbus_pci_phys_allocate, &rct); 456 457 kmem_free(rct.bussize_ioreqs, size); 458 kmem_free(rct.bussize_memreqs, size); 459 kmem_free(rct.iobustags, maxbus * sizeof(rbus_tag_t)); 460 kmem_free(rct.membustags, maxbus * sizeof(rbus_tag_t)); 461 } 462 463 static void 464 rbus_pci_phys_countspace(pci_chipset_tag_t pc, pcitag_t tag, void *context) 465 { 466 int bus, device, function; 467 struct rbus_pci_addr_fixup_context *rct = 468 (struct rbus_pci_addr_fixup_context *)context; 469 470 pci_decompose_tag(pc, tag, &bus, &device, &function); 471 472 printf("%s: configuring device %02x:%02x:%02x\n", 473 device_xname(rct->csc->sc_dev), 474 bus, device, function); 475 476 pciaddr_resource_manage(pc, tag, 477 rbus_do_phys_countspace, context); 478 } 479 480 481 int 482 rbus_do_phys_countspace(pci_chipset_tag_t pc, pcitag_t tag, int mapreg, void *ctx, int type, bus_addr_t *addr, bus_size_t size) 483 { 484 struct rbus_pci_addr_fixup_context *rct = 485 (struct rbus_pci_addr_fixup_context *)ctx; 486 int bus, device, function; 487 488 pci_decompose_tag(pc, tag, &bus, &device, &function); 489 490 if(size > (1<<24)) { 491 printf("%s: skipping huge space request of size=%08x\n", 492 device_xname(rct->csc->sc_dev), (unsigned int)size); 493 return 0; 494 } 495 496 if(PCI_MAPREG_TYPE(type) == PCI_MAPREG_TYPE_IO) { 497 rct->bussize_ioreqs[bus] += size; 498 } else { 499 rct->bussize_memreqs[bus]+= size; 500 } 501 502 return 0; 503 } 504 505 static void 506 rbus_pci_phys_allocate(pci_chipset_tag_t pc, pcitag_t tag, void *context) 507 { 508 int bus, device, function, command; 509 struct rbus_pci_addr_fixup_context *rct = 510 (struct rbus_pci_addr_fixup_context *)context; 511 512 pci_decompose_tag(pc, tag, &bus, &device, &function); 513 514 printf("%s: configuring device %02x:%02x:%02x\n", 515 device_xname(rct->csc->sc_dev), 516 bus, device, function); 517 518 pciaddr_resource_manage(pc, tag, 519 rbus_do_phys_allocate, context); 520 521 /* now turn the device's memory and I/O on */ 522 command = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 523 command |= PCI_COMMAND_IO_ENABLE|PCI_COMMAND_MEM_ENABLE; 524 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, command); 525 } 526 527 int 528 rbus_do_phys_allocate(pci_chipset_tag_t pc, pcitag_t tag, int mapreg, void *ctx, int type, bus_addr_t *addr, bus_size_t size) 529 { 530 struct rbus_pci_addr_fixup_context *rct = 531 (struct rbus_pci_addr_fixup_context *)ctx; 532 cardbus_chipset_tag_t ct = rct->ct; 533 struct cardbus_softc *sc = rct->sc; 534 cardbus_function_t *cf = sc->sc_cf; 535 rbus_tag_t rbustag; 536 bus_space_tag_t bustag; 537 bus_addr_t mask = size -1; 538 bus_addr_t base = 0; 539 bus_space_handle_t handle; 540 int busflags = 0; 541 int flags = 0; 542 const char *bustype; 543 int bus, device, function; 544 545 pci_decompose_tag(pc, tag, &bus, &device, &function); 546 547 /* 548 * some devices come up with garbage in them (Tulip?) 549 * we are in charge here, so give them address 550 * space anyway. 551 * 552 * XXX this may be due to no secondary PCI reset!!! 553 */ 554 #if 0 555 if (*addr) { 556 printf("Already allocated space at %08x\n", 557 (unsigned int)*addr); 558 return (0); 559 } 560 #endif 561 562 if(size > (1<<24)) { 563 printf("%s: skipping huge space request of size=%08x\n", 564 device_xname(rct->csc->sc_dev), (unsigned int)size); 565 return 0; 566 } 567 568 if(PCI_MAPREG_TYPE(type) == PCI_MAPREG_TYPE_IO) { 569 bustag = sc->sc_iot; 570 rbustag = rct->iobustags[bus]; 571 bustype = "io"; 572 } else { 573 bustag = sc->sc_memt; 574 rbustag = rct->membustags[bus]; 575 bustype = "mem"; 576 } 577 578 if((*cf->cardbus_space_alloc)(ct, rbustag, base, size, 579 mask, size, busflags|flags, 580 addr, &handle)) { 581 printf("%s: no available resources (size=%08x) for bar %2d. fixup failed\n", 582 device_xname(rct->csc->sc_dev), (unsigned int)size, mapreg); 583 584 *addr = 0; 585 pci_conf_write(pc, tag, mapreg, *addr); 586 return (1); 587 } 588 589 printf("%s: alloc %s space of size %08x for %02d:%02d:%02d -> %08x\n", 590 device_xname(rct->csc->sc_dev), 591 bustype, 592 (unsigned int)size, 593 bus, device, function, (unsigned int)*addr); 594 595 /* write new address to PCI device configuration header */ 596 pci_conf_write(pc, tag, mapreg, *addr); 597 598 /* check */ 599 { 600 DPRINTF(("%s: pci_addr_fixup: ", 601 device_xname(rct->csc->sc_dev))); 602 #ifdef CBB_DEBUG 603 if(rbus_ppb_debug) { pciaddr_print_devid(pc, tag); } 604 #endif 605 } 606 607 /* double check that the value got inserted correctly */ 608 if (pciaddr_ioaddr(pci_conf_read(pc, tag, mapreg)) != *addr) { 609 pci_conf_write(pc, tag, mapreg, 0); /* clear */ 610 printf("%s: fixup failed. (new address=%#x)\n", 611 device_xname(rct->csc->sc_dev), 612 (unsigned)*addr); 613 return (1); 614 } 615 616 DPRINTF(("new address 0x%08x\n", 617 (unsigned)*addr)); 618 619 return (0); 620 } 621 622 static void 623 ppb_cardbus_attach(device_t parent, device_t self, void *aux) 624 { 625 struct ppb_cardbus_softc *csc = device_private(self); 626 struct cardbus_softc *parent_sc = device_private(parent); 627 struct cardbus_attach_args *ca = aux; 628 cardbus_devfunc_t ct = ca->ca_ct; 629 cardbus_chipset_tag_t cc = ct->ct_cc; 630 struct pccbb_softc *psc = (struct pccbb_softc *)cc; 631 struct pcibus_attach_args pba; 632 char devinfo[256]; 633 pcireg_t busdata; 634 int mybus, rv; 635 u_int16_t pciirq; 636 int minbus, maxbus; 637 638 csc->sc_dev = self; 639 640 mybus = ct->ct_bus; 641 pciirq = 0; 642 rv = 0; 643 644 /* shut up compiler */ 645 csc->foo = parent_sc->sc_intrline; 646 647 648 pci_devinfo(ca->ca_id, ca->ca_class, 0, devinfo, sizeof(devinfo)); 649 printf(": %s (rev. 0x%02x)\n", devinfo, PCI_REVISION(ca->ca_class)); 650 651 csc->sc_tag = ca->ca_tag; 652 653 busdata = Cardbus_conf_read(ct, ca->ca_tag, PPB_REG_BUSINFO); 654 minbus = pcibios_max_bus; 655 maxbus = minbus; /* XXX; gcc */ 656 657 if (PPB_BUSINFO_SECONDARY(busdata) == 0) { 658 aprint_error_dev(self, "not configured by system firmware calling pci_bus_fixup(%d)\n", 0); 659 660 /* 661 * first, pull the reset wire on the secondary bridge 662 * to clear all devices 663 */ 664 busdata = Cardbus_conf_read(ct, ca->ca_tag, 665 PPB_REG_BRIDGECONTROL); 666 Cardbus_conf_write(ct, ca->ca_tag, PPB_REG_BRIDGECONTROL, 667 busdata | PPB_BC_SECONDARY_RESET); 668 delay(1); 669 Cardbus_conf_write(ct, ca->ca_tag, PPB_REG_BRIDGECONTROL, 670 busdata); 671 672 /* then go initialize the bridge control registers */ 673 maxbus = pci_bus_fixup(psc->sc_pc, 0); 674 } 675 676 busdata = Cardbus_conf_read(ct, ca->ca_tag, PPB_REG_BUSINFO); 677 if(PPB_BUSINFO_SECONDARY(busdata) == 0) { 678 aprint_error_dev(self, "still not configured, not fixable.\n"); 679 return; 680 } 681 682 #if 0 683 minbus = PPB_BUSINFO_SECONDARY(busdata); 684 maxbus = PPB_BUSINFO_SUBORDINATE(busdata); 685 #endif 686 687 /* now, go and assign addresses for the new devices */ 688 rbus_pci_addr_fixup(csc, cc, parent_sc, 689 psc->sc_pc, 690 ca, 691 minbus, maxbus); 692 693 /* 694 * now configure all connected devices to the IRQ which 695 * was assigned to this slot, as they will all arrive from 696 * that IRQ. 697 */ 698 rbus_intr_fixup(psc->sc_pc, minbus, maxbus, ca->ca_intrline); 699 700 /* 701 * enable direct routing of interrupts. We do this because 702 * we can not manage to get pccb_intr_establish() called until 703 * PCI subsystem is merged with rbus. The major thing that this 704 * routine does is avoid calling the driver's interrupt routine 705 * when the card has been removed. 706 * 707 * The rbus_ppb.c can not cope with card desertions until the merging 708 * anyway. 709 */ 710 pccbb_intr_route(psc); 711 712 /* 713 * Attach the PCI bus than hangs off of it. 714 * 715 * XXX Don't pass-through Memory Read Multiple. Should we? 716 * XXX Consult the spec... 717 */ 718 pba.pba_iot = ca->ca_iot; 719 pba.pba_memt = ca->ca_memt; 720 pba.pba_dmat = ca->ca_dmat; 721 pba.pba_pc = psc->sc_pc; 722 pba.pba_flags = PCI_FLAGS_IO_ENABLED|PCI_FLAGS_MEM_ENABLED; 723 pba.pba_bus = PPB_BUSINFO_SECONDARY(busdata); 724 pba.pba_bridgetag = &csc->sc_tag; 725 /*pba.pba_intrswiz = parent_sc->sc_intrswiz; */ 726 pba.pba_intrtag = psc->sc_pa.pa_intrtag; 727 728 config_found_ia(self, "pcibus", &pba, rppbprint); 729 } 730 731 int 732 ppb_activate(device_t self, enum devact act) 733 { 734 printf("ppb_activate called\n"); 735 return 0; 736 } 737 738