1 /* $NetBSD: if_rtw_cardbus.c,v 1.42 2011/08/01 11:20:27 drochner Exp $ */ 2 3 /*- 4 * Copyright (c) 2004, 2005 David Young. All rights reserved. 5 * 6 * Adapted for the RTL8180 by David Young. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY David Young ``AS IS'' AND ANY 18 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 19 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 20 * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL David 21 * Young BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 22 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 23 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 25 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 28 * OF SUCH DAMAGE. 29 */ 30 /*- 31 * Copyright (c) 1999, 2000 The NetBSD Foundation, Inc. 32 * All rights reserved. 33 * 34 * This code is derived from software contributed to The NetBSD Foundation 35 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 36 * NASA Ames Research Center. 37 * 38 * Redistribution and use in source and binary forms, with or without 39 * modification, are permitted provided that the following conditions 40 * are met: 41 * 1. Redistributions of source code must retain the above copyright 42 * notice, this list of conditions and the following disclaimer. 43 * 2. Redistributions in binary form must reproduce the above copyright 44 * notice, this list of conditions and the following disclaimer in the 45 * documentation and/or other materials provided with the distribution. 46 * 47 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 48 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 49 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 50 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 51 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 52 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 53 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 54 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 55 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 56 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 57 * POSSIBILITY OF SUCH DAMAGE. 58 */ 59 60 /* 61 * Cardbus front-end for the Realtek RTL8180 802.11 MAC/BBP driver. 62 * 63 * TBD factor with atw, tlp Cardbus front-ends? 64 */ 65 66 #include <sys/cdefs.h> 67 __KERNEL_RCSID(0, "$NetBSD: if_rtw_cardbus.c,v 1.42 2011/08/01 11:20:27 drochner Exp $"); 68 69 #include "opt_inet.h" 70 71 #include <sys/param.h> 72 #include <sys/systm.h> 73 #include <sys/mbuf.h> 74 #include <sys/malloc.h> 75 #include <sys/kernel.h> 76 #include <sys/socket.h> 77 #include <sys/ioctl.h> 78 #include <sys/errno.h> 79 #include <sys/device.h> 80 81 #include <machine/endian.h> 82 83 #include <net/if.h> 84 #include <net/if_dl.h> 85 #include <net/if_media.h> 86 #include <net/if_ether.h> 87 88 #include <net80211/ieee80211_netbsd.h> 89 #include <net80211/ieee80211_radiotap.h> 90 #include <net80211/ieee80211_var.h> 91 92 #include <sys/bus.h> 93 #include <sys/intr.h> 94 95 #include <dev/ic/rtwreg.h> 96 #include <dev/ic/rtwvar.h> 97 98 #include <dev/pci/pcivar.h> 99 #include <dev/pci/pcireg.h> 100 #include <dev/pci/pcidevs.h> 101 102 #include <dev/cardbus/cardbusvar.h> 103 #include <dev/pci/pcidevs.h> 104 105 /* 106 * PCI configuration space registers used by the RTL8180. 107 */ 108 #define RTW_PCI_IOBA PCI_BAR(0) /* i/o mapped base */ 109 #define RTW_PCI_MMBA PCI_BAR(1) /* memory mapped base */ 110 111 struct rtw_cardbus_softc { 112 struct rtw_softc sc_rtw; /* real RTL8180 softc */ 113 114 /* CardBus-specific goo. */ 115 void *sc_ih; /* interrupt handle */ 116 cardbus_devfunc_t sc_ct; /* our CardBus devfuncs */ 117 pcitag_t sc_tag; /* our CardBus tag */ 118 int sc_csr; /* CSR bits */ 119 bus_size_t sc_mapsize; /* size of the mapped bus space 120 * region 121 */ 122 123 int sc_bar; /* which BAR to use */ 124 }; 125 126 int rtw_cardbus_match(device_t, cfdata_t, void *); 127 void rtw_cardbus_attach(device_t, device_t, void *); 128 int rtw_cardbus_detach(device_t, int); 129 130 CFATTACH_DECL3_NEW(rtw_cardbus, sizeof(struct rtw_cardbus_softc), 131 rtw_cardbus_match, rtw_cardbus_attach, rtw_cardbus_detach, NULL, NULL, NULL, 132 DVF_DETACH_SHUTDOWN); 133 134 void rtw_cardbus_setup(struct rtw_cardbus_softc *); 135 136 bool rtw_cardbus_resume(device_t, const pmf_qual_t *); 137 bool rtw_cardbus_suspend(device_t, const pmf_qual_t *); 138 139 const struct rtw_cardbus_product *rtw_cardbus_lookup( 140 const struct cardbus_attach_args *); 141 142 const struct rtw_cardbus_product { 143 u_int32_t rcp_vendor; /* PCI vendor ID */ 144 u_int32_t rcp_product; /* PCI product ID */ 145 const char *rcp_product_name; 146 } rtw_cardbus_products[] = { 147 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8180, 148 "Realtek RTL8180 802.11 MAC/BBP" }, 149 150 { PCI_VENDOR_BELKIN, PCI_PRODUCT_BELKIN_F5D6020V3, 151 "Belkin F5D6020v3 802.11b (RTL8180 MAC/BBP)" }, 152 153 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DWL610, 154 "DWL-610 D-Link Air 802.11b (RTL8180 MAC/BBP)" }, 155 156 { 0, 0, NULL }, 157 }; 158 159 const struct rtw_cardbus_product * 160 rtw_cardbus_lookup(const struct cardbus_attach_args *ca) 161 { 162 const struct rtw_cardbus_product *rcp; 163 164 for (rcp = rtw_cardbus_products; rcp->rcp_product_name != NULL; rcp++) { 165 if (PCI_VENDOR(ca->ca_id) == rcp->rcp_vendor && 166 PCI_PRODUCT(ca->ca_id) == rcp->rcp_product) 167 return rcp; 168 } 169 return NULL; 170 } 171 172 int 173 rtw_cardbus_match(device_t parent, cfdata_t match, void *aux) 174 { 175 struct cardbus_attach_args *ca = aux; 176 177 if (rtw_cardbus_lookup(ca) != NULL) 178 return 1; 179 180 return 0; 181 } 182 183 static void 184 rtw_cardbus_funcregen(struct rtw_regs *regs, int enable) 185 { 186 u_int32_t reg; 187 rtw_config0123_enable(regs, 1); 188 reg = RTW_READ(regs, RTW_CONFIG3); 189 if (enable) 190 RTW_WRITE(regs, RTW_CONFIG3, reg | RTW_CONFIG3_FUNCREGEN); 191 else 192 RTW_WRITE(regs, RTW_CONFIG3, reg & ~RTW_CONFIG3_FUNCREGEN); 193 rtw_config0123_enable(regs, 0); 194 } 195 196 void 197 rtw_cardbus_attach(device_t parent, device_t self, void *aux) 198 { 199 struct rtw_cardbus_softc *csc = device_private(self); 200 struct rtw_softc *sc = &csc->sc_rtw; 201 struct rtw_regs *regs = &sc->sc_regs; 202 struct cardbus_attach_args *ca = aux; 203 cardbus_devfunc_t ct = ca->ca_ct; 204 const struct rtw_cardbus_product *rcp; 205 bus_addr_t adr; 206 int rev; 207 208 sc->sc_dev = self; 209 sc->sc_dmat = ca->ca_dmat; 210 csc->sc_ct = ct; 211 csc->sc_tag = ca->ca_tag; 212 213 rcp = rtw_cardbus_lookup(ca); 214 if (rcp == NULL) { 215 printf("\n"); 216 panic("rtw_cardbus_attach: impossible"); 217 } 218 219 /* Get revision info. */ 220 rev = PCI_REVISION(ca->ca_class); 221 222 printf(": %s\n", rcp->rcp_product_name); 223 224 RTW_DPRINTF(RTW_DEBUG_ATTACH, 225 ("%s: pass %d.%d signature %08x\n", device_xname(self), 226 (rev >> 4) & 0xf, rev & 0xf, 227 Cardbus_conf_read(ct, csc->sc_tag, 0x80))); 228 229 /* 230 * Map the device. 231 */ 232 csc->sc_csr = PCI_COMMAND_MASTER_ENABLE | 233 PCI_COMMAND_PARITY_ENABLE | 234 PCI_COMMAND_SERR_ENABLE; 235 if (Cardbus_mapreg_map(ct, RTW_PCI_MMBA, PCI_MAPREG_TYPE_MEM, 0, 236 ®s->r_bt, ®s->r_bh, &adr, ®s->r_sz) == 0) { 237 RTW_DPRINTF(RTW_DEBUG_ATTACH, 238 ("%s: %s mapped %" PRIuMAX " bytes mem space\n", 239 device_xname(self), __func__, (uintmax_t)regs->r_sz)); 240 csc->sc_csr |= PCI_COMMAND_MEM_ENABLE; 241 csc->sc_bar = RTW_PCI_MMBA; 242 } else if (Cardbus_mapreg_map(ct, RTW_PCI_IOBA, PCI_MAPREG_TYPE_IO, 243 0, ®s->r_bt, ®s->r_bh, &adr, ®s->r_sz) == 0) { 244 RTW_DPRINTF(RTW_DEBUG_ATTACH, 245 ("%s: %s mapped %" PRIuMAX " bytes I/O space\n", 246 device_xname(self), __func__, (uintmax_t)regs->r_sz)); 247 csc->sc_csr |= PCI_COMMAND_IO_ENABLE; 248 csc->sc_bar = RTW_PCI_IOBA; 249 } else { 250 aprint_error_dev(self, "unable to map device registers\n"); 251 return; 252 } 253 254 /* 255 * Bring the chip out of powersave mode and initialize the 256 * configuration registers. 257 */ 258 rtw_cardbus_setup(csc); 259 260 /* 261 * Finish off the attach. 262 */ 263 rtw_attach(sc); 264 265 rtw_cardbus_funcregen(regs, 1); 266 267 RTW_WRITE(regs, RTW_FEMR, 0); 268 RTW_WRITE(regs, RTW_FER, RTW_READ(regs, RTW_FER)); 269 270 if (pmf_device_register(self, 271 rtw_cardbus_suspend, rtw_cardbus_resume)) { 272 pmf_class_network_register(self, &sc->sc_if); 273 /* 274 * Power down the socket. 275 */ 276 pmf_device_suspend(self, &sc->sc_qual); 277 } else 278 aprint_error_dev(self, "couldn't establish power handler\n"); 279 } 280 281 int 282 rtw_cardbus_detach(device_t self, int flags) 283 { 284 struct rtw_cardbus_softc *csc = device_private(self); 285 struct rtw_softc *sc = &csc->sc_rtw; 286 struct rtw_regs *regs = &sc->sc_regs; 287 struct cardbus_devfunc *ct = csc->sc_ct; 288 int rc; 289 290 #if defined(DIAGNOSTIC) 291 if (ct == NULL) 292 panic("%s: data structure lacks", device_xname(self)); 293 #endif 294 295 if ((rc = rtw_detach(sc)) != 0) 296 return rc; 297 298 /* 299 * Unhook the interrupt handler. 300 */ 301 if (csc->sc_ih != NULL) 302 Cardbus_intr_disestablish(ct, csc->sc_ih); 303 304 /* 305 * Release bus space and close window. 306 */ 307 if (csc->sc_bar != 0) 308 Cardbus_mapreg_unmap(ct, csc->sc_bar, 309 regs->r_bt, regs->r_bh, regs->r_sz); 310 311 return 0; 312 } 313 314 bool 315 rtw_cardbus_resume(device_t self, const pmf_qual_t *qual) 316 { 317 struct rtw_cardbus_softc *csc = device_private(self); 318 struct rtw_softc *sc = &csc->sc_rtw; 319 cardbus_devfunc_t ct = csc->sc_ct; 320 321 /* 322 * Map and establish the interrupt. 323 */ 324 csc->sc_ih = Cardbus_intr_establish(ct, IPL_NET, rtw_intr, sc); 325 if (csc->sc_ih == NULL) { 326 aprint_error_dev(sc->sc_dev, 327 "unable to establish interrupt\n"); 328 return false; 329 } 330 331 rtw_cardbus_funcregen(&sc->sc_regs, 1); 332 333 RTW_WRITE(&sc->sc_regs, RTW_FEMR, RTW_FEMR_INTR); 334 RTW_WRITE(&sc->sc_regs, RTW_FER, RTW_FER_INTR); 335 336 return rtw_resume(self, qual); 337 } 338 339 bool 340 rtw_cardbus_suspend(device_t self, const pmf_qual_t *qual) 341 { 342 struct rtw_cardbus_softc *csc = device_private(self); 343 struct rtw_softc *sc = &csc->sc_rtw; 344 cardbus_devfunc_t ct = csc->sc_ct; 345 346 if (!rtw_suspend(self, qual)) 347 return false; 348 349 RTW_WRITE(&sc->sc_regs, RTW_FEMR, 350 RTW_READ(&sc->sc_regs, RTW_FEMR) & ~RTW_FEMR_INTR); 351 352 rtw_cardbus_funcregen(&sc->sc_regs, 0); 353 354 /* Unhook the interrupt handler. */ 355 Cardbus_intr_disestablish(ct, csc->sc_ih); 356 csc->sc_ih = NULL; 357 return true; 358 } 359 360 void 361 rtw_cardbus_setup(struct rtw_cardbus_softc *csc) 362 { 363 pcitag_t tag = csc->sc_tag; 364 cardbus_devfunc_t ct = csc->sc_ct; 365 pcireg_t bhlc, csr, lattimer; 366 367 (void)cardbus_set_powerstate(ct, tag, PCI_PWR_D0); 368 369 /* I believe the datasheet tries to warn us that the RTL8180 370 * wants for 16 (0x10) to divide the latency timer. 371 */ 372 bhlc = Cardbus_conf_read(ct, tag, PCI_BHLC_REG); 373 lattimer = rounddown(PCI_LATTIMER(bhlc), 0x10); 374 if (PCI_LATTIMER(bhlc) != lattimer) { 375 bhlc &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 376 bhlc |= (lattimer << PCI_LATTIMER_SHIFT); 377 Cardbus_conf_write(ct, tag, PCI_BHLC_REG, bhlc); 378 } 379 380 /* Enable the appropriate bits in the PCI CSR. */ 381 csr = Cardbus_conf_read(ct, tag, PCI_COMMAND_STATUS_REG); 382 csr &= ~(PCI_COMMAND_IO_ENABLE|PCI_COMMAND_MEM_ENABLE); 383 csr |= csc->sc_csr; 384 Cardbus_conf_write(ct, tag, PCI_COMMAND_STATUS_REG, csr); 385 } 386