xref: /netbsd-src/sys/dev/cardbus/adv_cardbus.c (revision 413d532bcc3f62d122e56d92e13ac64825a40baf)
1 /*	$NetBSD: adv_cardbus.c,v 1.29 2012/10/27 17:18:15 chs Exp $	*/
2 
3 /*-
4  * Copyright (c) 2000 The NetBSD Foundation, Inc.
5  * All rights reserved.
6  *
7  * This code is derived from software contributed to The NetBSD Foundation
8  * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
9  * NASA Ames Research Center.
10  *
11  * Redistribution and use in source and binary forms, with or without
12  * modification, are permitted provided that the following conditions
13  * are met:
14  * 1. Redistributions of source code must retain the above copyright
15  *    notice, this list of conditions and the following disclaimer.
16  * 2. Redistributions in binary form must reproduce the above copyright
17  *    notice, this list of conditions and the following disclaimer in the
18  *    documentation and/or other materials provided with the distribution.
19  *
20  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
21  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
22  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
24  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30  * POSSIBILITY OF SUCH DAMAGE.
31  */
32 
33 /*
34  * this file was brought from ahc_cardbus.c and adv_pci.c
35  * and modified by YAMAMOTO Takashi.
36  */
37 
38 #include <sys/cdefs.h>
39 __KERNEL_RCSID(0, "$NetBSD: adv_cardbus.c,v 1.29 2012/10/27 17:18:15 chs Exp $");
40 
41 #include <sys/param.h>
42 #include <sys/systm.h>
43 #include <sys/malloc.h>
44 #include <sys/kernel.h>
45 #include <sys/queue.h>
46 #include <sys/device.h>
47 
48 #include <sys/bus.h>
49 #include <sys/intr.h>
50 
51 #include <dev/scsipi/scsi_all.h>
52 #include <dev/scsipi/scsipi_all.h>
53 #include <dev/scsipi/scsiconf.h>
54 
55 #include <dev/pci/pcireg.h>
56 #include <dev/pci/pcidevs.h>
57 
58 #include <dev/cardbus/cardbusvar.h>
59 #include <dev/pci/pcidevs.h>
60 
61 #include <dev/ic/advlib.h>
62 #include <dev/ic/adv.h>
63 
64 #define ADV_CARDBUS_IOBA PCI_BAR0
65 #define ADV_CARDBUS_MMBA PCI_BAR1
66 
67 #define ADV_CARDBUS_DEBUG
68 #define ADV_CARDBUS_ALLOW_MEMIO
69 
70 #define DEVNAME(sc) device_xname((sc)->sc_dev)
71 
72 struct adv_cardbus_softc {
73 	struct asc_softc sc_adv;	/* real ADV */
74 
75 	/* CardBus-specific goo. */
76 	cardbus_devfunc_t sc_ct;	/* our CardBus devfuncs */
77 	pcitag_t sc_tag;
78 
79 	int	sc_bar;
80 	pcireg_t	sc_csr;
81 	bus_size_t sc_size;
82 };
83 
84 int	adv_cardbus_match(device_t, cfdata_t, void *);
85 void	adv_cardbus_attach(device_t, device_t, void *);
86 int	adv_cardbus_detach(device_t, int);
87 
88 CFATTACH_DECL_NEW(adv_cardbus, sizeof(struct adv_cardbus_softc),
89     adv_cardbus_match, adv_cardbus_attach, adv_cardbus_detach, NULL);
90 
91 int
92 adv_cardbus_match(device_t parent, cfdata_t match, void *aux)
93 {
94 	struct cardbus_attach_args *ca = aux;
95 
96 	if (PCI_VENDOR(ca->ca_id) == PCI_VENDOR_ADVSYS &&
97 	    PCI_PRODUCT(ca->ca_id) == PCI_PRODUCT_ADVSYS_ULTRA)
98 		return (1);
99 
100 	return (0);
101 }
102 
103 void
104 adv_cardbus_attach(device_t parent, device_t self, void *aux)
105 {
106 	struct cardbus_attach_args *ca = aux;
107 	struct adv_cardbus_softc *csc = device_private(self);
108 	struct asc_softc *sc = &csc->sc_adv;
109 	cardbus_devfunc_t ct = ca->ca_ct;
110 	bus_space_tag_t iot;
111 	bus_space_handle_t ioh;
112 	pcireg_t reg;
113 	u_int8_t latency = 0x20;
114 
115 	sc->sc_dev = self;
116 	sc->sc_flags = 0;
117 
118 	if (PCI_VENDOR(ca->ca_id) == PCI_VENDOR_ADVSYS) {
119 		switch (PCI_PRODUCT(ca->ca_id)) {
120 		case PCI_PRODUCT_ADVSYS_1200A:
121 			printf(": AdvanSys ASC1200A SCSI adapter\n");
122 			latency = 0;
123 			break;
124 
125 		case PCI_PRODUCT_ADVSYS_1200B:
126 			printf(": AdvanSys ASC1200B SCSI adapter\n");
127 			latency = 0;
128 			break;
129 
130 		case PCI_PRODUCT_ADVSYS_ULTRA:
131 			switch (PCI_REVISION(ca->ca_class)) {
132 			case ASC_PCI_REVISION_3050:
133 				printf(": AdvanSys ABP-9xxUA SCSI adapter\n");
134 				break;
135 
136 			case ASC_PCI_REVISION_3150:
137 				printf(": AdvanSys ABP-9xxU SCSI adapter\n");
138 				break;
139 			}
140 			break;
141 
142 		default:
143 			printf(": unknown model!\n");
144 			return;
145 		}
146 	}
147 
148 	csc->sc_ct = ct;
149 	csc->sc_tag = ca->ca_tag;
150 
151 	/*
152 	 * Map the device.
153 	 */
154 	csc->sc_csr = PCI_COMMAND_MASTER_ENABLE;
155 
156 #ifdef ADV_CARDBUS_ALLOW_MEMIO
157 	if (Cardbus_mapreg_map(csc->sc_ct, ADV_CARDBUS_MMBA,
158 	    PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0,
159 	    &iot, &ioh, NULL, &csc->sc_size) == 0) {
160 #ifdef ADV_CARDBUS_DEBUG
161 		printf("%s: memio enabled\n", DEVNAME(sc));
162 #endif
163 		csc->sc_bar = ADV_CARDBUS_MMBA;
164 		csc->sc_csr |= PCI_COMMAND_MEM_ENABLE;
165 	} else
166 #endif
167 	if (Cardbus_mapreg_map(csc->sc_ct, ADV_CARDBUS_IOBA,
168 	    PCI_MAPREG_TYPE_IO, 0, &iot, &ioh, NULL, &csc->sc_size) == 0) {
169 #ifdef ADV_CARDBUS_DEBUG
170 		printf("%s: io enabled\n", DEVNAME(sc));
171 #endif
172 		csc->sc_bar = ADV_CARDBUS_IOBA;
173 		csc->sc_csr |= PCI_COMMAND_IO_ENABLE;
174 	} else {
175 		csc->sc_bar = 0;
176 		aprint_error_dev(sc->sc_dev, "unable to map device registers\n");
177 		return;
178 	}
179 
180 	/* Enable the appropriate bits in the PCI CSR. */
181 	reg = Cardbus_conf_read(ct, ca->ca_tag, PCI_COMMAND_STATUS_REG);
182 	reg &= ~(PCI_COMMAND_IO_ENABLE|PCI_COMMAND_MEM_ENABLE);
183 	reg |= csc->sc_csr;
184 	Cardbus_conf_write(ct, ca->ca_tag, PCI_COMMAND_STATUS_REG, reg);
185 
186 	/*
187 	 * Make sure the latency timer is set to some reasonable
188 	 * value.
189 	 */
190 	reg = Cardbus_conf_read(ct, ca->ca_tag, PCI_BHLC_REG);
191 	if (PCI_LATTIMER(reg) < latency) {
192 		reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT);
193 		reg |= (latency << PCI_LATTIMER_SHIFT);
194 		Cardbus_conf_write(ct, ca->ca_tag, PCI_BHLC_REG, reg);
195 	}
196 
197 	ASC_SET_CHIP_CONTROL(iot, ioh, ASC_CC_HALT);
198 	ASC_SET_CHIP_STATUS(iot, ioh, 0);
199 
200 	sc->sc_iot = iot;
201 	sc->sc_ioh = ioh;
202 	sc->sc_dmat = ca->ca_dmat;
203 	sc->pci_device_id = ca->ca_id;
204 	sc->bus_type = ASC_IS_PCI;
205 	sc->chip_version = ASC_GET_CHIP_VER_NO(iot, ioh);
206 
207 	/*
208 	 * Initialize the board
209 	 */
210 	if (adv_init(sc)) {
211 		printf("adv_init failed\n");
212 		return;
213 	}
214 
215 	/*
216 	 * Establish the interrupt.
217 	 */
218 	sc->sc_ih = Cardbus_intr_establish(ct, IPL_BIO, adv_intr, sc);
219 	if (sc->sc_ih == NULL) {
220 		aprint_error_dev(sc->sc_dev,
221 				 "unable to establish interrupt\n");
222 		return;
223 	}
224 
225 	/*
226 	 * Attach.
227 	 */
228 	adv_attach(sc);
229 }
230 
231 int
232 adv_cardbus_detach(device_t self, int flags)
233 {
234 	struct adv_cardbus_softc *csc = device_private(self);
235 	struct asc_softc *sc = &csc->sc_adv;
236 
237 	int rv;
238 
239 	rv = adv_detach(sc, flags);
240 	if (rv)
241 		return rv;
242 
243 	if (sc->sc_ih) {
244 		Cardbus_intr_disestablish(csc->sc_ct, sc->sc_ih);
245 		sc->sc_ih = 0;
246 	}
247 
248 	if (csc->sc_bar != 0) {
249 		Cardbus_mapreg_unmap(csc->sc_ct, csc->sc_bar,
250 		    sc->sc_iot, sc->sc_ioh, csc->sc_size);
251 		csc->sc_bar = 0;
252 	}
253 
254 	return 0;
255 }
256