1 /* $NetBSD: if_cemac.c,v 1.28 2024/07/05 04:31:50 rin Exp $ */ 2 3 /* 4 * Copyright (c) 2015 Genetec Corporation. All rights reserved. 5 * Written by Hashimoto Kenichi for Genetec Corporation. 6 * 7 * Based on arch/arm/at91/at91emac.c 8 * 9 * Copyright (c) 2007 Embedtronics Oy 10 * All rights reserved. 11 * 12 * Copyright (c) 2004 Jesse Off 13 * All rights reserved. 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 /* 38 * Cadence EMAC/GEM ethernet controller IP driver 39 * used by arm/at91, arm/zynq SoC 40 */ 41 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "$NetBSD: if_cemac.c,v 1.28 2024/07/05 04:31:50 rin Exp $"); 44 45 #include <sys/types.h> 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/ioctl.h> 49 #include <sys/kernel.h> 50 #include <sys/proc.h> 51 #include <sys/malloc.h> 52 #include <sys/time.h> 53 #include <sys/device.h> 54 #include <uvm/uvm_extern.h> 55 56 #include <sys/bus.h> 57 #include <machine/intr.h> 58 59 #include <arm/cpufunc.h> 60 61 #include <net/if.h> 62 #include <net/if_dl.h> 63 #include <net/if_types.h> 64 #include <net/if_media.h> 65 #include <net/if_ether.h> 66 #include <net/bpf.h> 67 68 #include <dev/mii/mii.h> 69 #include <dev/mii/miivar.h> 70 71 #ifdef INET 72 #include <netinet/in.h> 73 #include <netinet/in_systm.h> 74 #include <netinet/in_var.h> 75 #include <netinet/ip.h> 76 #include <netinet/if_inarp.h> 77 #endif 78 79 #include <dev/cadence/cemacreg.h> 80 #include <dev/cadence/if_cemacvar.h> 81 82 #define DEFAULT_MDCDIV 32 83 84 #define CEMAC_READ(x) \ 85 bus_space_read_4(sc->sc_iot, sc->sc_ioh, (x)) 86 #define CEMAC_WRITE(x, y) \ 87 bus_space_write_4(sc->sc_iot, sc->sc_ioh, (x), (y)) 88 #define CEMAC_GEM_WRITE(x, y) \ 89 do { \ 90 if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) \ 91 bus_space_write_4(sc->sc_iot, sc->sc_ioh, (GEM_##x), (y)); \ 92 else \ 93 bus_space_write_4(sc->sc_iot, sc->sc_ioh, (ETH_##x), (y)); \ 94 } while(0) 95 96 #define RX_QLEN 64 97 #define TX_QLEN 2 /* I'm very sorry but that's where we can get */ 98 99 struct cemac_qmeta { 100 struct mbuf *m; 101 bus_dmamap_t m_dmamap; 102 }; 103 104 struct cemac_softc { 105 device_t sc_dev; 106 bus_space_tag_t sc_iot; 107 bus_space_handle_t sc_ioh; 108 bus_dma_tag_t sc_dmat; 109 uint8_t sc_enaddr[ETHER_ADDR_LEN]; 110 struct ethercom sc_ethercom; 111 mii_data_t sc_mii; 112 113 void *rbqpage; 114 unsigned rbqlen; 115 bus_addr_t rbqpage_dsaddr; 116 bus_dmamap_t rbqpage_dmamap; 117 void *tbqpage; 118 unsigned tbqlen; 119 bus_addr_t tbqpage_dsaddr; 120 bus_dmamap_t tbqpage_dmamap; 121 122 volatile struct eth_dsc *RDSC; 123 int rxqi; 124 struct cemac_qmeta rxq[RX_QLEN]; 125 volatile struct eth_dsc *TDSC; 126 int txqi, txqc; 127 struct cemac_qmeta txq[TX_QLEN]; 128 callout_t cemac_tick_ch; 129 bool tx_busy; 130 131 int cemac_flags; 132 }; 133 134 static void cemac_init(struct cemac_softc *); 135 static int cemac_gctx(struct cemac_softc *); 136 static int cemac_mediachange(struct ifnet *); 137 static void cemac_mediastatus(struct ifnet *, struct ifmediareq *); 138 static int cemac_mii_readreg(device_t, int, int, uint16_t *); 139 static int cemac_mii_writereg(device_t, int, int, uint16_t); 140 static void cemac_statchg(struct ifnet *); 141 static void cemac_tick(void *); 142 static int cemac_ifioctl(struct ifnet *, u_long, void *); 143 static void cemac_ifstart(struct ifnet *); 144 static void cemac_ifwatchdog(struct ifnet *); 145 static int cemac_ifinit(struct ifnet *); 146 static void cemac_ifstop(struct ifnet *, int); 147 static void cemac_setaddr(struct ifnet *); 148 149 #ifdef CEMAC_DEBUG 150 int cemac_debug = CEMAC_DEBUG; 151 #define DPRINTFN(n, fmt) if (cemac_debug >= (n)) printf fmt 152 #else 153 #define DPRINTFN(n, fmt) 154 #endif 155 156 CFATTACH_DECL_NEW(cemac, sizeof(struct cemac_softc), 157 cemac_match, cemac_attach, NULL, NULL); 158 159 int 160 cemac_match_common(device_t parent, cfdata_t match, void *aux) 161 { 162 if (strcmp(match->cf_name, "cemac") == 0) 163 return 1; 164 return 0; 165 } 166 167 void 168 cemac_attach_common(device_t self, bus_space_tag_t iot, 169 bus_space_handle_t ioh, bus_dma_tag_t dmat, int flags) 170 { 171 struct cemac_softc *sc = device_private(self); 172 prop_data_t enaddr; 173 uint32_t u; 174 175 176 sc->sc_dev = self; 177 sc->sc_ioh = ioh; 178 sc->sc_iot = iot; 179 sc->sc_dmat = dmat; 180 sc->cemac_flags = flags; 181 182 aprint_naive("\n"); 183 if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) 184 aprint_normal(": Cadence Gigabit Ethernet Controller\n"); 185 else 186 aprint_normal(": Cadence Ethernet Controller\n"); 187 188 /* configure emac: */ 189 CEMAC_WRITE(ETH_CTL, 0); // disable everything 190 CEMAC_WRITE(ETH_IDR, -1); // disable interrupts 191 CEMAC_WRITE(ETH_RBQP, 0); // clear receive 192 CEMAC_WRITE(ETH_TBQP, 0); // clear transmit 193 if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) 194 CEMAC_WRITE(ETH_CFG, 195 GEM_CFG_CLK_64 | GEM_CFG_GEN | ETH_CFG_SPD | ETH_CFG_FD); 196 else 197 CEMAC_WRITE(ETH_CFG, 198 ETH_CFG_CLK_32 | ETH_CFG_SPD | ETH_CFG_FD | ETH_CFG_BIG); 199 //CEMAC_WRITE(ETH_TCR, 0); // send nothing 200 //(void)CEMAC_READ(ETH_ISR); 201 u = CEMAC_READ(ETH_TSR); 202 CEMAC_WRITE(ETH_TSR, (u & (ETH_TSR_UND | ETH_TSR_COMP | ETH_TSR_BNQ 203 | ETH_TSR_IDLE | ETH_TSR_RLE 204 | ETH_TSR_COL | ETH_TSR_OVR))); 205 u = CEMAC_READ(ETH_RSR); 206 CEMAC_WRITE(ETH_RSR, (u & (ETH_RSR_OVR | ETH_RSR_REC | ETH_RSR_BNA))); 207 208 /* Fetch the Ethernet address from property if set. */ 209 enaddr = prop_dictionary_get(device_properties(self), "mac-address"); 210 211 if (enaddr != NULL) { 212 KASSERT(prop_object_type(enaddr) == PROP_TYPE_DATA); 213 KASSERT(prop_data_size(enaddr) == ETHER_ADDR_LEN); 214 memcpy(sc->sc_enaddr, prop_data_value(enaddr), 215 ETHER_ADDR_LEN); 216 } else { 217 static const uint8_t hardcoded[ETHER_ADDR_LEN] = { 218 0x00, 0x0d, 0x10, 0x81, 0x0c, 0x94 219 }; 220 memcpy(sc->sc_enaddr, hardcoded, ETHER_ADDR_LEN); 221 } 222 223 cemac_init(sc); 224 } 225 226 static int 227 cemac_gctx(struct cemac_softc *sc) 228 { 229 uint32_t tsr; 230 231 tsr = CEMAC_READ(ETH_TSR); 232 if (!ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) { 233 // no space left 234 if (!(tsr & ETH_TSR_BNQ)) 235 return 0; 236 } else { 237 if (tsr & GEM_TSR_TXGO) 238 return 0; 239 } 240 CEMAC_WRITE(ETH_TSR, tsr); 241 242 // free sent frames 243 while (sc->txqc > (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM) ? 0 : 244 (tsr & ETH_TSR_IDLE ? 0 : 1))) { 245 int bi = sc->txqi % TX_QLEN; 246 247 DPRINTFN(3,("%s: TDSC[%i].Addr 0x%08x\n", 248 __FUNCTION__, bi, sc->TDSC[bi].Addr)); 249 DPRINTFN(3,("%s: TDSC[%i].Info 0x%08x\n", 250 __FUNCTION__, bi, sc->TDSC[bi].Info)); 251 252 bus_dmamap_sync(sc->sc_dmat, sc->txq[bi].m_dmamap, 0, 253 sc->txq[bi].m->m_pkthdr.len, BUS_DMASYNC_POSTWRITE); 254 bus_dmamap_unload(sc->sc_dmat, sc->txq[bi].m_dmamap); 255 m_freem(sc->txq[bi].m); 256 DPRINTFN(2,("%s: freed idx #%i mbuf %p (txqc=%i)\n", 257 __FUNCTION__, bi, sc->txq[bi].m, sc->txqc)); 258 sc->txq[bi].m = NULL; 259 sc->txqi = (bi + 1) % TX_QLEN; 260 sc->txqc--; 261 } 262 263 // mark we're free 264 if (sc->tx_busy) { 265 sc->tx_busy = false; 266 /* Disable transmit-buffer-free interrupt */ 267 /*CEMAC_WRITE(ETH_IDR, ETH_ISR_TBRE);*/ 268 } 269 270 return 1; 271 } 272 273 int 274 cemac_intr(void *arg) 275 { 276 struct cemac_softc *sc = (struct cemac_softc *)arg; 277 struct ifnet * ifp = &sc->sc_ethercom.ec_if; 278 uint32_t imr, isr, ctl; 279 #ifdef CEMAC_DEBUG 280 uint32_t rsr; 281 #endif 282 int bi; 283 284 imr = ~CEMAC_READ(ETH_IMR); 285 if (!(imr & (ETH_ISR_RCOM | ETH_ISR_TBRE | ETH_ISR_TIDLE | 286 ETH_ISR_RBNA | ETH_ISR_ROVR | ETH_ISR_TCOM))) { 287 // interrupt not enabled, can't be us 288 return 0; 289 } 290 291 isr = CEMAC_READ(ETH_ISR); 292 CEMAC_WRITE(ETH_ISR, isr); 293 isr &= imr; 294 #ifdef CEMAC_DEBUG 295 rsr = CEMAC_READ(ETH_RSR); // get receive status register 296 #endif 297 DPRINTFN(2, ("%s: isr=0x%08X rsr=0x%08X imr=0x%08X\n", __FUNCTION__, isr, rsr, imr)); 298 299 net_stat_ref_t nsr = IF_STAT_GETREF(ifp); 300 if (isr & ETH_ISR_RBNA) { // out of receive buffers 301 CEMAC_WRITE(ETH_RSR, ETH_RSR_BNA); // clear interrupt 302 ctl = CEMAC_READ(ETH_CTL); // get current control register value 303 CEMAC_WRITE(ETH_CTL, ctl & ~ETH_CTL_RE); // disable receiver 304 CEMAC_WRITE(ETH_RSR, ETH_RSR_BNA); // clear BNA bit 305 CEMAC_WRITE(ETH_CTL, ctl | ETH_CTL_RE); // re-enable receiver 306 if_statinc_ref(ifp, nsr, if_ierrors); 307 if_statinc_ref(ifp, nsr, if_ipackets); 308 DPRINTFN(1,("%s: out of receive buffers\n", __FUNCTION__)); 309 } 310 if (isr & ETH_ISR_ROVR) { 311 CEMAC_WRITE(ETH_RSR, ETH_RSR_OVR); // clear interrupt 312 if_statinc_ref(ifp, nsr, if_ierrors); 313 if_statinc_ref(ifp, nsr, if_ipackets); 314 DPRINTFN(1,("%s: receive overrun\n", __FUNCTION__)); 315 } 316 317 if (isr & ETH_ISR_RCOM) { // packet has been received! 318 uint32_t nfo; 319 DPRINTFN(2,("#2 RDSC[%i].INFO=0x%08X\n", sc->rxqi % RX_QLEN, sc->RDSC[sc->rxqi % RX_QLEN].Info)); 320 while (sc->RDSC[(bi = sc->rxqi % RX_QLEN)].Addr & ETH_RDSC_F_USED) { 321 int fl, csum; 322 struct mbuf *m; 323 324 nfo = sc->RDSC[bi].Info; 325 fl = (nfo & ETH_RDSC_I_LEN) - 4; 326 DPRINTFN(2,("## nfo=0x%08X\n", nfo)); 327 328 MGETHDR(m, M_DONTWAIT, MT_DATA); 329 if (m != NULL) MCLGET(m, M_DONTWAIT); 330 if (m != NULL && (m->m_flags & M_EXT)) { 331 bus_dmamap_sync(sc->sc_dmat, sc->rxq[bi].m_dmamap, 0, 332 MCLBYTES, BUS_DMASYNC_POSTREAD); 333 bus_dmamap_unload(sc->sc_dmat, 334 sc->rxq[bi].m_dmamap); 335 m_set_rcvif(sc->rxq[bi].m, ifp); 336 sc->rxq[bi].m->m_pkthdr.len = 337 sc->rxq[bi].m->m_len = fl; 338 switch (nfo & ETH_RDSC_I_CHKSUM) { 339 case ETH_RDSC_I_CHKSUM_IP: 340 csum = M_CSUM_IPv4; 341 break; 342 case ETH_RDSC_I_CHKSUM_UDP: 343 csum = M_CSUM_IPv4 | M_CSUM_UDPv4 | 344 M_CSUM_UDPv6; 345 break; 346 case ETH_RDSC_I_CHKSUM_TCP: 347 csum = M_CSUM_IPv4 | M_CSUM_TCPv4 | 348 M_CSUM_TCPv6; 349 break; 350 default: 351 csum = 0; 352 break; 353 } 354 sc->rxq[bi].m->m_pkthdr.csum_flags = csum; 355 DPRINTFN(2,("received %u bytes packet\n", fl)); 356 if_percpuq_enqueue(ifp->if_percpuq, 357 sc->rxq[bi].m); 358 if (mtod(m, intptr_t) & 3) 359 m_adj(m, mtod(m, intptr_t) & 3); 360 sc->rxq[bi].m = m; 361 bus_dmamap_load(sc->sc_dmat, 362 sc->rxq[bi].m_dmamap, 363 m->m_ext.ext_buf, MCLBYTES, 364 NULL, BUS_DMA_NOWAIT); 365 bus_dmamap_sync(sc->sc_dmat, sc->rxq[bi].m_dmamap, 0, 366 MCLBYTES, BUS_DMASYNC_PREREAD); 367 sc->RDSC[bi].Info = 0; 368 sc->RDSC[bi].Addr = 369 sc->rxq[bi].m_dmamap->dm_segs[0].ds_addr 370 | (bi == (RX_QLEN-1) ? ETH_RDSC_F_WRAP : 0); 371 } else { 372 /* Drop packets until we can get replacement 373 * empty mbufs for the RXDQ. 374 */ 375 m_freem(m); 376 if_statinc_ref(ifp, nsr, if_ierrors); 377 } 378 sc->rxqi++; 379 } 380 } 381 382 IF_STAT_PUTREF(ifp); 383 384 if (cemac_gctx(sc) > 0) 385 if_schedule_deferred_start(ifp); 386 #if 0 // reloop 387 irq = CEMAC_READ(IntStsC); 388 if ((irq & (IntSts_RxSQ | IntSts_ECI)) != 0) 389 goto begin; 390 #endif 391 392 return (1); 393 } 394 395 396 static void 397 cemac_init(struct cemac_softc *sc) 398 { 399 bus_dma_segment_t segs; 400 int rsegs, err, i; 401 struct ifnet * ifp = &sc->sc_ethercom.ec_if; 402 struct mii_data * const mii = &sc->sc_mii; 403 uint32_t u; 404 #if 0 405 int mdcdiv = DEFAULT_MDCDIV; 406 #endif 407 408 callout_init(&sc->cemac_tick_ch, 0); 409 410 // ok... 411 CEMAC_WRITE(ETH_CTL, ETH_CTL_MPE); // disable everything 412 CEMAC_WRITE(ETH_IDR, -1); // disable interrupts 413 CEMAC_WRITE(ETH_RBQP, 0); // clear receive 414 CEMAC_WRITE(ETH_TBQP, 0); // clear transmit 415 if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) 416 CEMAC_WRITE(ETH_CFG, 417 GEM_CFG_CLK_64 | ETH_CFG_SPD | ETH_CFG_FD | ETH_CFG_BIG); 418 else 419 CEMAC_WRITE(ETH_CFG, 420 ETH_CFG_CLK_32 | ETH_CFG_SPD | ETH_CFG_FD | ETH_CFG_BIG); 421 if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) { 422 CEMAC_WRITE(GEM_DMA_CFG, 423 __SHIFTIN((MCLBYTES + 63) / 64, GEM_DMA_CFG_RX_BUF_SIZE) | 424 __SHIFTIN(3, GEM_DMA_CFG_RX_PKTBUF_MEMSZ_SEL) | 425 GEM_DMA_CFG_TX_PKTBUF_MEMSZ_SEL | 426 __SHIFTIN(16, GEM_DMA_CFG_AHB_FIXED_BURST_LEN) | 427 GEM_DMA_CFG_DISC_WHEN_NO_AHB); 428 } 429 // CEMAC_WRITE(ETH_TCR, 0); // send nothing 430 // (void)CEMAC_READ(ETH_ISR); 431 u = CEMAC_READ(ETH_TSR); 432 CEMAC_WRITE(ETH_TSR, (u & (ETH_TSR_UND | ETH_TSR_COMP | ETH_TSR_BNQ 433 | ETH_TSR_IDLE | ETH_TSR_RLE 434 | ETH_TSR_COL | ETH_TSR_OVR))); 435 u = CEMAC_READ(ETH_RSR); 436 CEMAC_WRITE(ETH_RSR, (u & (ETH_RSR_OVR | ETH_RSR_REC | ETH_RSR_BNA))); 437 438 #if 0 439 if (device_cfdata(sc->sc_dev)->cf_flags) 440 mdcdiv = device_cfdata(sc->sc_dev)->cf_flags; 441 #endif 442 /* set ethernet address */ 443 CEMAC_GEM_WRITE(SA1L, (sc->sc_enaddr[3] << 24) 444 | (sc->sc_enaddr[2] << 16) | (sc->sc_enaddr[1] << 8) 445 | (sc->sc_enaddr[0])); 446 CEMAC_GEM_WRITE(SA1H, (sc->sc_enaddr[5] << 8) 447 | (sc->sc_enaddr[4])); 448 CEMAC_GEM_WRITE(SA2L, 0); 449 CEMAC_GEM_WRITE(SA2H, 0); 450 CEMAC_GEM_WRITE(SA3L, 0); 451 CEMAC_GEM_WRITE(SA3H, 0); 452 CEMAC_GEM_WRITE(SA4L, 0); 453 CEMAC_GEM_WRITE(SA4H, 0); 454 455 /* Allocate a page of memory for receive queue descriptors */ 456 sc->rbqlen = (ETH_DSC_SIZE * (RX_QLEN + 1) * 2 + PAGE_SIZE - 1) / PAGE_SIZE; 457 sc->rbqlen *= PAGE_SIZE; 458 DPRINTFN(1,("%s: rbqlen=%i\n", __FUNCTION__, sc->rbqlen)); 459 460 err = bus_dmamem_alloc(sc->sc_dmat, sc->rbqlen, 0, 461 MAX(16384, PAGE_SIZE), // see EMAC errata why forced to 16384 byte boundary 462 &segs, 1, &rsegs, BUS_DMA_WAITOK); 463 if (err == 0) { 464 DPRINTFN(1,("%s: -> bus_dmamem_map\n", __FUNCTION__)); 465 err = bus_dmamem_map(sc->sc_dmat, &segs, 1, sc->rbqlen, 466 &sc->rbqpage, (BUS_DMA_WAITOK | BUS_DMA_COHERENT)); 467 } 468 if (err == 0) { 469 DPRINTFN(1,("%s: -> bus_dmamap_create\n", __FUNCTION__)); 470 err = bus_dmamap_create(sc->sc_dmat, sc->rbqlen, 1, 471 sc->rbqlen, MAX(16384, PAGE_SIZE), BUS_DMA_WAITOK, 472 &sc->rbqpage_dmamap); 473 } 474 if (err == 0) { 475 DPRINTFN(1,("%s: -> bus_dmamap_load\n", __FUNCTION__)); 476 err = bus_dmamap_load(sc->sc_dmat, sc->rbqpage_dmamap, 477 sc->rbqpage, sc->rbqlen, NULL, BUS_DMA_WAITOK); 478 } 479 if (err != 0) 480 panic("%s: Cannot get DMA memory", device_xname(sc->sc_dev)); 481 482 sc->rbqpage_dsaddr = sc->rbqpage_dmamap->dm_segs[0].ds_addr; 483 memset(sc->rbqpage, 0, sc->rbqlen); 484 485 /* Allocate a page of memory for transmit queue descriptors */ 486 sc->tbqlen = (ETH_DSC_SIZE * (TX_QLEN + 1) * 2 + PAGE_SIZE - 1) / PAGE_SIZE; 487 sc->tbqlen *= PAGE_SIZE; 488 DPRINTFN(1,("%s: tbqlen=%i\n", __FUNCTION__, sc->tbqlen)); 489 490 err = bus_dmamem_alloc(sc->sc_dmat, sc->tbqlen, 0, 491 MAX(16384, PAGE_SIZE), // see EMAC errata why forced to 16384 byte boundary 492 &segs, 1, &rsegs, BUS_DMA_WAITOK); 493 if (err == 0) { 494 DPRINTFN(1,("%s: -> bus_dmamem_map\n", __FUNCTION__)); 495 err = bus_dmamem_map(sc->sc_dmat, &segs, 1, sc->tbqlen, 496 &sc->tbqpage, (BUS_DMA_WAITOK | BUS_DMA_COHERENT)); 497 } 498 if (err == 0) { 499 DPRINTFN(1,("%s: -> bus_dmamap_create\n", __FUNCTION__)); 500 err = bus_dmamap_create(sc->sc_dmat, sc->tbqlen, 1, 501 sc->tbqlen, MAX(16384, PAGE_SIZE), BUS_DMA_WAITOK, 502 &sc->tbqpage_dmamap); 503 } 504 if (err == 0) { 505 DPRINTFN(1,("%s: -> bus_dmamap_load\n", __FUNCTION__)); 506 err = bus_dmamap_load(sc->sc_dmat, sc->tbqpage_dmamap, 507 sc->tbqpage, sc->tbqlen, NULL, BUS_DMA_WAITOK); 508 } 509 if (err != 0) 510 panic("%s: Cannot get DMA memory", device_xname(sc->sc_dev)); 511 512 sc->tbqpage_dsaddr = sc->tbqpage_dmamap->dm_segs[0].ds_addr; 513 memset(sc->tbqpage, 0, sc->tbqlen); 514 515 /* Set up pointers to start of each queue in kernel addr space. 516 * Each descriptor queue or status queue entry uses 2 words 517 */ 518 sc->RDSC = (void *)sc->rbqpage; 519 sc->TDSC = (void *)sc->tbqpage; 520 521 /* init TX queue */ 522 for (i = 0; i < TX_QLEN; i++) { 523 sc->TDSC[i].Addr = 0; 524 sc->TDSC[i].Info = ETH_TDSC_I_USED | 525 (i == (TX_QLEN - 1) ? ETH_TDSC_I_WRAP : 0); 526 } 527 528 /* Populate the RXQ with mbufs */ 529 sc->rxqi = 0; 530 for (i = 0; i < RX_QLEN; i++) { 531 struct mbuf *m; 532 533 err = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, PAGE_SIZE, 534 BUS_DMA_WAITOK, &sc->rxq[i].m_dmamap); 535 if (err) { 536 panic("%s: dmamap_create failed: %i\n", __FUNCTION__, err); 537 } 538 MGETHDR(m, M_WAIT, MT_DATA); 539 MCLGET(m, M_WAIT); 540 sc->rxq[i].m = m; 541 if (mtod(m, intptr_t) & 3) { 542 m_adj(m, mtod(m, intptr_t) & 3); 543 } 544 err = bus_dmamap_load(sc->sc_dmat, sc->rxq[i].m_dmamap, 545 m->m_ext.ext_buf, MCLBYTES, NULL, 546 BUS_DMA_WAITOK); 547 if (err) { 548 panic("%s: dmamap_load failed: %i\n", __FUNCTION__, err); 549 } 550 sc->RDSC[i].Addr = sc->rxq[i].m_dmamap->dm_segs[0].ds_addr 551 | (i == (RX_QLEN-1) ? ETH_RDSC_F_WRAP : 0); 552 sc->RDSC[i].Info = 0; 553 bus_dmamap_sync(sc->sc_dmat, sc->rxq[i].m_dmamap, 0, 554 MCLBYTES, BUS_DMASYNC_PREREAD); 555 } 556 557 /* prepare transmit queue */ 558 for (i = 0; i < TX_QLEN; i++) { 559 err = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 0, 560 (BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW), 561 &sc->txq[i].m_dmamap); 562 if (err) 563 panic("ARGH #1"); 564 sc->txq[i].m = NULL; 565 } 566 567 /* Program each queue's start addr, cur addr, and len registers 568 * with the physical addresses. 569 */ 570 CEMAC_WRITE(ETH_RBQP, (uint32_t)sc->rbqpage_dsaddr); 571 CEMAC_WRITE(ETH_TBQP, (uint32_t)sc->tbqpage_dsaddr); 572 573 /* Divide HCLK by 32 for MDC clock */ 574 sc->sc_ethercom.ec_mii = mii; 575 mii->mii_ifp = ifp; 576 mii->mii_readreg = cemac_mii_readreg; 577 mii->mii_writereg = cemac_mii_writereg; 578 mii->mii_statchg = cemac_statchg; 579 ifmedia_init(&mii->mii_media, IFM_IMASK, cemac_mediachange, 580 cemac_mediastatus); 581 mii_attach(sc->sc_dev, mii, 0xffffffff, MII_PHY_ANY, 1, 0); 582 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 583 584 #if 0 585 // enable / disable interrupts 586 CEMAC_WRITE(ETH_IDR, -1); 587 CEMAC_WRITE(ETH_IER, ETH_ISR_RCOM | ETH_ISR_TBRE | ETH_ISR_TIDLE 588 | ETH_ISR_RBNA | ETH_ISR_ROVR | ETH_ISR_TCOM); 589 // (void)CEMAC_READ(ETH_ISR); // why 590 591 // enable transmitter / receiver 592 CEMAC_WRITE(ETH_CTL, ETH_CTL_TE | ETH_CTL_RE | ETH_CTL_ISR 593 | ETH_CTL_CSR | ETH_CTL_MPE); 594 #endif 595 /* 596 * We can support hardware checksumming. 597 */ 598 ifp->if_capabilities |= 599 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 600 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 601 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx | 602 IFCAP_CSUM_TCPv6_Tx | IFCAP_CSUM_TCPv6_Rx | 603 IFCAP_CSUM_UDPv6_Tx | IFCAP_CSUM_UDPv6_Rx; 604 605 /* 606 * We can support 802.1Q VLAN-sized frames. 607 */ 608 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 609 610 strcpy(ifp->if_xname, device_xname(sc->sc_dev)); 611 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 612 ifp->if_ioctl = cemac_ifioctl; 613 ifp->if_start = cemac_ifstart; 614 ifp->if_watchdog = cemac_ifwatchdog; 615 ifp->if_init = cemac_ifinit; 616 ifp->if_stop = cemac_ifstop; 617 ifp->if_timer = 0; 618 ifp->if_softc = sc; 619 IFQ_SET_READY(&ifp->if_snd); 620 if_attach(ifp); 621 if_deferred_start_init(ifp, NULL); 622 ether_ifattach(ifp, (sc)->sc_enaddr); 623 } 624 625 static int 626 cemac_mediachange(struct ifnet *ifp) 627 { 628 if (ifp->if_flags & IFF_UP) 629 cemac_ifinit(ifp); 630 return (0); 631 } 632 633 static void 634 cemac_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 635 { 636 struct cemac_softc *sc = ifp->if_softc; 637 638 mii_pollstat(&sc->sc_mii); 639 ifmr->ifm_active = sc->sc_mii.mii_media_active; 640 ifmr->ifm_status = sc->sc_mii.mii_media_status; 641 } 642 643 644 static int 645 cemac_mii_readreg(device_t self, int phy, int reg, uint16_t *val) 646 { 647 struct cemac_softc *sc; 648 649 sc = device_private(self); 650 651 CEMAC_WRITE(ETH_MAN, (ETH_MAN_HIGH | ETH_MAN_RW_RD 652 | ((phy << ETH_MAN_PHYA_SHIFT) & ETH_MAN_PHYA) 653 | ((reg << ETH_MAN_REGA_SHIFT) & ETH_MAN_REGA) 654 | ETH_MAN_CODE_IEEE802_3)); 655 while (!(CEMAC_READ(ETH_SR) & ETH_SR_IDLE)) 656 ; 657 658 *val = CEMAC_READ(ETH_MAN) & ETH_MAN_DATA; 659 return 0; 660 } 661 662 static int 663 cemac_mii_writereg(device_t self, int phy, int reg, uint16_t val) 664 { 665 struct cemac_softc *sc; 666 667 sc = device_private(self); 668 669 CEMAC_WRITE(ETH_MAN, (ETH_MAN_HIGH | ETH_MAN_RW_WR 670 | ((phy << ETH_MAN_PHYA_SHIFT) & ETH_MAN_PHYA) 671 | ((reg << ETH_MAN_REGA_SHIFT) & ETH_MAN_REGA) 672 | ETH_MAN_CODE_IEEE802_3 673 | (val & ETH_MAN_DATA))); 674 while (!(CEMAC_READ(ETH_SR) & ETH_SR_IDLE)) 675 ; 676 677 return 0; 678 } 679 680 681 static void 682 cemac_statchg(struct ifnet *ifp) 683 { 684 struct cemac_softc *sc = ifp->if_softc; 685 struct mii_data *mii = &sc->sc_mii; 686 uint32_t reg; 687 688 /* 689 * We must keep the MAC and the PHY in sync as 690 * to the status of full-duplex! 691 */ 692 reg = CEMAC_READ(ETH_CFG); 693 reg &= ~ETH_CFG_FD; 694 if (sc->sc_mii.mii_media_active & IFM_FDX) 695 reg |= ETH_CFG_FD; 696 697 reg &= ~ETH_CFG_SPD; 698 if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) 699 reg &= ~GEM_CFG_GEN; 700 switch (IFM_SUBTYPE(mii->mii_media_active)) { 701 case IFM_10_T: 702 break; 703 case IFM_100_TX: 704 reg |= ETH_CFG_SPD; 705 break; 706 case IFM_1000_T: 707 reg |= ETH_CFG_SPD | GEM_CFG_GEN; 708 break; 709 default: 710 break; 711 } 712 CEMAC_WRITE(ETH_CFG, reg); 713 } 714 715 static void 716 cemac_tick(void *arg) 717 { 718 struct cemac_softc* sc = (struct cemac_softc *)arg; 719 struct ifnet * ifp = &sc->sc_ethercom.ec_if; 720 int s; 721 722 if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) 723 if_statadd(ifp, if_collisions, 724 CEMAC_READ(GEM_SCOL) + CEMAC_READ(GEM_MCOL)); 725 else 726 if_statadd(ifp, if_collisions, 727 CEMAC_READ(ETH_SCOL) + CEMAC_READ(ETH_MCOL)); 728 729 /* These misses are ok, they will happen if the RAM/CPU can't keep up */ 730 if (!ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) { 731 uint32_t misses = CEMAC_READ(ETH_DRFC); 732 if (misses > 0) 733 aprint_normal_ifnet(ifp, "%d rx misses\n", misses); 734 } 735 736 s = splnet(); 737 if (cemac_gctx(sc) > 0 && IFQ_IS_EMPTY(&ifp->if_snd) == 0) 738 cemac_ifstart(ifp); 739 splx(s); 740 741 mii_tick(&sc->sc_mii); 742 callout_reset(&sc->cemac_tick_ch, hz, cemac_tick, sc); 743 } 744 745 746 static int 747 cemac_ifioctl(struct ifnet *ifp, u_long cmd, void *data) 748 { 749 int s, error; 750 751 s = splnet(); 752 switch (cmd) { 753 default: 754 error = ether_ioctl(ifp, cmd, data); 755 if (error != ENETRESET) 756 break; 757 error = 0; 758 759 if (cmd == SIOCSIFCAP) { 760 error = if_init(ifp); 761 } else if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 762 ; 763 else if (ifp->if_flags & IFF_RUNNING) { 764 cemac_setaddr(ifp); 765 } 766 } 767 splx(s); 768 return error; 769 } 770 771 static void 772 cemac_ifstart(struct ifnet *ifp) 773 { 774 struct cemac_softc *sc = (struct cemac_softc *)ifp->if_softc; 775 struct mbuf *m; 776 bus_dma_segment_t *segs; 777 int s, bi, err, nsegs; 778 779 s = splnet(); 780 start: 781 if (cemac_gctx(sc) == 0) { 782 /* Enable transmit-buffer-free interrupt */ 783 CEMAC_WRITE(ETH_IER, ETH_ISR_TBRE); 784 sc->tx_busy = true; 785 ifp->if_timer = 10; 786 splx(s); 787 return; 788 } 789 790 ifp->if_timer = 0; 791 792 IFQ_POLL(&ifp->if_snd, m); 793 if (m == NULL) { 794 splx(s); 795 return; 796 } 797 798 bi = (sc->txqi + sc->txqc) % TX_QLEN; 799 if ((err = bus_dmamap_load_mbuf(sc->sc_dmat, sc->txq[bi].m_dmamap, m, 800 BUS_DMA_NOWAIT)) || 801 sc->txq[bi].m_dmamap->dm_segs[0].ds_addr & 0x3 || 802 sc->txq[bi].m_dmamap->dm_nsegs > 1) { 803 /* Copy entire mbuf chain to new single */ 804 struct mbuf *mn; 805 806 if (err == 0) 807 bus_dmamap_unload(sc->sc_dmat, sc->txq[bi].m_dmamap); 808 809 MGETHDR(mn, M_DONTWAIT, MT_DATA); 810 if (mn == NULL) goto stop; 811 if (m->m_pkthdr.len > MHLEN) { 812 MCLGET(mn, M_DONTWAIT); 813 if ((mn->m_flags & M_EXT) == 0) { 814 m_freem(mn); 815 goto stop; 816 } 817 } 818 m_copydata(m, 0, m->m_pkthdr.len, mtod(mn, void *)); 819 mn->m_pkthdr.len = mn->m_len = m->m_pkthdr.len; 820 IFQ_DEQUEUE(&ifp->if_snd, m); 821 m_freem(m); 822 m = mn; 823 bus_dmamap_load_mbuf(sc->sc_dmat, sc->txq[bi].m_dmamap, m, 824 BUS_DMA_NOWAIT); 825 } else { 826 IFQ_DEQUEUE(&ifp->if_snd, m); 827 } 828 829 bpf_mtap(ifp, m, BPF_D_OUT); 830 831 nsegs = sc->txq[bi].m_dmamap->dm_nsegs; 832 segs = sc->txq[bi].m_dmamap->dm_segs; 833 if (nsegs > 1) 834 panic("#### ARGH #2"); 835 836 sc->txq[bi].m = m; 837 sc->txqc++; 838 839 DPRINTFN(2,("%s: start sending idx #%i mbuf %p (txqc=%i, phys %p), len=%u\n", 840 __FUNCTION__, bi, sc->txq[bi].m, sc->txqc, (void*)segs->ds_addr, 841 (unsigned)m->m_pkthdr.len)); 842 #ifdef DIAGNOSTIC 843 if (sc->txqc > TX_QLEN) 844 panic("%s: txqc %i > %i", __FUNCTION__, sc->txqc, TX_QLEN); 845 #endif 846 847 bus_dmamap_sync(sc->sc_dmat, sc->txq[bi].m_dmamap, 0, 848 sc->txq[bi].m_dmamap->dm_mapsize, 849 BUS_DMASYNC_PREWRITE); 850 851 if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) { 852 sc->TDSC[bi].Addr = segs->ds_addr; 853 sc->TDSC[bi].Info = __SHIFTIN(m->m_pkthdr.len, ETH_TDSC_I_LEN) | 854 ETH_TDSC_I_LAST_BUF | (bi == (TX_QLEN - 1) ? ETH_TDSC_I_WRAP : 0); 855 856 DPRINTFN(3,("%s: TDSC[%i].Addr 0x%08x\n", 857 __FUNCTION__, bi, sc->TDSC[bi].Addr)); 858 DPRINTFN(3,("%s: TDSC[%i].Info 0x%08x\n", 859 __FUNCTION__, bi, sc->TDSC[bi].Info)); 860 861 uint32_t ctl = CEMAC_READ(ETH_CTL) | GEM_CTL_STARTTX; 862 CEMAC_WRITE(ETH_CTL, ctl); 863 DPRINTFN(3,("%s: ETH_CTL 0x%08x\n", __FUNCTION__, CEMAC_READ(ETH_CTL))); 864 } else { 865 CEMAC_WRITE(ETH_TAR, segs->ds_addr); 866 CEMAC_WRITE(ETH_TCR, m->m_pkthdr.len); 867 } 868 if (IFQ_IS_EMPTY(&ifp->if_snd) == 0) 869 goto start; 870 stop: 871 872 splx(s); 873 return; 874 } 875 876 static void 877 cemac_ifwatchdog(struct ifnet *ifp) 878 { 879 struct cemac_softc *sc = (struct cemac_softc *)ifp->if_softc; 880 881 if ((ifp->if_flags & IFF_RUNNING) == 0) 882 return; 883 aprint_error_ifnet(ifp, "device timeout, CTL = 0x%08x, CFG = 0x%08x\n", 884 CEMAC_READ(ETH_CTL), CEMAC_READ(ETH_CFG)); 885 } 886 887 static int 888 cemac_ifinit(struct ifnet *ifp) 889 { 890 struct cemac_softc *sc = ifp->if_softc; 891 uint32_t dma, cfg; 892 int s = splnet(); 893 894 callout_stop(&sc->cemac_tick_ch); 895 896 if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) { 897 898 if (ifp->if_capenable & 899 (IFCAP_CSUM_IPv4_Tx | 900 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_UDPv4_Tx | 901 IFCAP_CSUM_TCPv6_Tx | IFCAP_CSUM_UDPv6_Tx)) { 902 dma = CEMAC_READ(GEM_DMA_CFG); 903 dma |= GEM_DMA_CFG_CHKSUM_GEN_OFFLOAD_EN; 904 CEMAC_WRITE(GEM_DMA_CFG, dma); 905 } 906 if (ifp->if_capenable & 907 (IFCAP_CSUM_IPv4_Rx | 908 IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx | 909 IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx)) { 910 cfg = CEMAC_READ(ETH_CFG); 911 cfg |= GEM_CFG_RX_CHKSUM_OFFLD_EN; 912 CEMAC_WRITE(ETH_CFG, cfg); 913 } 914 } 915 916 // enable interrupts 917 CEMAC_WRITE(ETH_IDR, -1); 918 CEMAC_WRITE(ETH_IER, ETH_ISR_RCOM | ETH_ISR_TBRE | ETH_ISR_TIDLE 919 | ETH_ISR_RBNA | ETH_ISR_ROVR | ETH_ISR_TCOM); 920 921 // enable transmitter / receiver 922 CEMAC_WRITE(ETH_CTL, ETH_CTL_TE | ETH_CTL_RE | ETH_CTL_ISR 923 | ETH_CTL_CSR | ETH_CTL_MPE); 924 925 mii_mediachg(&sc->sc_mii); 926 callout_reset(&sc->cemac_tick_ch, hz, cemac_tick, sc); 927 ifp->if_flags |= IFF_RUNNING; 928 splx(s); 929 return 0; 930 } 931 932 static void 933 cemac_ifstop(struct ifnet *ifp, int disable) 934 { 935 // uint32_t u; 936 struct cemac_softc *sc = ifp->if_softc; 937 938 #if 0 939 CEMAC_WRITE(ETH_CTL, ETH_CTL_MPE); // disable everything 940 CEMAC_WRITE(ETH_IDR, -1); // disable interrupts 941 // CEMAC_WRITE(ETH_RBQP, 0); // clear receive 942 if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) 943 CEMAC_WRITE(ETH_CFG, 944 GEM_CFG_CLK_64 | ETH_CFG_SPD | ETH_CFG_FD | ETH_CFG_BIG); 945 else 946 CEMAC_WRITE(ETH_CFG, 947 ETH_CFG_CLK_32 | ETH_CFG_SPD | ETH_CFG_FD | ETH_CFG_BIG); 948 // CEMAC_WRITE(ETH_TCR, 0); // send nothing 949 // (void)CEMAC_READ(ETH_ISR); 950 u = CEMAC_READ(ETH_TSR); 951 CEMAC_WRITE(ETH_TSR, (u & (ETH_TSR_UND | ETH_TSR_COMP | ETH_TSR_BNQ 952 | ETH_TSR_IDLE | ETH_TSR_RLE 953 | ETH_TSR_COL | ETH_TSR_OVR))); 954 u = CEMAC_READ(ETH_RSR); 955 CEMAC_WRITE(ETH_RSR, (u & (ETH_RSR_OVR | ETH_RSR_REC | ETH_RSR_BNA))); 956 #endif 957 callout_stop(&sc->cemac_tick_ch); 958 959 /* Down the MII. */ 960 mii_down(&sc->sc_mii); 961 962 ifp->if_flags &= ~IFF_RUNNING; 963 ifp->if_timer = 0; 964 sc->tx_busy = false; 965 sc->sc_mii.mii_media_status &= ~IFM_ACTIVE; 966 } 967 968 static void 969 cemac_setaddr(struct ifnet *ifp) 970 { 971 struct cemac_softc *sc = ifp->if_softc; 972 struct ethercom *ec = &sc->sc_ethercom; 973 struct ether_multi *enm; 974 struct ether_multistep step; 975 uint8_t ias[3][ETHER_ADDR_LEN]; 976 uint32_t h, nma = 0, hashes[2] = { 0, 0 }; 977 uint32_t ctl = CEMAC_READ(ETH_CTL); 978 uint32_t cfg = CEMAC_READ(ETH_CFG); 979 980 /* disable receiver temporarily */ 981 CEMAC_WRITE(ETH_CTL, ctl & ~ETH_CTL_RE); 982 983 cfg &= ~(ETH_CFG_MTI | ETH_CFG_UNI | ETH_CFG_CAF | ETH_CFG_UNI); 984 985 if (ifp->if_flags & IFF_PROMISC) { 986 cfg |= ETH_CFG_CAF; 987 } else { 988 cfg &= ~ETH_CFG_CAF; 989 } 990 991 // ETH_CFG_BIG? 992 993 ifp->if_flags &= ~IFF_ALLMULTI; 994 995 ETHER_LOCK(ec); 996 ETHER_FIRST_MULTI(step, ec, enm); 997 while (enm != NULL) { 998 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 999 /* 1000 * We must listen to a range of multicast addresses. 1001 * For now, just accept all multicasts, rather than 1002 * trying to set only those filter bits needed to match 1003 * the range. (At this time, the only use of address 1004 * ranges is for IP multicast routing, for which the 1005 * range is big enough to require all bits set.) 1006 */ 1007 cfg |= ETH_CFG_MTI; 1008 hashes[0] = 0xffffffffUL; 1009 hashes[1] = 0xffffffffUL; 1010 ifp->if_flags |= IFF_ALLMULTI; 1011 nma = 0; 1012 break; 1013 } 1014 1015 if (nma < 3) { 1016 /* We can program 3 perfect address filters for mcast */ 1017 memcpy(ias[nma], enm->enm_addrlo, ETHER_ADDR_LEN); 1018 } else { 1019 /* 1020 * XXX: Datasheet is not very clear here, I'm not sure 1021 * if I'm doing this right. --joff 1022 */ 1023 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 1024 1025 /* Just want the 6 most-significant bits. */ 1026 h = h >> 26; 1027 #if 0 1028 hashes[h / 32] |= (1 << (h % 32)); 1029 #else 1030 hashes[0] = 0xffffffffUL; 1031 hashes[1] = 0xffffffffUL; 1032 #endif 1033 cfg |= ETH_CFG_MTI; 1034 } 1035 ETHER_NEXT_MULTI(step, enm); 1036 nma++; 1037 } 1038 ETHER_UNLOCK(ec); 1039 1040 // program... 1041 DPRINTFN(1,("%s: en0 %02x:%02x:%02x:%02x:%02x:%02x\n", __FUNCTION__, 1042 sc->sc_enaddr[0], sc->sc_enaddr[1], sc->sc_enaddr[2], 1043 sc->sc_enaddr[3], sc->sc_enaddr[4], sc->sc_enaddr[5])); 1044 CEMAC_GEM_WRITE(SA1L, (sc->sc_enaddr[3] << 24) 1045 | (sc->sc_enaddr[2] << 16) | (sc->sc_enaddr[1] << 8) 1046 | (sc->sc_enaddr[0])); 1047 CEMAC_GEM_WRITE(SA1H, (sc->sc_enaddr[5] << 8) 1048 | (sc->sc_enaddr[4])); 1049 if (nma > 0) { 1050 DPRINTFN(1,("%s: en1 %02x:%02x:%02x:%02x:%02x:%02x\n", __FUNCTION__, 1051 ias[0][0], ias[0][1], ias[0][2], 1052 ias[0][3], ias[0][4], ias[0][5])); 1053 CEMAC_WRITE(ETH_SA2L, (ias[0][3] << 24) 1054 | (ias[0][2] << 16) | (ias[0][1] << 8) 1055 | (ias[0][0])); 1056 CEMAC_WRITE(ETH_SA2H, (ias[0][4] << 8) 1057 | (ias[0][5])); 1058 } 1059 if (nma > 1) { 1060 DPRINTFN(1,("%s: en2 %02x:%02x:%02x:%02x:%02x:%02x\n", __FUNCTION__, 1061 ias[1][0], ias[1][1], ias[1][2], 1062 ias[1][3], ias[1][4], ias[1][5])); 1063 CEMAC_WRITE(ETH_SA3L, (ias[1][3] << 24) 1064 | (ias[1][2] << 16) | (ias[1][1] << 8) 1065 | (ias[1][0])); 1066 CEMAC_WRITE(ETH_SA3H, (ias[1][4] << 8) 1067 | (ias[1][5])); 1068 } 1069 if (nma > 2) { 1070 DPRINTFN(1,("%s: en3 %02x:%02x:%02x:%02x:%02x:%02x\n", __FUNCTION__, 1071 ias[2][0], ias[2][1], ias[2][2], 1072 ias[2][3], ias[2][4], ias[2][5])); 1073 CEMAC_WRITE(ETH_SA4L, (ias[2][3] << 24) 1074 | (ias[2][2] << 16) | (ias[2][1] << 8) 1075 | (ias[2][0])); 1076 CEMAC_WRITE(ETH_SA4H, (ias[2][4] << 8) 1077 | (ias[2][5])); 1078 } 1079 CEMAC_GEM_WRITE(HSH, hashes[0]); 1080 CEMAC_GEM_WRITE(HSL, hashes[1]); 1081 CEMAC_WRITE(ETH_CFG, cfg); 1082 CEMAC_WRITE(ETH_CTL, ctl | ETH_CTL_RE); 1083 } 1084