1 /* $NetBSD: if_cemac.c,v 1.23 2020/06/28 12:43:00 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2015 Genetec Corporation. All rights reserved. 5 * Written by Hashimoto Kenichi for Genetec Corporation. 6 * 7 * Based on arch/arm/at91/at91emac.c 8 * 9 * Copyright (c) 2007 Embedtronics Oy 10 * All rights reserved. 11 * 12 * Copyright (c) 2004 Jesse Off 13 * All rights reserved. 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 /* 38 * Cadence EMAC/GEM ethernet controller IP driver 39 * used by arm/at91, arm/zynq SoC 40 */ 41 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "$NetBSD: if_cemac.c,v 1.23 2020/06/28 12:43:00 skrll Exp $"); 44 45 #include <sys/types.h> 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/ioctl.h> 49 #include <sys/kernel.h> 50 #include <sys/proc.h> 51 #include <sys/malloc.h> 52 #include <sys/time.h> 53 #include <sys/device.h> 54 #include <uvm/uvm_extern.h> 55 56 #include <sys/bus.h> 57 #include <machine/intr.h> 58 59 #include <arm/cpufunc.h> 60 61 #include <net/if.h> 62 #include <net/if_dl.h> 63 #include <net/if_types.h> 64 #include <net/if_media.h> 65 #include <net/if_ether.h> 66 #include <net/bpf.h> 67 68 #include <dev/mii/mii.h> 69 #include <dev/mii/miivar.h> 70 71 #ifdef INET 72 #include <netinet/in.h> 73 #include <netinet/in_systm.h> 74 #include <netinet/in_var.h> 75 #include <netinet/ip.h> 76 #include <netinet/if_inarp.h> 77 #endif 78 79 #include <dev/cadence/cemacreg.h> 80 #include <dev/cadence/if_cemacvar.h> 81 82 #define DEFAULT_MDCDIV 32 83 84 #define CEMAC_READ(x) \ 85 bus_space_read_4(sc->sc_iot, sc->sc_ioh, (x)) 86 #define CEMAC_WRITE(x, y) \ 87 bus_space_write_4(sc->sc_iot, sc->sc_ioh, (x), (y)) 88 #define CEMAC_GEM_WRITE(x, y) \ 89 do { \ 90 if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) \ 91 bus_space_write_4(sc->sc_iot, sc->sc_ioh, (GEM_##x), (y)); \ 92 else \ 93 bus_space_write_4(sc->sc_iot, sc->sc_ioh, (ETH_##x), (y)); \ 94 } while(0) 95 96 #define RX_QLEN 64 97 #define TX_QLEN 2 /* I'm very sorry but that's where we can get */ 98 99 struct cemac_qmeta { 100 struct mbuf *m; 101 bus_dmamap_t m_dmamap; 102 }; 103 104 struct cemac_softc { 105 device_t sc_dev; 106 bus_space_tag_t sc_iot; 107 bus_space_handle_t sc_ioh; 108 bus_dma_tag_t sc_dmat; 109 uint8_t sc_enaddr[ETHER_ADDR_LEN]; 110 struct ethercom sc_ethercom; 111 mii_data_t sc_mii; 112 113 void *rbqpage; 114 unsigned rbqlen; 115 bus_addr_t rbqpage_dsaddr; 116 bus_dmamap_t rbqpage_dmamap; 117 void *tbqpage; 118 unsigned tbqlen; 119 bus_addr_t tbqpage_dsaddr; 120 bus_dmamap_t tbqpage_dmamap; 121 122 volatile struct eth_dsc *RDSC; 123 int rxqi; 124 struct cemac_qmeta rxq[RX_QLEN]; 125 volatile struct eth_dsc *TDSC; 126 int txqi, txqc; 127 struct cemac_qmeta txq[TX_QLEN]; 128 callout_t cemac_tick_ch; 129 130 int cemac_flags; 131 }; 132 133 static void cemac_init(struct cemac_softc *); 134 static int cemac_gctx(struct cemac_softc *); 135 static int cemac_mediachange(struct ifnet *); 136 static void cemac_mediastatus(struct ifnet *, struct ifmediareq *); 137 static int cemac_mii_readreg(device_t, int, int, uint16_t *); 138 static int cemac_mii_writereg(device_t, int, int, uint16_t); 139 static void cemac_statchg(struct ifnet *); 140 static void cemac_tick(void *); 141 static int cemac_ifioctl(struct ifnet *, u_long, void *); 142 static void cemac_ifstart(struct ifnet *); 143 static void cemac_ifwatchdog(struct ifnet *); 144 static int cemac_ifinit(struct ifnet *); 145 static void cemac_ifstop(struct ifnet *, int); 146 static void cemac_setaddr(struct ifnet *); 147 148 #ifdef CEMAC_DEBUG 149 int cemac_debug = CEMAC_DEBUG; 150 #define DPRINTFN(n, fmt) if (cemac_debug >= (n)) printf fmt 151 #else 152 #define DPRINTFN(n, fmt) 153 #endif 154 155 CFATTACH_DECL_NEW(cemac, sizeof(struct cemac_softc), 156 cemac_match, cemac_attach, NULL, NULL); 157 158 int 159 cemac_match_common(device_t parent, cfdata_t match, void *aux) 160 { 161 if (strcmp(match->cf_name, "cemac") == 0) 162 return 1; 163 return 0; 164 } 165 166 void 167 cemac_attach_common(device_t self, bus_space_tag_t iot, 168 bus_space_handle_t ioh, bus_dma_tag_t dmat, int flags) 169 { 170 struct cemac_softc *sc = device_private(self); 171 prop_data_t enaddr; 172 uint32_t u; 173 174 175 sc->sc_dev = self; 176 sc->sc_ioh = ioh; 177 sc->sc_iot = iot; 178 sc->sc_dmat = dmat; 179 sc->cemac_flags = flags; 180 181 aprint_naive("\n"); 182 if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) 183 aprint_normal(": Cadence Gigabit Ethernet Controller\n"); 184 else 185 aprint_normal(": Cadence Ethernet Controller\n"); 186 187 /* configure emac: */ 188 CEMAC_WRITE(ETH_CTL, 0); // disable everything 189 CEMAC_WRITE(ETH_IDR, -1); // disable interrupts 190 CEMAC_WRITE(ETH_RBQP, 0); // clear receive 191 CEMAC_WRITE(ETH_TBQP, 0); // clear transmit 192 if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) 193 CEMAC_WRITE(ETH_CFG, 194 GEM_CFG_CLK_64 | GEM_CFG_GEN | ETH_CFG_SPD | ETH_CFG_FD); 195 else 196 CEMAC_WRITE(ETH_CFG, 197 ETH_CFG_CLK_32 | ETH_CFG_SPD | ETH_CFG_FD | ETH_CFG_BIG); 198 //CEMAC_WRITE(ETH_TCR, 0); // send nothing 199 //(void)CEMAC_READ(ETH_ISR); 200 u = CEMAC_READ(ETH_TSR); 201 CEMAC_WRITE(ETH_TSR, (u & (ETH_TSR_UND | ETH_TSR_COMP | ETH_TSR_BNQ 202 | ETH_TSR_IDLE | ETH_TSR_RLE 203 | ETH_TSR_COL | ETH_TSR_OVR))); 204 u = CEMAC_READ(ETH_RSR); 205 CEMAC_WRITE(ETH_RSR, (u & (ETH_RSR_OVR | ETH_RSR_REC | ETH_RSR_BNA))); 206 207 /* Fetch the Ethernet address from property if set. */ 208 enaddr = prop_dictionary_get(device_properties(self), "mac-address"); 209 210 if (enaddr != NULL) { 211 KASSERT(prop_object_type(enaddr) == PROP_TYPE_DATA); 212 KASSERT(prop_data_size(enaddr) == ETHER_ADDR_LEN); 213 memcpy(sc->sc_enaddr, prop_data_value(enaddr), 214 ETHER_ADDR_LEN); 215 } else { 216 static const uint8_t hardcoded[ETHER_ADDR_LEN] = { 217 0x00, 0x0d, 0x10, 0x81, 0x0c, 0x94 218 }; 219 memcpy(sc->sc_enaddr, hardcoded, ETHER_ADDR_LEN); 220 } 221 222 cemac_init(sc); 223 } 224 225 static int 226 cemac_gctx(struct cemac_softc *sc) 227 { 228 struct ifnet * ifp = &sc->sc_ethercom.ec_if; 229 uint32_t tsr; 230 231 tsr = CEMAC_READ(ETH_TSR); 232 if (!ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) { 233 // no space left 234 if (!(tsr & ETH_TSR_BNQ)) 235 return 0; 236 } else { 237 if (tsr & GEM_TSR_TXGO) 238 return 0; 239 } 240 CEMAC_WRITE(ETH_TSR, tsr); 241 242 // free sent frames 243 while (sc->txqc > (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM) ? 0 : 244 (tsr & ETH_TSR_IDLE ? 0 : 1))) { 245 int bi = sc->txqi % TX_QLEN; 246 247 DPRINTFN(3,("%s: TDSC[%i].Addr 0x%08x\n", 248 __FUNCTION__, bi, sc->TDSC[bi].Addr)); 249 DPRINTFN(3,("%s: TDSC[%i].Info 0x%08x\n", 250 __FUNCTION__, bi, sc->TDSC[bi].Info)); 251 252 bus_dmamap_sync(sc->sc_dmat, sc->txq[bi].m_dmamap, 0, 253 sc->txq[bi].m->m_pkthdr.len, BUS_DMASYNC_POSTWRITE); 254 bus_dmamap_unload(sc->sc_dmat, sc->txq[bi].m_dmamap); 255 m_freem(sc->txq[bi].m); 256 DPRINTFN(2,("%s: freed idx #%i mbuf %p (txqc=%i)\n", 257 __FUNCTION__, bi, sc->txq[bi].m, sc->txqc)); 258 sc->txq[bi].m = NULL; 259 sc->txqi = (bi + 1) % TX_QLEN; 260 sc->txqc--; 261 } 262 263 // mark we're free 264 if (ifp->if_flags & IFF_OACTIVE) { 265 ifp->if_flags &= ~IFF_OACTIVE; 266 /* Disable transmit-buffer-free interrupt */ 267 /*CEMAC_WRITE(ETH_IDR, ETH_ISR_TBRE);*/ 268 } 269 270 return 1; 271 } 272 273 int 274 cemac_intr(void *arg) 275 { 276 struct cemac_softc *sc = (struct cemac_softc *)arg; 277 struct ifnet * ifp = &sc->sc_ethercom.ec_if; 278 uint32_t imr, isr, ctl; 279 #ifdef CEMAC_DEBUG 280 uint32_t rsr; 281 #endif 282 int bi; 283 284 imr = ~CEMAC_READ(ETH_IMR); 285 if (!(imr & (ETH_ISR_RCOM | ETH_ISR_TBRE | ETH_ISR_TIDLE | 286 ETH_ISR_RBNA | ETH_ISR_ROVR | ETH_ISR_TCOM))) { 287 // interrupt not enabled, can't be us 288 return 0; 289 } 290 291 isr = CEMAC_READ(ETH_ISR); 292 CEMAC_WRITE(ETH_ISR, isr); 293 isr &= imr; 294 #ifdef CEMAC_DEBUG 295 rsr = CEMAC_READ(ETH_RSR); // get receive status register 296 #endif 297 DPRINTFN(2, ("%s: isr=0x%08X rsr=0x%08X imr=0x%08X\n", __FUNCTION__, isr, rsr, imr)); 298 299 net_stat_ref_t nsr = IF_STAT_GETREF(ifp); 300 if (isr & ETH_ISR_RBNA) { // out of receive buffers 301 CEMAC_WRITE(ETH_RSR, ETH_RSR_BNA); // clear interrupt 302 ctl = CEMAC_READ(ETH_CTL); // get current control register value 303 CEMAC_WRITE(ETH_CTL, ctl & ~ETH_CTL_RE); // disable receiver 304 CEMAC_WRITE(ETH_RSR, ETH_RSR_BNA); // clear BNA bit 305 CEMAC_WRITE(ETH_CTL, ctl | ETH_CTL_RE); // re-enable receiver 306 if_statinc_ref(nsr, if_ierrors); 307 if_statinc_ref(nsr, if_ipackets); 308 DPRINTFN(1,("%s: out of receive buffers\n", __FUNCTION__)); 309 } 310 if (isr & ETH_ISR_ROVR) { 311 CEMAC_WRITE(ETH_RSR, ETH_RSR_OVR); // clear interrupt 312 if_statinc_ref(nsr, if_ierrors); 313 if_statinc_ref(nsr, if_ipackets); 314 DPRINTFN(1,("%s: receive overrun\n", __FUNCTION__)); 315 } 316 317 if (isr & ETH_ISR_RCOM) { // packet has been received! 318 uint32_t nfo; 319 DPRINTFN(2,("#2 RDSC[%i].INFO=0x%08X\n", sc->rxqi % RX_QLEN, sc->RDSC[sc->rxqi % RX_QLEN].Info)); 320 while (sc->RDSC[(bi = sc->rxqi % RX_QLEN)].Addr & ETH_RDSC_F_USED) { 321 int fl, csum; 322 struct mbuf *m; 323 324 nfo = sc->RDSC[bi].Info; 325 fl = (nfo & ETH_RDSC_I_LEN) - 4; 326 DPRINTFN(2,("## nfo=0x%08X\n", nfo)); 327 328 MGETHDR(m, M_DONTWAIT, MT_DATA); 329 if (m != NULL) MCLGET(m, M_DONTWAIT); 330 if (m != NULL && (m->m_flags & M_EXT)) { 331 bus_dmamap_sync(sc->sc_dmat, sc->rxq[bi].m_dmamap, 0, 332 MCLBYTES, BUS_DMASYNC_POSTREAD); 333 bus_dmamap_unload(sc->sc_dmat, 334 sc->rxq[bi].m_dmamap); 335 m_set_rcvif(sc->rxq[bi].m, ifp); 336 sc->rxq[bi].m->m_pkthdr.len = 337 sc->rxq[bi].m->m_len = fl; 338 switch (nfo & ETH_RDSC_I_CHKSUM) { 339 case ETH_RDSC_I_CHKSUM_IP: 340 csum = M_CSUM_IPv4; 341 break; 342 case ETH_RDSC_I_CHKSUM_UDP: 343 csum = M_CSUM_IPv4 | M_CSUM_UDPv4 | 344 M_CSUM_UDPv6; 345 break; 346 case ETH_RDSC_I_CHKSUM_TCP: 347 csum = M_CSUM_IPv4 | M_CSUM_TCPv4 | 348 M_CSUM_TCPv6; 349 break; 350 default: 351 csum = 0; 352 break; 353 } 354 sc->rxq[bi].m->m_pkthdr.csum_flags = csum; 355 DPRINTFN(2,("received %u bytes packet\n", fl)); 356 if_percpuq_enqueue(ifp->if_percpuq, 357 sc->rxq[bi].m); 358 if (mtod(m, intptr_t) & 3) 359 m_adj(m, mtod(m, intptr_t) & 3); 360 sc->rxq[bi].m = m; 361 bus_dmamap_load(sc->sc_dmat, 362 sc->rxq[bi].m_dmamap, 363 m->m_ext.ext_buf, MCLBYTES, 364 NULL, BUS_DMA_NOWAIT); 365 bus_dmamap_sync(sc->sc_dmat, sc->rxq[bi].m_dmamap, 0, 366 MCLBYTES, BUS_DMASYNC_PREREAD); 367 sc->RDSC[bi].Info = 0; 368 sc->RDSC[bi].Addr = 369 sc->rxq[bi].m_dmamap->dm_segs[0].ds_addr 370 | (bi == (RX_QLEN-1) ? ETH_RDSC_F_WRAP : 0); 371 } else { 372 /* Drop packets until we can get replacement 373 * empty mbufs for the RXDQ. 374 */ 375 if (m != NULL) 376 m_freem(m); 377 if_statinc_ref(nsr, if_ierrors); 378 } 379 sc->rxqi++; 380 } 381 } 382 383 IF_STAT_PUTREF(ifp); 384 385 if (cemac_gctx(sc) > 0) 386 if_schedule_deferred_start(ifp); 387 #if 0 // reloop 388 irq = CEMAC_READ(IntStsC); 389 if ((irq & (IntSts_RxSQ | IntSts_ECI)) != 0) 390 goto begin; 391 #endif 392 393 return (1); 394 } 395 396 397 static void 398 cemac_init(struct cemac_softc *sc) 399 { 400 bus_dma_segment_t segs; 401 int rsegs, err, i; 402 struct ifnet * ifp = &sc->sc_ethercom.ec_if; 403 struct mii_data * const mii = &sc->sc_mii; 404 uint32_t u; 405 #if 0 406 int mdcdiv = DEFAULT_MDCDIV; 407 #endif 408 409 callout_init(&sc->cemac_tick_ch, 0); 410 411 // ok... 412 CEMAC_WRITE(ETH_CTL, ETH_CTL_MPE); // disable everything 413 CEMAC_WRITE(ETH_IDR, -1); // disable interrupts 414 CEMAC_WRITE(ETH_RBQP, 0); // clear receive 415 CEMAC_WRITE(ETH_TBQP, 0); // clear transmit 416 if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) 417 CEMAC_WRITE(ETH_CFG, 418 GEM_CFG_CLK_64 | ETH_CFG_SPD | ETH_CFG_FD | ETH_CFG_BIG); 419 else 420 CEMAC_WRITE(ETH_CFG, 421 ETH_CFG_CLK_32 | ETH_CFG_SPD | ETH_CFG_FD | ETH_CFG_BIG); 422 if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) { 423 CEMAC_WRITE(GEM_DMA_CFG, 424 __SHIFTIN((MCLBYTES + 63) / 64, GEM_DMA_CFG_RX_BUF_SIZE) | 425 __SHIFTIN(3, GEM_DMA_CFG_RX_PKTBUF_MEMSZ_SEL) | 426 GEM_DMA_CFG_TX_PKTBUF_MEMSZ_SEL | 427 __SHIFTIN(16, GEM_DMA_CFG_AHB_FIXED_BURST_LEN) | 428 GEM_DMA_CFG_DISC_WHEN_NO_AHB); 429 } 430 // CEMAC_WRITE(ETH_TCR, 0); // send nothing 431 // (void)CEMAC_READ(ETH_ISR); 432 u = CEMAC_READ(ETH_TSR); 433 CEMAC_WRITE(ETH_TSR, (u & (ETH_TSR_UND | ETH_TSR_COMP | ETH_TSR_BNQ 434 | ETH_TSR_IDLE | ETH_TSR_RLE 435 | ETH_TSR_COL | ETH_TSR_OVR))); 436 u = CEMAC_READ(ETH_RSR); 437 CEMAC_WRITE(ETH_RSR, (u & (ETH_RSR_OVR | ETH_RSR_REC | ETH_RSR_BNA))); 438 439 #if 0 440 if (device_cfdata(sc->sc_dev)->cf_flags) 441 mdcdiv = device_cfdata(sc->sc_dev)->cf_flags; 442 #endif 443 /* set ethernet address */ 444 CEMAC_GEM_WRITE(SA1L, (sc->sc_enaddr[3] << 24) 445 | (sc->sc_enaddr[2] << 16) | (sc->sc_enaddr[1] << 8) 446 | (sc->sc_enaddr[0])); 447 CEMAC_GEM_WRITE(SA1H, (sc->sc_enaddr[5] << 8) 448 | (sc->sc_enaddr[4])); 449 CEMAC_GEM_WRITE(SA2L, 0); 450 CEMAC_GEM_WRITE(SA2H, 0); 451 CEMAC_GEM_WRITE(SA3L, 0); 452 CEMAC_GEM_WRITE(SA3H, 0); 453 CEMAC_GEM_WRITE(SA4L, 0); 454 CEMAC_GEM_WRITE(SA4H, 0); 455 456 /* Allocate a page of memory for receive queue descriptors */ 457 sc->rbqlen = (ETH_DSC_SIZE * (RX_QLEN + 1) * 2 + PAGE_SIZE - 1) / PAGE_SIZE; 458 sc->rbqlen *= PAGE_SIZE; 459 DPRINTFN(1,("%s: rbqlen=%i\n", __FUNCTION__, sc->rbqlen)); 460 461 err = bus_dmamem_alloc(sc->sc_dmat, sc->rbqlen, 0, 462 MAX(16384, PAGE_SIZE), // see EMAC errata why forced to 16384 byte boundary 463 &segs, 1, &rsegs, BUS_DMA_WAITOK); 464 if (err == 0) { 465 DPRINTFN(1,("%s: -> bus_dmamem_map\n", __FUNCTION__)); 466 err = bus_dmamem_map(sc->sc_dmat, &segs, 1, sc->rbqlen, 467 &sc->rbqpage, (BUS_DMA_WAITOK | BUS_DMA_COHERENT)); 468 } 469 if (err == 0) { 470 DPRINTFN(1,("%s: -> bus_dmamap_create\n", __FUNCTION__)); 471 err = bus_dmamap_create(sc->sc_dmat, sc->rbqlen, 1, 472 sc->rbqlen, MAX(16384, PAGE_SIZE), BUS_DMA_WAITOK, 473 &sc->rbqpage_dmamap); 474 } 475 if (err == 0) { 476 DPRINTFN(1,("%s: -> bus_dmamap_load\n", __FUNCTION__)); 477 err = bus_dmamap_load(sc->sc_dmat, sc->rbqpage_dmamap, 478 sc->rbqpage, sc->rbqlen, NULL, BUS_DMA_WAITOK); 479 } 480 if (err != 0) 481 panic("%s: Cannot get DMA memory", device_xname(sc->sc_dev)); 482 483 sc->rbqpage_dsaddr = sc->rbqpage_dmamap->dm_segs[0].ds_addr; 484 memset(sc->rbqpage, 0, sc->rbqlen); 485 486 /* Allocate a page of memory for transmit queue descriptors */ 487 sc->tbqlen = (ETH_DSC_SIZE * (TX_QLEN + 1) * 2 + PAGE_SIZE - 1) / PAGE_SIZE; 488 sc->tbqlen *= PAGE_SIZE; 489 DPRINTFN(1,("%s: tbqlen=%i\n", __FUNCTION__, sc->tbqlen)); 490 491 err = bus_dmamem_alloc(sc->sc_dmat, sc->tbqlen, 0, 492 MAX(16384, PAGE_SIZE), // see EMAC errata why forced to 16384 byte boundary 493 &segs, 1, &rsegs, BUS_DMA_WAITOK); 494 if (err == 0) { 495 DPRINTFN(1,("%s: -> bus_dmamem_map\n", __FUNCTION__)); 496 err = bus_dmamem_map(sc->sc_dmat, &segs, 1, sc->tbqlen, 497 &sc->tbqpage, (BUS_DMA_WAITOK | BUS_DMA_COHERENT)); 498 } 499 if (err == 0) { 500 DPRINTFN(1,("%s: -> bus_dmamap_create\n", __FUNCTION__)); 501 err = bus_dmamap_create(sc->sc_dmat, sc->tbqlen, 1, 502 sc->tbqlen, MAX(16384, PAGE_SIZE), BUS_DMA_WAITOK, 503 &sc->tbqpage_dmamap); 504 } 505 if (err == 0) { 506 DPRINTFN(1,("%s: -> bus_dmamap_load\n", __FUNCTION__)); 507 err = bus_dmamap_load(sc->sc_dmat, sc->tbqpage_dmamap, 508 sc->tbqpage, sc->tbqlen, NULL, BUS_DMA_WAITOK); 509 } 510 if (err != 0) 511 panic("%s: Cannot get DMA memory", device_xname(sc->sc_dev)); 512 513 sc->tbqpage_dsaddr = sc->tbqpage_dmamap->dm_segs[0].ds_addr; 514 memset(sc->tbqpage, 0, sc->tbqlen); 515 516 /* Set up pointers to start of each queue in kernel addr space. 517 * Each descriptor queue or status queue entry uses 2 words 518 */ 519 sc->RDSC = (void *)sc->rbqpage; 520 sc->TDSC = (void *)sc->tbqpage; 521 522 /* init TX queue */ 523 for (i = 0; i < TX_QLEN; i++) { 524 sc->TDSC[i].Addr = 0; 525 sc->TDSC[i].Info = ETH_TDSC_I_USED | 526 (i == (TX_QLEN - 1) ? ETH_TDSC_I_WRAP : 0); 527 } 528 529 /* Populate the RXQ with mbufs */ 530 sc->rxqi = 0; 531 for (i = 0; i < RX_QLEN; i++) { 532 struct mbuf *m; 533 534 err = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, PAGE_SIZE, 535 BUS_DMA_WAITOK, &sc->rxq[i].m_dmamap); 536 if (err) { 537 panic("%s: dmamap_create failed: %i\n", __FUNCTION__, err); 538 } 539 MGETHDR(m, M_WAIT, MT_DATA); 540 MCLGET(m, M_WAIT); 541 sc->rxq[i].m = m; 542 if (mtod(m, intptr_t) & 3) { 543 m_adj(m, mtod(m, intptr_t) & 3); 544 } 545 err = bus_dmamap_load(sc->sc_dmat, sc->rxq[i].m_dmamap, 546 m->m_ext.ext_buf, MCLBYTES, NULL, 547 BUS_DMA_WAITOK); 548 if (err) { 549 panic("%s: dmamap_load failed: %i\n", __FUNCTION__, err); 550 } 551 sc->RDSC[i].Addr = sc->rxq[i].m_dmamap->dm_segs[0].ds_addr 552 | (i == (RX_QLEN-1) ? ETH_RDSC_F_WRAP : 0); 553 sc->RDSC[i].Info = 0; 554 bus_dmamap_sync(sc->sc_dmat, sc->rxq[i].m_dmamap, 0, 555 MCLBYTES, BUS_DMASYNC_PREREAD); 556 } 557 558 /* prepare transmit queue */ 559 for (i = 0; i < TX_QLEN; i++) { 560 err = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 0, 561 (BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW), 562 &sc->txq[i].m_dmamap); 563 if (err) 564 panic("ARGH #1"); 565 sc->txq[i].m = NULL; 566 } 567 568 /* Program each queue's start addr, cur addr, and len registers 569 * with the physical addresses. 570 */ 571 CEMAC_WRITE(ETH_RBQP, (uint32_t)sc->rbqpage_dsaddr); 572 CEMAC_WRITE(ETH_TBQP, (uint32_t)sc->tbqpage_dsaddr); 573 574 /* Divide HCLK by 32 for MDC clock */ 575 sc->sc_ethercom.ec_mii = mii; 576 mii->mii_ifp = ifp; 577 mii->mii_readreg = cemac_mii_readreg; 578 mii->mii_writereg = cemac_mii_writereg; 579 mii->mii_statchg = cemac_statchg; 580 ifmedia_init(&mii->mii_media, IFM_IMASK, cemac_mediachange, 581 cemac_mediastatus); 582 mii_attach(sc->sc_dev, mii, 0xffffffff, MII_PHY_ANY, 583 MII_OFFSET_ANY, 0); 584 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 585 586 #if 0 587 // enable / disable interrupts 588 CEMAC_WRITE(ETH_IDR, -1); 589 CEMAC_WRITE(ETH_IER, ETH_ISR_RCOM | ETH_ISR_TBRE | ETH_ISR_TIDLE 590 | ETH_ISR_RBNA | ETH_ISR_ROVR | ETH_ISR_TCOM); 591 // (void)CEMAC_READ(ETH_ISR); // why 592 593 // enable transmitter / receiver 594 CEMAC_WRITE(ETH_CTL, ETH_CTL_TE | ETH_CTL_RE | ETH_CTL_ISR 595 | ETH_CTL_CSR | ETH_CTL_MPE); 596 #endif 597 /* 598 * We can support hardware checksumming. 599 */ 600 ifp->if_capabilities |= 601 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 602 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 603 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx | 604 IFCAP_CSUM_TCPv6_Tx | IFCAP_CSUM_TCPv6_Rx | 605 IFCAP_CSUM_UDPv6_Tx | IFCAP_CSUM_UDPv6_Rx; 606 607 /* 608 * We can support 802.1Q VLAN-sized frames. 609 */ 610 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 611 612 strcpy(ifp->if_xname, device_xname(sc->sc_dev)); 613 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 614 ifp->if_ioctl = cemac_ifioctl; 615 ifp->if_start = cemac_ifstart; 616 ifp->if_watchdog = cemac_ifwatchdog; 617 ifp->if_init = cemac_ifinit; 618 ifp->if_stop = cemac_ifstop; 619 ifp->if_timer = 0; 620 ifp->if_softc = sc; 621 IFQ_SET_READY(&ifp->if_snd); 622 if_attach(ifp); 623 if_deferred_start_init(ifp, NULL); 624 ether_ifattach(ifp, (sc)->sc_enaddr); 625 } 626 627 static int 628 cemac_mediachange(struct ifnet *ifp) 629 { 630 if (ifp->if_flags & IFF_UP) 631 cemac_ifinit(ifp); 632 return (0); 633 } 634 635 static void 636 cemac_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 637 { 638 struct cemac_softc *sc = ifp->if_softc; 639 640 mii_pollstat(&sc->sc_mii); 641 ifmr->ifm_active = sc->sc_mii.mii_media_active; 642 ifmr->ifm_status = sc->sc_mii.mii_media_status; 643 } 644 645 646 static int 647 cemac_mii_readreg(device_t self, int phy, int reg, uint16_t *val) 648 { 649 struct cemac_softc *sc; 650 651 sc = device_private(self); 652 653 CEMAC_WRITE(ETH_MAN, (ETH_MAN_HIGH | ETH_MAN_RW_RD 654 | ((phy << ETH_MAN_PHYA_SHIFT) & ETH_MAN_PHYA) 655 | ((reg << ETH_MAN_REGA_SHIFT) & ETH_MAN_REGA) 656 | ETH_MAN_CODE_IEEE802_3)); 657 while (!(CEMAC_READ(ETH_SR) & ETH_SR_IDLE)) 658 ; 659 660 *val = CEMAC_READ(ETH_MAN) & ETH_MAN_DATA; 661 return 0; 662 } 663 664 static int 665 cemac_mii_writereg(device_t self, int phy, int reg, uint16_t val) 666 { 667 struct cemac_softc *sc; 668 669 sc = device_private(self); 670 671 CEMAC_WRITE(ETH_MAN, (ETH_MAN_HIGH | ETH_MAN_RW_WR 672 | ((phy << ETH_MAN_PHYA_SHIFT) & ETH_MAN_PHYA) 673 | ((reg << ETH_MAN_REGA_SHIFT) & ETH_MAN_REGA) 674 | ETH_MAN_CODE_IEEE802_3 675 | (val & ETH_MAN_DATA))); 676 while (!(CEMAC_READ(ETH_SR) & ETH_SR_IDLE)) 677 ; 678 679 return 0; 680 } 681 682 683 static void 684 cemac_statchg(struct ifnet *ifp) 685 { 686 struct cemac_softc *sc = ifp->if_softc; 687 struct mii_data *mii = &sc->sc_mii; 688 uint32_t reg; 689 690 /* 691 * We must keep the MAC and the PHY in sync as 692 * to the status of full-duplex! 693 */ 694 reg = CEMAC_READ(ETH_CFG); 695 reg &= ~ETH_CFG_FD; 696 if (sc->sc_mii.mii_media_active & IFM_FDX) 697 reg |= ETH_CFG_FD; 698 699 reg &= ~ETH_CFG_SPD; 700 if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) 701 reg &= ~GEM_CFG_GEN; 702 switch (IFM_SUBTYPE(mii->mii_media_active)) { 703 case IFM_10_T: 704 break; 705 case IFM_100_TX: 706 reg |= ETH_CFG_SPD; 707 break; 708 case IFM_1000_T: 709 reg |= ETH_CFG_SPD | GEM_CFG_GEN; 710 break; 711 default: 712 break; 713 } 714 CEMAC_WRITE(ETH_CFG, reg); 715 } 716 717 static void 718 cemac_tick(void *arg) 719 { 720 struct cemac_softc* sc = (struct cemac_softc *)arg; 721 struct ifnet * ifp = &sc->sc_ethercom.ec_if; 722 int s; 723 724 if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) 725 if_statadd(ifp, if_collisions, 726 CEMAC_READ(GEM_SCOL) + CEMAC_READ(GEM_MCOL)); 727 else 728 if_statadd(ifp, if_collisions, 729 CEMAC_READ(ETH_SCOL) + CEMAC_READ(ETH_MCOL)); 730 731 /* These misses are ok, they will happen if the RAM/CPU can't keep up */ 732 if (!ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) { 733 uint32_t misses = CEMAC_READ(ETH_DRFC); 734 if (misses > 0) 735 aprint_normal_ifnet(ifp, "%d rx misses\n", misses); 736 } 737 738 s = splnet(); 739 if (cemac_gctx(sc) > 0 && IFQ_IS_EMPTY(&ifp->if_snd) == 0) 740 cemac_ifstart(ifp); 741 splx(s); 742 743 mii_tick(&sc->sc_mii); 744 callout_reset(&sc->cemac_tick_ch, hz, cemac_tick, sc); 745 } 746 747 748 static int 749 cemac_ifioctl(struct ifnet *ifp, u_long cmd, void *data) 750 { 751 int s, error; 752 753 s = splnet(); 754 switch (cmd) { 755 default: 756 error = ether_ioctl(ifp, cmd, data); 757 if (error != ENETRESET) 758 break; 759 error = 0; 760 761 if (cmd == SIOCSIFCAP) { 762 error = (*ifp->if_init)(ifp); 763 } else if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 764 ; 765 else if (ifp->if_flags & IFF_RUNNING) { 766 cemac_setaddr(ifp); 767 } 768 } 769 splx(s); 770 return error; 771 } 772 773 static void 774 cemac_ifstart(struct ifnet *ifp) 775 { 776 struct cemac_softc *sc = (struct cemac_softc *)ifp->if_softc; 777 struct mbuf *m; 778 bus_dma_segment_t *segs; 779 int s, bi, err, nsegs; 780 781 s = splnet(); 782 start: 783 if (cemac_gctx(sc) == 0) { 784 /* Enable transmit-buffer-free interrupt */ 785 CEMAC_WRITE(ETH_IER, ETH_ISR_TBRE); 786 ifp->if_flags |= IFF_OACTIVE; 787 ifp->if_timer = 10; 788 splx(s); 789 return; 790 } 791 792 ifp->if_timer = 0; 793 794 IFQ_POLL(&ifp->if_snd, m); 795 if (m == NULL) { 796 splx(s); 797 return; 798 } 799 800 bi = (sc->txqi + sc->txqc) % TX_QLEN; 801 if ((err = bus_dmamap_load_mbuf(sc->sc_dmat, sc->txq[bi].m_dmamap, m, 802 BUS_DMA_NOWAIT)) || 803 sc->txq[bi].m_dmamap->dm_segs[0].ds_addr & 0x3 || 804 sc->txq[bi].m_dmamap->dm_nsegs > 1) { 805 /* Copy entire mbuf chain to new single */ 806 struct mbuf *mn; 807 808 if (err == 0) 809 bus_dmamap_unload(sc->sc_dmat, sc->txq[bi].m_dmamap); 810 811 MGETHDR(mn, M_DONTWAIT, MT_DATA); 812 if (mn == NULL) goto stop; 813 if (m->m_pkthdr.len > MHLEN) { 814 MCLGET(mn, M_DONTWAIT); 815 if ((mn->m_flags & M_EXT) == 0) { 816 m_freem(mn); 817 goto stop; 818 } 819 } 820 m_copydata(m, 0, m->m_pkthdr.len, mtod(mn, void *)); 821 mn->m_pkthdr.len = mn->m_len = m->m_pkthdr.len; 822 IFQ_DEQUEUE(&ifp->if_snd, m); 823 m_freem(m); 824 m = mn; 825 bus_dmamap_load_mbuf(sc->sc_dmat, sc->txq[bi].m_dmamap, m, 826 BUS_DMA_NOWAIT); 827 } else { 828 IFQ_DEQUEUE(&ifp->if_snd, m); 829 } 830 831 bpf_mtap(ifp, m, BPF_D_OUT); 832 833 nsegs = sc->txq[bi].m_dmamap->dm_nsegs; 834 segs = sc->txq[bi].m_dmamap->dm_segs; 835 if (nsegs > 1) 836 panic("#### ARGH #2"); 837 838 sc->txq[bi].m = m; 839 sc->txqc++; 840 841 DPRINTFN(2,("%s: start sending idx #%i mbuf %p (txqc=%i, phys %p), len=%u\n", 842 __FUNCTION__, bi, sc->txq[bi].m, sc->txqc, (void*)segs->ds_addr, 843 (unsigned)m->m_pkthdr.len)); 844 #ifdef DIAGNOSTIC 845 if (sc->txqc > TX_QLEN) 846 panic("%s: txqc %i > %i", __FUNCTION__, sc->txqc, TX_QLEN); 847 #endif 848 849 bus_dmamap_sync(sc->sc_dmat, sc->txq[bi].m_dmamap, 0, 850 sc->txq[bi].m_dmamap->dm_mapsize, 851 BUS_DMASYNC_PREWRITE); 852 853 if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) { 854 sc->TDSC[bi].Addr = segs->ds_addr; 855 sc->TDSC[bi].Info = __SHIFTIN(m->m_pkthdr.len, ETH_TDSC_I_LEN) | 856 ETH_TDSC_I_LAST_BUF | (bi == (TX_QLEN - 1) ? ETH_TDSC_I_WRAP : 0); 857 858 DPRINTFN(3,("%s: TDSC[%i].Addr 0x%08x\n", 859 __FUNCTION__, bi, sc->TDSC[bi].Addr)); 860 DPRINTFN(3,("%s: TDSC[%i].Info 0x%08x\n", 861 __FUNCTION__, bi, sc->TDSC[bi].Info)); 862 863 uint32_t ctl = CEMAC_READ(ETH_CTL) | GEM_CTL_STARTTX; 864 CEMAC_WRITE(ETH_CTL, ctl); 865 DPRINTFN(3,("%s: ETH_CTL 0x%08x\n", __FUNCTION__, CEMAC_READ(ETH_CTL))); 866 } else { 867 CEMAC_WRITE(ETH_TAR, segs->ds_addr); 868 CEMAC_WRITE(ETH_TCR, m->m_pkthdr.len); 869 } 870 if (IFQ_IS_EMPTY(&ifp->if_snd) == 0) 871 goto start; 872 stop: 873 874 splx(s); 875 return; 876 } 877 878 static void 879 cemac_ifwatchdog(struct ifnet *ifp) 880 { 881 struct cemac_softc *sc = (struct cemac_softc *)ifp->if_softc; 882 883 if ((ifp->if_flags & IFF_RUNNING) == 0) 884 return; 885 aprint_error_ifnet(ifp, "device timeout, CTL = 0x%08x, CFG = 0x%08x\n", 886 CEMAC_READ(ETH_CTL), CEMAC_READ(ETH_CFG)); 887 } 888 889 static int 890 cemac_ifinit(struct ifnet *ifp) 891 { 892 struct cemac_softc *sc = ifp->if_softc; 893 uint32_t dma, cfg; 894 int s = splnet(); 895 896 callout_stop(&sc->cemac_tick_ch); 897 898 if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) { 899 900 if (ifp->if_capenable & 901 (IFCAP_CSUM_IPv4_Tx | 902 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_UDPv4_Tx | 903 IFCAP_CSUM_TCPv6_Tx | IFCAP_CSUM_UDPv6_Tx)) { 904 dma = CEMAC_READ(GEM_DMA_CFG); 905 dma |= GEM_DMA_CFG_CHKSUM_GEN_OFFLOAD_EN; 906 CEMAC_WRITE(GEM_DMA_CFG, dma); 907 } 908 if (ifp->if_capenable & 909 (IFCAP_CSUM_IPv4_Rx | 910 IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx | 911 IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx)) { 912 cfg = CEMAC_READ(ETH_CFG); 913 cfg |= GEM_CFG_RX_CHKSUM_OFFLD_EN; 914 CEMAC_WRITE(ETH_CFG, cfg); 915 } 916 } 917 918 // enable interrupts 919 CEMAC_WRITE(ETH_IDR, -1); 920 CEMAC_WRITE(ETH_IER, ETH_ISR_RCOM | ETH_ISR_TBRE | ETH_ISR_TIDLE 921 | ETH_ISR_RBNA | ETH_ISR_ROVR | ETH_ISR_TCOM); 922 923 // enable transmitter / receiver 924 CEMAC_WRITE(ETH_CTL, ETH_CTL_TE | ETH_CTL_RE | ETH_CTL_ISR 925 | ETH_CTL_CSR | ETH_CTL_MPE); 926 927 mii_mediachg(&sc->sc_mii); 928 callout_reset(&sc->cemac_tick_ch, hz, cemac_tick, sc); 929 ifp->if_flags |= IFF_RUNNING; 930 splx(s); 931 return 0; 932 } 933 934 static void 935 cemac_ifstop(struct ifnet *ifp, int disable) 936 { 937 // uint32_t u; 938 struct cemac_softc *sc = ifp->if_softc; 939 940 #if 0 941 CEMAC_WRITE(ETH_CTL, ETH_CTL_MPE); // disable everything 942 CEMAC_WRITE(ETH_IDR, -1); // disable interrupts 943 // CEMAC_WRITE(ETH_RBQP, 0); // clear receive 944 if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) 945 CEMAC_WRITE(ETH_CFG, 946 GEM_CFG_CLK_64 | ETH_CFG_SPD | ETH_CFG_FD | ETH_CFG_BIG); 947 else 948 CEMAC_WRITE(ETH_CFG, 949 ETH_CFG_CLK_32 | ETH_CFG_SPD | ETH_CFG_FD | ETH_CFG_BIG); 950 // CEMAC_WRITE(ETH_TCR, 0); // send nothing 951 // (void)CEMAC_READ(ETH_ISR); 952 u = CEMAC_READ(ETH_TSR); 953 CEMAC_WRITE(ETH_TSR, (u & (ETH_TSR_UND | ETH_TSR_COMP | ETH_TSR_BNQ 954 | ETH_TSR_IDLE | ETH_TSR_RLE 955 | ETH_TSR_COL | ETH_TSR_OVR))); 956 u = CEMAC_READ(ETH_RSR); 957 CEMAC_WRITE(ETH_RSR, (u & (ETH_RSR_OVR | ETH_RSR_REC | ETH_RSR_BNA))); 958 #endif 959 callout_stop(&sc->cemac_tick_ch); 960 961 /* Down the MII. */ 962 mii_down(&sc->sc_mii); 963 964 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 965 ifp->if_timer = 0; 966 sc->sc_mii.mii_media_status &= ~IFM_ACTIVE; 967 } 968 969 static void 970 cemac_setaddr(struct ifnet *ifp) 971 { 972 struct cemac_softc *sc = ifp->if_softc; 973 struct ethercom *ec = &sc->sc_ethercom; 974 struct ether_multi *enm; 975 struct ether_multistep step; 976 uint8_t ias[3][ETHER_ADDR_LEN]; 977 uint32_t h, nma = 0, hashes[2] = { 0, 0 }; 978 uint32_t ctl = CEMAC_READ(ETH_CTL); 979 uint32_t cfg = CEMAC_READ(ETH_CFG); 980 981 /* disable receiver temporarily */ 982 CEMAC_WRITE(ETH_CTL, ctl & ~ETH_CTL_RE); 983 984 cfg &= ~(ETH_CFG_MTI | ETH_CFG_UNI | ETH_CFG_CAF | ETH_CFG_UNI); 985 986 if (ifp->if_flags & IFF_PROMISC) { 987 cfg |= ETH_CFG_CAF; 988 } else { 989 cfg &= ~ETH_CFG_CAF; 990 } 991 992 // ETH_CFG_BIG? 993 994 ifp->if_flags &= ~IFF_ALLMULTI; 995 996 ETHER_LOCK(ec); 997 ETHER_FIRST_MULTI(step, ec, enm); 998 while (enm != NULL) { 999 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1000 /* 1001 * We must listen to a range of multicast addresses. 1002 * For now, just accept all multicasts, rather than 1003 * trying to set only those filter bits needed to match 1004 * the range. (At this time, the only use of address 1005 * ranges is for IP multicast routing, for which the 1006 * range is big enough to require all bits set.) 1007 */ 1008 cfg |= ETH_CFG_MTI; 1009 hashes[0] = 0xffffffffUL; 1010 hashes[1] = 0xffffffffUL; 1011 ifp->if_flags |= IFF_ALLMULTI; 1012 nma = 0; 1013 break; 1014 } 1015 1016 if (nma < 3) { 1017 /* We can program 3 perfect address filters for mcast */ 1018 memcpy(ias[nma], enm->enm_addrlo, ETHER_ADDR_LEN); 1019 } else { 1020 /* 1021 * XXX: Datasheet is not very clear here, I'm not sure 1022 * if I'm doing this right. --joff 1023 */ 1024 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 1025 1026 /* Just want the 6 most-significant bits. */ 1027 h = h >> 26; 1028 #if 0 1029 hashes[h / 32] |= (1 << (h % 32)); 1030 #else 1031 hashes[0] = 0xffffffffUL; 1032 hashes[1] = 0xffffffffUL; 1033 #endif 1034 cfg |= ETH_CFG_MTI; 1035 } 1036 ETHER_NEXT_MULTI(step, enm); 1037 nma++; 1038 } 1039 ETHER_UNLOCK(ec); 1040 1041 // program... 1042 DPRINTFN(1,("%s: en0 %02x:%02x:%02x:%02x:%02x:%02x\n", __FUNCTION__, 1043 sc->sc_enaddr[0], sc->sc_enaddr[1], sc->sc_enaddr[2], 1044 sc->sc_enaddr[3], sc->sc_enaddr[4], sc->sc_enaddr[5])); 1045 CEMAC_GEM_WRITE(SA1L, (sc->sc_enaddr[3] << 24) 1046 | (sc->sc_enaddr[2] << 16) | (sc->sc_enaddr[1] << 8) 1047 | (sc->sc_enaddr[0])); 1048 CEMAC_GEM_WRITE(SA1H, (sc->sc_enaddr[5] << 8) 1049 | (sc->sc_enaddr[4])); 1050 if (nma > 0) { 1051 DPRINTFN(1,("%s: en1 %02x:%02x:%02x:%02x:%02x:%02x\n", __FUNCTION__, 1052 ias[0][0], ias[0][1], ias[0][2], 1053 ias[0][3], ias[0][4], ias[0][5])); 1054 CEMAC_WRITE(ETH_SA2L, (ias[0][3] << 24) 1055 | (ias[0][2] << 16) | (ias[0][1] << 8) 1056 | (ias[0][0])); 1057 CEMAC_WRITE(ETH_SA2H, (ias[0][4] << 8) 1058 | (ias[0][5])); 1059 } 1060 if (nma > 1) { 1061 DPRINTFN(1,("%s: en2 %02x:%02x:%02x:%02x:%02x:%02x\n", __FUNCTION__, 1062 ias[1][0], ias[1][1], ias[1][2], 1063 ias[1][3], ias[1][4], ias[1][5])); 1064 CEMAC_WRITE(ETH_SA3L, (ias[1][3] << 24) 1065 | (ias[1][2] << 16) | (ias[1][1] << 8) 1066 | (ias[1][0])); 1067 CEMAC_WRITE(ETH_SA3H, (ias[1][4] << 8) 1068 | (ias[1][5])); 1069 } 1070 if (nma > 2) { 1071 DPRINTFN(1,("%s: en3 %02x:%02x:%02x:%02x:%02x:%02x\n", __FUNCTION__, 1072 ias[2][0], ias[2][1], ias[2][2], 1073 ias[2][3], ias[2][4], ias[2][5])); 1074 CEMAC_WRITE(ETH_SA4L, (ias[2][3] << 24) 1075 | (ias[2][2] << 16) | (ias[2][1] << 8) 1076 | (ias[2][0])); 1077 CEMAC_WRITE(ETH_SA4H, (ias[2][4] << 8) 1078 | (ias[2][5])); 1079 } 1080 CEMAC_GEM_WRITE(HSH, hashes[0]); 1081 CEMAC_GEM_WRITE(HSL, hashes[1]); 1082 CEMAC_WRITE(ETH_CFG, cfg); 1083 CEMAC_WRITE(ETH_CTL, ctl | ETH_CTL_RE); 1084 } 1085