1 /* $NetBSD: atavar.h,v 1.19 2001/04/25 17:53:27 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 1998 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by the University of 17 * California, Berkeley and its contributors. 18 * 4. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 */ 34 35 /* Hight-level functions and structures used by both ATA and ATAPI devices */ 36 37 /* Datas common to drives and controller drivers */ 38 struct ata_drive_datas { 39 u_int8_t drive; /* drive number */ 40 int8_t ata_vers; /* ATA version supported */ 41 u_int16_t drive_flags; /* bitmask for drives present/absent and cap */ 42 #define DRIVE_ATA 0x0001 43 #define DRIVE_ATAPI 0x0002 44 #define DRIVE_OLD 0x0004 45 #define DRIVE (DRIVE_ATA|DRIVE_ATAPI|DRIVE_OLD) 46 #define DRIVE_CAP32 0x0008 47 #define DRIVE_DMA 0x0010 48 #define DRIVE_UDMA 0x0020 49 #define DRIVE_MODE 0x0040 /* the drive reported its mode */ 50 #define DRIVE_RESET 0x0080 /* reset the drive state at next xfer */ 51 #define DRIVE_DMAERR 0x0100 /* Udma transfer had crc error, don't try DMA */ 52 /* 53 * Current setting of drive's PIO, DMA and UDMA modes. 54 * Is initialised by the disks drivers at attach time, and may be 55 * changed later by the controller's code if needed 56 */ 57 u_int8_t PIO_mode; /* Current setting of drive's PIO mode */ 58 u_int8_t DMA_mode; /* Current setting of drive's DMA mode */ 59 u_int8_t UDMA_mode; /* Current setting of drive's UDMA mode */ 60 /* Supported modes for this drive */ 61 u_int8_t PIO_cap; /* supported drive's PIO mode */ 62 u_int8_t DMA_cap; /* supported drive's DMA mode */ 63 u_int8_t UDMA_cap; /* supported drive's UDMA mode */ 64 /* 65 * Drive state. 66 * This is reset to 0 after a channel reset. 67 */ 68 u_int8_t state; 69 #define RESET 0 70 #define RECAL 1 71 #define RECAL_WAIT 2 72 #define PIOMODE 3 73 #define PIOMODE_WAIT 4 74 #define DMAMODE 5 75 #define DMAMODE_WAIT 6 76 #define GEOMETRY 7 77 #define GEOMETRY_WAIT 8 78 #define MULTIMODE 9 79 #define MULTIMODE_WAIT 10 80 #define READY 11 81 82 /* numbers of xfers and DMA errs. Used by ata_dmaerr() */ 83 u_int8_t n_dmaerrs; 84 u_int32_t n_xfers; 85 /* Downgrade after NERRS_MAX errors in at most NXFER xfers */ 86 #define NERRS_MAX 4 87 #define NXFER 4000 88 89 struct device *drv_softc; /* ATA drives softc, if any */ 90 void* chnl_softc; /* channel softc */ 91 }; 92 93 /* ATA/ATAPI common attachement datas */ 94 /* 95 * XXX Small hack alert 96 * NOTE: The first field of struct ata_atapi_attach is shared with 97 * dev/scspi/scsipiconf.h's struct scsipi_channel. This allows 98 * atapibus and scsibus to attach to the same device. 99 */ 100 struct ata_atapi_attach { 101 u_int8_t aa_type; /* Type of device */ 102 /*#define T_SCSI 0*/ 103 #define T_ATAPI 1 104 #define T_ATA 2 105 u_int8_t aa_channel; /* controller's channel */ 106 u_int8_t aa_openings; /* Number of simultaneous commands possible */ 107 struct ata_drive_datas *aa_drv_data; 108 void *aa_bus_private; /* infos specifics to this bus */ 109 }; 110 111 /* User config flags that force (or disable) the use of a mode */ 112 #define ATA_CONFIG_PIO_MODES 0x0007 113 #define ATA_CONFIG_PIO_SET 0x0008 114 #define ATA_CONFIG_PIO_OFF 0 115 #define ATA_CONFIG_DMA_MODES 0x0070 116 #define ATA_CONFIG_DMA_SET 0x0080 117 #define ATA_CONFIG_DMA_DISABLE 0x0070 118 #define ATA_CONFIG_DMA_OFF 4 119 #define ATA_CONFIG_UDMA_MODES 0x0700 120 #define ATA_CONFIG_UDMA_SET 0x0800 121 #define ATA_CONFIG_UDMA_DISABLE 0x0700 122 #define ATA_CONFIG_UDMA_OFF 8 123 124 /* 125 * ATA/ATAPI commands description 126 * 127 * This structure defines the interface between the ATA/ATAPI device driver 128 * and the controller for short commands. It contains the command's parameter, 129 * the len of data's to read/write (if any), and a function to call upon 130 * completion. 131 * If no sleep is allowed, the driver can poll for command completion. 132 * Once the command completed, if the error registed is valid, the flag 133 * AT_ERROR is set and the error register value is copied to r_error . 134 * A separate interface is needed for read/write or ATAPI packet commands 135 * (which need multiple interrupts per commands). 136 */ 137 struct wdc_command { 138 u_int8_t r_command; /* Parameters to upload to registers */ 139 u_int8_t r_head; 140 u_int16_t r_cyl; 141 u_int8_t r_sector; 142 u_int8_t r_count; 143 u_int8_t r_precomp; 144 u_int8_t r_st_bmask; /* status register mask to wait for before command */ 145 u_int8_t r_st_pmask; /* status register mask to wait for after command */ 146 u_int8_t r_error; /* error register after command done */ 147 volatile u_int16_t flags; 148 #define AT_READ 0x0001 /* There is data to read */ 149 #define AT_WRITE 0x0002 /* There is data to write (excl. with AT_READ) */ 150 #define AT_WAIT 0x0008 /* wait in controller code for command completion */ 151 #define AT_POLL 0x0010 /* poll for command completion (no interrupts) */ 152 #define AT_DONE 0x0020 /* command is done */ 153 #define AT_ERROR 0x0040 /* command is done with error */ 154 #define AT_TIMEOU 0x0080 /* command timed out */ 155 #define AT_DF 0x0100 /* Drive fault */ 156 #define AT_READREG 0x0200 /* Read registers on completion */ 157 int timeout; /* timeout (in ms) */ 158 void *data; /* Data buffer address */ 159 int bcount; /* number of bytes to transfer */ 160 void (*callback) __P((void*)); /* command to call once command completed */ 161 void *callback_arg; /* argument passed to *callback() */ 162 }; 163 164 int wdc_exec_command __P((struct ata_drive_datas *, struct wdc_command*)); 165 #define WDC_COMPLETE 0x01 166 #define WDC_QUEUED 0x02 167 #define WDC_TRY_AGAIN 0x03 168 169 void wdc_probe_caps __P((struct ata_drive_datas*)); 170 int wdc_downgrade_mode __P((struct ata_drive_datas*)); 171 172 void wdc_reset_channel __P((struct ata_drive_datas *)); 173 174 int wdc_ata_addref __P((struct ata_drive_datas *)); 175 void wdc_ata_delref __P((struct ata_drive_datas *)); 176 void wdc_ata_kill_pending __P((struct ata_drive_datas *)); 177 178 struct ataparams; 179 int ata_get_params __P((struct ata_drive_datas*, u_int8_t, 180 struct ataparams *)); 181 int ata_set_mode __P((struct ata_drive_datas*, u_int8_t, u_int8_t)); 182 /* return code for these cmds */ 183 #define CMD_OK 0 184 #define CMD_ERR 1 185 #define CMD_AGAIN 2 186 187 void ata_dmaerr __P((struct ata_drive_datas *)); 188 void ata_perror __P((struct ata_drive_datas *, int, char *)); 189