1 /* $NetBSD: sdhc_acpi.c,v 1.20 2022/02/06 15:52:20 jmcneill Exp $ */ 2 3 /* 4 * Copyright (c) 2016 Kimihiro Nonaka <nonaka@NetBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. The name of the author may not be used to endorse or promote products 13 * derived from this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 20 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 21 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 22 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 23 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: sdhc_acpi.c,v 1.20 2022/02/06 15:52:20 jmcneill Exp $"); 30 31 #include <sys/param.h> 32 #include <sys/device.h> 33 #include <sys/systm.h> 34 #include <sys/kmem.h> 35 36 #include <dev/acpi/acpireg.h> 37 #include <dev/acpi/acpivar.h> 38 #include <dev/acpi/acpi_intr.h> 39 40 #include <dev/sdmmc/sdhcreg.h> 41 #include <dev/sdmmc/sdhcvar.h> 42 #include <dev/sdmmc/sdmmcvar.h> 43 44 /* Freescale ESDHC */ 45 #define SDHC_ESDHC_FLAGS \ 46 (SDHC_FLAG_HAVE_DVS|SDHC_FLAG_NO_PWR0|SDHC_FLAG_32BIT_ACCESS|SDHC_FLAG_ENHANCED) 47 48 /* Rockchip eMMC device-specific method (_DSM) - 434addb0-8ff3-49d5-a724-95844b79ad1f */ 49 static UINT8 sdhc_acpi_rockchip_dsm_uuid[ACPI_UUID_LENGTH] = { 50 0xb0, 0xdd, 0x4a, 0x43, 0xf3, 0x8f, 0xd5, 0x49, 51 0xa7, 0x24, 0x95, 0x84, 0x4b, 0x79, 0xad, 0x1f 52 }; 53 #define ROCKCHIP_DSM_REV 0 54 #define ROCKCHIP_DSM_FUNC_SET_CARD_CLOCK 1 55 56 #define _COMPONENT ACPI_RESOURCE_COMPONENT 57 ACPI_MODULE_NAME ("sdhc_acpi") 58 59 static int sdhc_acpi_match(device_t, cfdata_t, void *); 60 static void sdhc_acpi_attach(device_t, device_t, void *); 61 static int sdhc_acpi_detach(device_t, int); 62 static bool sdhc_acpi_resume(device_t, const pmf_qual_t *); 63 64 struct sdhc_acpi_softc { 65 struct sdhc_softc sc; 66 bus_space_tag_t sc_memt; 67 bus_space_handle_t sc_memh; 68 bus_size_t sc_memsize; 69 void *sc_ih; 70 ACPI_HANDLE sc_handle; 71 72 ACPI_HANDLE sc_crs, sc_srs; 73 ACPI_BUFFER sc_crs_buffer; 74 }; 75 76 CFATTACH_DECL_NEW(sdhc_acpi, sizeof(struct sdhc_acpi_softc), 77 sdhc_acpi_match, sdhc_acpi_attach, sdhc_acpi_detach, NULL); 78 79 static void sdhc_acpi_intel_emmc_hw_reset(struct sdhc_softc *, 80 struct sdhc_host *); 81 82 static int sdhc_acpi_rockchip_bus_clock(struct sdhc_softc *, 83 int); 84 85 static const struct sdhc_acpi_slot { 86 const char *hid; 87 const char *uid; 88 int type; 89 #define SLOT_TYPE_SD 0 /* SD or SDIO */ 90 #define SLOT_TYPE_EMMC 1 /* eMMC */ 91 uint32_t flags; 92 } sdhc_acpi_slot_map[] = { 93 { .hid = "80865ACA", .type = SLOT_TYPE_SD }, 94 { .hid = "80865ACC", .type = SLOT_TYPE_EMMC }, 95 { .hid = "80865AD0", .type = SLOT_TYPE_SD }, 96 { .hid = "80860F14", .uid = "1", .type = SLOT_TYPE_EMMC }, 97 { .hid = "80860F14", .uid = "3", .type = SLOT_TYPE_SD }, 98 { .hid = "80860F16", .type = SLOT_TYPE_SD }, 99 { .hid = "INT33BB", .uid = "2", .type = SLOT_TYPE_SD }, 100 { .hid = "INT33BB", .uid = "3", .type = SLOT_TYPE_SD }, 101 { .hid = "INT33C6", .type = SLOT_TYPE_SD }, 102 { .hid = "INT3436", .type = SLOT_TYPE_SD }, 103 { .hid = "INT344D", .type = SLOT_TYPE_SD }, 104 { .hid = "NXP0003", .uid = "0", .type = SLOT_TYPE_SD, 105 .flags = SDHC_ESDHC_FLAGS }, 106 { .hid = "NXP0003", .uid = "1", .type = SLOT_TYPE_EMMC, 107 .flags = SDHC_ESDHC_FLAGS }, 108 { .hid = "RKCP0D40", .type = SLOT_TYPE_SD, 109 .flags = SDHC_FLAG_32BIT_ACCESS | 110 SDHC_FLAG_8BIT_MODE | 111 SDHC_FLAG_SINGLE_POWER_WRITE }, 112 113 /* Generic IDs last */ 114 { .hid = "PNP0D40", .type = SLOT_TYPE_SD }, 115 { .hid = "PNP0FFF", .uid = "3", .type = SLOT_TYPE_SD }, 116 }; 117 118 static const struct sdhc_acpi_slot * 119 sdhc_acpi_find_slot(ACPI_DEVICE_INFO *ad) 120 { 121 const struct sdhc_acpi_slot *slot; 122 const char *hid, *uid; 123 size_t i; 124 125 hid = ad->HardwareId.String; 126 uid = ad->UniqueId.String; 127 128 if (!(ad->Valid & ACPI_VALID_HID) || hid == NULL) 129 return NULL; 130 131 for (i = 0; i < __arraycount(sdhc_acpi_slot_map); i++) { 132 slot = &sdhc_acpi_slot_map[i]; 133 const char * const slot_id[] = { slot->hid, NULL }; 134 if (acpi_match_hid(ad, slot_id)) { 135 if (slot->uid == NULL || 136 ((ad->Valid & ACPI_VALID_UID) != 0 && 137 uid != NULL && 138 strcmp(uid, slot->uid) == 0)) 139 return slot; 140 } 141 } 142 return NULL; 143 } 144 145 static int 146 sdhc_acpi_match(device_t parent, cfdata_t match, void *opaque) 147 { 148 struct acpi_attach_args *aa = opaque; 149 150 if (aa->aa_node->ad_type != ACPI_TYPE_DEVICE) 151 return 0; 152 153 return sdhc_acpi_find_slot(aa->aa_node->ad_devinfo) != NULL; 154 } 155 156 static void 157 sdhc_acpi_attach(device_t parent, device_t self, void *opaque) 158 { 159 struct sdhc_acpi_softc *sc = device_private(self); 160 struct acpi_attach_args *aa = opaque; 161 const struct sdhc_acpi_slot *slot; 162 struct acpi_resources res; 163 struct acpi_mem *mem; 164 struct acpi_irq *irq; 165 ACPI_STATUS rv; 166 ACPI_INTEGER clock_freq; 167 ACPI_INTEGER caps, caps_mask; 168 ACPI_INTEGER funcs; 169 170 sc->sc.sc_dev = self; 171 sc->sc.sc_dmat = aa->aa_dmat; 172 sc->sc.sc_host = NULL; 173 sc->sc_memt = aa->aa_memt; 174 sc->sc_handle = aa->aa_node->ad_handle; 175 176 slot = sdhc_acpi_find_slot(aa->aa_node->ad_devinfo); 177 if (slot->type == SLOT_TYPE_EMMC) 178 sc->sc.sc_vendor_hw_reset = sdhc_acpi_intel_emmc_hw_reset; 179 180 rv = acpi_dsm_query(sc->sc_handle, sdhc_acpi_rockchip_dsm_uuid, 181 ROCKCHIP_DSM_REV, &funcs); 182 if (ACPI_SUCCESS(rv) && 183 ISSET(funcs, __BIT(ROCKCHIP_DSM_FUNC_SET_CARD_CLOCK))) { 184 sc->sc.sc_vendor_bus_clock = sdhc_acpi_rockchip_bus_clock; 185 } 186 187 rv = acpi_resource_parse(self, aa->aa_node->ad_handle, "_CRS", 188 &res, &acpi_resource_parse_ops_default); 189 if (ACPI_FAILURE(rv)) 190 return; 191 192 AcpiGetHandle(aa->aa_node->ad_handle, "_CRS", &sc->sc_crs); 193 AcpiGetHandle(aa->aa_node->ad_handle, "_SRS", &sc->sc_srs); 194 if (sc->sc_crs && sc->sc_srs) { 195 /* XXX Why need this? */ 196 sc->sc_crs_buffer.Pointer = NULL; 197 sc->sc_crs_buffer.Length = ACPI_ALLOCATE_LOCAL_BUFFER; 198 rv = AcpiGetCurrentResources(sc->sc_crs, &sc->sc_crs_buffer); 199 if (ACPI_FAILURE(rv)) 200 sc->sc_crs = sc->sc_srs = NULL; 201 } 202 203 mem = acpi_res_mem(&res, 0); 204 irq = acpi_res_irq(&res, 0); 205 if (mem == NULL || irq == NULL) { 206 aprint_error_dev(self, "incomplete resources\n"); 207 goto cleanup; 208 } 209 if (mem->ar_length == 0) { 210 aprint_error_dev(self, "zero length memory resource\n"); 211 goto cleanup; 212 } 213 sc->sc_memsize = mem->ar_length; 214 215 if (bus_space_map(sc->sc_memt, mem->ar_base, sc->sc_memsize, 0, 216 &sc->sc_memh)) { 217 aprint_error_dev(self, "couldn't map registers\n"); 218 goto cleanup; 219 } 220 221 sc->sc_ih = acpi_intr_establish(self, 222 (uint64_t)(uintptr_t)aa->aa_node->ad_handle, 223 IPL_BIO, false, sdhc_intr, &sc->sc, device_xname(self)); 224 if (sc->sc_ih == NULL) { 225 aprint_error_dev(self, 226 "couldn't establish interrupt handler\n"); 227 goto unmap; 228 } 229 230 sc->sc.sc_host = kmem_zalloc(sizeof(struct sdhc_host *), KM_SLEEP); 231 232 sc->sc.sc_flags |= slot->flags; 233 234 /* Enable DMA transfer */ 235 sc->sc.sc_flags |= SDHC_FLAG_USE_DMA; 236 237 /* Read clock frequency from device properties */ 238 rv = acpi_dsd_integer(aa->aa_node->ad_handle, "clock-frequency", 239 &clock_freq); 240 if (ACPI_SUCCESS(rv)) { 241 sc->sc.sc_clkbase = clock_freq / 1000; 242 sc->sc.sc_flags |= SDHC_FLAG_NO_CLKBASE; 243 } 244 245 /* Capability overrides */ 246 caps = caps_mask = 0; 247 acpi_dsd_integer(aa->aa_node->ad_handle, "sdhci-caps-mask", &caps_mask); 248 acpi_dsd_integer(aa->aa_node->ad_handle, "sdhci-caps", &caps); 249 if (caps || caps_mask) { 250 sc->sc.sc_caps = bus_space_read_4(sc->sc_memt, sc->sc_memh, 251 SDHC_CAPABILITIES); 252 sc->sc.sc_caps &= ~(caps_mask & 0xffffffff); 253 sc->sc.sc_caps |= (caps & 0xffffffff); 254 sc->sc.sc_caps2 = bus_space_read_4(sc->sc_memt, 255 sc->sc_memh, SDHC_CAPABILITIES2); 256 sc->sc.sc_caps2 &= ~(caps_mask >> 32); 257 sc->sc.sc_caps2 |= (caps >> 32); 258 sc->sc.sc_flags |= SDHC_FLAG_HOSTCAPS; 259 } 260 261 if (sdhc_host_found(&sc->sc, sc->sc_memt, sc->sc_memh, 262 sc->sc_memsize) != 0) { 263 aprint_error_dev(self, "couldn't initialize host\n"); 264 goto fail; 265 } 266 267 if (!pmf_device_register1(self, sdhc_suspend, sdhc_acpi_resume, 268 sdhc_shutdown)) { 269 aprint_error_dev(self, "couldn't establish powerhook\n"); 270 } 271 272 acpi_resource_cleanup(&res); 273 return; 274 275 fail: 276 if (sc->sc.sc_host != NULL) 277 kmem_free(sc->sc.sc_host, sizeof(struct sdhc_host *)); 278 sc->sc.sc_host = NULL; 279 if (sc->sc_ih != NULL) 280 acpi_intr_disestablish(sc->sc_ih); 281 sc->sc_ih = NULL; 282 unmap: 283 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_memsize); 284 sc->sc_memsize = 0; 285 cleanup: 286 if (sc->sc_crs_buffer.Pointer) 287 ACPI_FREE(sc->sc_crs_buffer.Pointer); 288 sc->sc_crs_buffer.Pointer = NULL; 289 acpi_resource_cleanup(&res); 290 } 291 292 static int 293 sdhc_acpi_detach(device_t self, int flags) 294 { 295 struct sdhc_acpi_softc *sc = device_private(self); 296 int rv; 297 298 pmf_device_deregister(self); 299 300 rv = sdhc_detach(&sc->sc, flags); 301 if (rv) 302 return rv; 303 304 if (sc->sc_ih != NULL) 305 acpi_intr_disestablish(sc->sc_ih); 306 307 if (sc->sc.sc_host != NULL) 308 kmem_free(sc->sc.sc_host, sizeof(struct sdhc_host *)); 309 310 if (sc->sc_memsize > 0) 311 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_memsize); 312 313 if (sc->sc_crs_buffer.Pointer) 314 ACPI_FREE(sc->sc_crs_buffer.Pointer); 315 316 return 0; 317 } 318 319 static bool 320 sdhc_acpi_resume(device_t self, const pmf_qual_t *qual) 321 { 322 struct sdhc_acpi_softc *sc = device_private(self); 323 ACPI_STATUS rv; 324 325 if (sc->sc_crs && sc->sc_srs) { 326 rv = AcpiSetCurrentResources(sc->sc_srs, &sc->sc_crs_buffer); 327 if (ACPI_FAILURE(rv)) 328 printf("%s: _SRS failed: %s\n", 329 device_xname(self), AcpiFormatException(rv)); 330 } 331 332 return sdhc_resume(self, qual); 333 } 334 335 static void 336 sdhc_acpi_intel_emmc_hw_reset(struct sdhc_softc *sc, struct sdhc_host *hp) 337 { 338 kmutex_t *plock = sdhc_host_lock(hp); 339 uint8_t reg; 340 341 mutex_enter(plock); 342 343 reg = sdhc_host_read_1(hp, SDHC_POWER_CTL); 344 reg |= 0x10; 345 sdhc_host_write_1(hp, SDHC_POWER_CTL, reg); 346 347 sdmmc_delay(10); 348 349 reg &= ~0x10; 350 sdhc_host_write_1(hp, SDHC_POWER_CTL, reg); 351 352 sdmmc_delay(1000); 353 354 mutex_exit(plock); 355 } 356 357 static int 358 sdhc_acpi_rockchip_bus_clock(struct sdhc_softc *sc, int freq) 359 { 360 struct sdhc_acpi_softc *asc = (struct sdhc_acpi_softc *)sc; 361 ACPI_STATUS rv; 362 ACPI_OBJECT targetfreq; 363 ACPI_OBJECT arg3; 364 ACPI_INTEGER actfreq; 365 366 targetfreq.Integer.Type = ACPI_TYPE_INTEGER; 367 targetfreq.Integer.Value = freq * 1000; 368 arg3.Package.Type = ACPI_TYPE_PACKAGE; 369 arg3.Package.Count = 1; 370 arg3.Package.Elements = &targetfreq; 371 372 rv = acpi_dsm_integer(asc->sc_handle, sdhc_acpi_rockchip_dsm_uuid, 373 ROCKCHIP_DSM_REV, ROCKCHIP_DSM_FUNC_SET_CARD_CLOCK, &arg3, 374 &actfreq); 375 if (ACPI_FAILURE(rv)) { 376 aprint_error_dev(sc->sc_dev, 377 "eMMC Set Card Clock DSM failed: %s\n", 378 AcpiFormatException(rv)); 379 return ENXIO; 380 } 381 382 aprint_debug_dev(sc->sc_dev, 383 "eMMC Set Card Clock DSM returned %" PRIu64 " Hz\n", actfreq); 384 if (actfreq == 0 && freq != 0) { 385 return EINVAL; 386 } 387 388 return 0; 389 } 390