1 /* $NetBSD: acpi_cpu_cstate.c,v 1.53 2011/06/22 08:49:54 jruoho Exp $ */ 2 3 /*- 4 * Copyright (c) 2010, 2011 Jukka Ruohonen <jruohonen@iki.fi> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: acpi_cpu_cstate.c,v 1.53 2011/06/22 08:49:54 jruoho Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/cpu.h> 34 #include <sys/device.h> 35 #include <sys/kernel.h> 36 #include <sys/mutex.h> 37 #include <sys/timetc.h> 38 39 #include <dev/acpi/acpireg.h> 40 #include <dev/acpi/acpivar.h> 41 #include <dev/acpi/acpi_cpu.h> 42 #include <dev/acpi/acpi_timer.h> 43 44 #include <machine/acpi_machdep.h> 45 46 #define _COMPONENT ACPI_BUS_COMPONENT 47 ACPI_MODULE_NAME ("acpi_cpu_cstate") 48 49 static ACPI_STATUS acpicpu_cstate_cst(struct acpicpu_softc *); 50 static ACPI_STATUS acpicpu_cstate_cst_add(struct acpicpu_softc *, 51 ACPI_OBJECT *, int ); 52 static void acpicpu_cstate_cst_bios(void); 53 static void acpicpu_cstate_memset(struct acpicpu_softc *); 54 static ACPI_STATUS acpicpu_cstate_dep(struct acpicpu_softc *); 55 static void acpicpu_cstate_fadt(struct acpicpu_softc *); 56 static void acpicpu_cstate_quirks(struct acpicpu_softc *); 57 static int acpicpu_cstate_latency(struct acpicpu_softc *); 58 static bool acpicpu_cstate_bm_check(void); 59 static void acpicpu_cstate_idle_enter(struct acpicpu_softc *,int); 60 61 extern struct acpicpu_softc **acpicpu_sc; 62 63 /* 64 * XXX: The local APIC timer (as well as TSC) is typically stopped in C3. 65 * For now, we cannot but disable C3. But there appears to be timer- 66 * related interrupt issues also in C2. The only entirely safe option 67 * at the moment is to use C1. 68 */ 69 #ifdef ACPICPU_ENABLE_C3 70 static int cs_state_max = ACPI_STATE_C3; 71 #else 72 static int cs_state_max = ACPI_STATE_C1; 73 #endif 74 75 void 76 acpicpu_cstate_attach(device_t self) 77 { 78 struct acpicpu_softc *sc = device_private(self); 79 ACPI_STATUS rv; 80 81 /* 82 * Either use the preferred _CST or resort to FADT. 83 */ 84 rv = acpicpu_cstate_cst(sc); 85 86 switch (rv) { 87 88 case AE_OK: 89 acpicpu_cstate_cst_bios(); 90 break; 91 92 default: 93 sc->sc_flags |= ACPICPU_FLAG_C_FADT; 94 acpicpu_cstate_fadt(sc); 95 break; 96 } 97 98 /* 99 * Query the optional _CSD. 100 */ 101 rv = acpicpu_cstate_dep(sc); 102 103 if (ACPI_SUCCESS(rv)) 104 sc->sc_flags |= ACPICPU_FLAG_C_DEP; 105 106 sc->sc_flags |= ACPICPU_FLAG_C; 107 108 acpicpu_cstate_quirks(sc); 109 } 110 111 void 112 acpicpu_cstate_detach(device_t self) 113 { 114 struct acpicpu_softc *sc = device_private(self); 115 116 if ((sc->sc_flags & ACPICPU_FLAG_C) == 0) 117 return; 118 119 (void)acpicpu_md_cstate_stop(); 120 121 sc->sc_flags &= ~ACPICPU_FLAG_C; 122 } 123 124 void 125 acpicpu_cstate_start(device_t self) 126 { 127 struct acpicpu_softc *sc = device_private(self); 128 129 (void)acpicpu_md_cstate_start(sc); 130 } 131 132 void 133 acpicpu_cstate_suspend(void *aux) 134 { 135 /* Nothing. */ 136 } 137 138 void 139 acpicpu_cstate_resume(void *aux) 140 { 141 acpicpu_cstate_callback(aux); 142 } 143 144 void 145 acpicpu_cstate_callback(void *aux) 146 { 147 struct acpicpu_softc *sc; 148 device_t self = aux; 149 150 sc = device_private(self); 151 152 if ((sc->sc_flags & ACPICPU_FLAG_C_FADT) != 0) 153 return; 154 155 mutex_enter(&sc->sc_mtx); 156 (void)acpicpu_cstate_cst(sc); 157 mutex_exit(&sc->sc_mtx); 158 } 159 160 static ACPI_STATUS 161 acpicpu_cstate_cst(struct acpicpu_softc *sc) 162 { 163 ACPI_OBJECT *elm, *obj; 164 ACPI_BUFFER buf; 165 ACPI_STATUS rv; 166 uint32_t i, n; 167 uint8_t count; 168 169 rv = acpi_eval_struct(sc->sc_node->ad_handle, "_CST", &buf); 170 171 if (ACPI_FAILURE(rv)) 172 return rv; 173 174 obj = buf.Pointer; 175 176 if (obj->Type != ACPI_TYPE_PACKAGE) { 177 rv = AE_TYPE; 178 goto out; 179 } 180 181 if (obj->Package.Count < 2) { 182 rv = AE_LIMIT; 183 goto out; 184 } 185 186 elm = obj->Package.Elements; 187 188 if (elm[0].Type != ACPI_TYPE_INTEGER) { 189 rv = AE_TYPE; 190 goto out; 191 } 192 193 n = elm[0].Integer.Value; 194 195 if (n != obj->Package.Count - 1) { 196 rv = AE_BAD_VALUE; 197 goto out; 198 } 199 200 if (n > ACPI_C_STATES_MAX) { 201 rv = AE_LIMIT; 202 goto out; 203 } 204 205 acpicpu_cstate_memset(sc); 206 207 CTASSERT(ACPI_STATE_C0 == 0 && ACPI_STATE_C1 == 1); 208 CTASSERT(ACPI_STATE_C2 == 2 && ACPI_STATE_C3 == 3); 209 210 for (count = 0, i = 1; i <= n; i++) { 211 212 elm = &obj->Package.Elements[i]; 213 rv = acpicpu_cstate_cst_add(sc, elm, i); 214 215 if (ACPI_SUCCESS(rv)) 216 count++; 217 } 218 219 rv = (count != 0) ? AE_OK : AE_NOT_EXIST; 220 221 out: 222 if (buf.Pointer != NULL) 223 ACPI_FREE(buf.Pointer); 224 225 return rv; 226 } 227 228 static ACPI_STATUS 229 acpicpu_cstate_cst_add(struct acpicpu_softc *sc, ACPI_OBJECT *elm, int i) 230 { 231 struct acpicpu_cstate *cs = sc->sc_cstate; 232 struct acpicpu_cstate state; 233 struct acpicpu_reg *reg; 234 ACPI_STATUS rv = AE_OK; 235 ACPI_OBJECT *obj; 236 uint32_t type; 237 238 (void)memset(&state, 0, sizeof(*cs)); 239 240 state.cs_flags = ACPICPU_FLAG_C_BM_STS; 241 242 if (elm->Type != ACPI_TYPE_PACKAGE) { 243 rv = AE_TYPE; 244 goto out; 245 } 246 247 if (elm->Package.Count != 4) { 248 rv = AE_LIMIT; 249 goto out; 250 } 251 252 /* 253 * Type. 254 */ 255 obj = &elm->Package.Elements[1]; 256 257 if (obj->Type != ACPI_TYPE_INTEGER) { 258 rv = AE_TYPE; 259 goto out; 260 } 261 262 type = obj->Integer.Value; 263 264 if (type < ACPI_STATE_C1 || type > ACPI_STATE_C3) { 265 rv = AE_TYPE; 266 goto out; 267 } 268 269 /* 270 * Latency. 271 */ 272 obj = &elm->Package.Elements[2]; 273 274 if (obj->Type != ACPI_TYPE_INTEGER) { 275 rv = AE_TYPE; 276 goto out; 277 } 278 279 state.cs_latency = obj->Integer.Value; 280 281 /* 282 * Power. 283 */ 284 obj = &elm->Package.Elements[3]; 285 286 if (obj->Type != ACPI_TYPE_INTEGER) { 287 rv = AE_TYPE; 288 goto out; 289 } 290 291 state.cs_power = obj->Integer.Value; 292 293 /* 294 * Register. 295 */ 296 obj = &elm->Package.Elements[0]; 297 298 if (obj->Type != ACPI_TYPE_BUFFER) { 299 rv = AE_TYPE; 300 goto out; 301 } 302 303 CTASSERT(sizeof(struct acpicpu_reg) == 15); 304 305 if (obj->Buffer.Length < sizeof(struct acpicpu_reg)) { 306 rv = AE_LIMIT; 307 goto out; 308 } 309 310 reg = (struct acpicpu_reg *)obj->Buffer.Pointer; 311 312 switch (reg->reg_spaceid) { 313 314 case ACPI_ADR_SPACE_SYSTEM_IO: 315 state.cs_method = ACPICPU_C_STATE_SYSIO; 316 317 if (reg->reg_addr == 0) { 318 rv = AE_AML_ILLEGAL_ADDRESS; 319 goto out; 320 } 321 322 if (reg->reg_bitwidth != 8) { 323 rv = AE_AML_BAD_RESOURCE_LENGTH; 324 goto out; 325 } 326 327 state.cs_addr = reg->reg_addr; 328 break; 329 330 case ACPI_ADR_SPACE_FIXED_HARDWARE: 331 state.cs_method = ACPICPU_C_STATE_FFH; 332 333 switch (type) { 334 335 case ACPI_STATE_C1: 336 337 /* 338 * If ACPI wants native access (FFH), but the 339 * MD code does not support MONITOR/MWAIT, use 340 * HLT for C1 and error out for higher C-states. 341 */ 342 if ((sc->sc_flags & ACPICPU_FLAG_C_FFH) == 0) 343 state.cs_method = ACPICPU_C_STATE_HALT; 344 345 break; 346 347 default: 348 349 if ((sc->sc_flags & ACPICPU_FLAG_C_FFH) == 0) { 350 rv = AE_SUPPORT; 351 goto out; 352 } 353 } 354 355 if (sc->sc_cap != 0) { 356 357 /* 358 * The _CST FFH GAS encoding may contain 359 * additional hints on Intel processors. 360 * Use these to determine whether we can 361 * avoid the bus master activity check. 362 */ 363 if ((reg->reg_accesssize & ACPICPU_PDC_GAS_BM) == 0) 364 state.cs_flags &= ~ACPICPU_FLAG_C_BM_STS; 365 } 366 367 break; 368 369 default: 370 rv = AE_AML_INVALID_SPACE_ID; 371 goto out; 372 } 373 374 /* 375 * As some systems define the type arbitrarily, 376 * we use a sequential counter instead of the 377 * BIOS data. For instance, AMD family 14h is 378 * instructed to only use the value 2; see 379 * 380 * Advanced Micro Devices: BIOS and Kernel 381 * Developer's Guide (BKDG) for AMD Family 382 * 14h Models 00h-0Fh Processors. Revision 383 * 3.00, January 4, 2011. 384 */ 385 if (i != (int)type) { 386 387 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 388 "C%d != C%u from BIOS", i, type)); 389 } 390 391 KASSERT(cs[i].cs_method == 0); 392 393 cs[i].cs_addr = state.cs_addr; 394 cs[i].cs_power = state.cs_power; 395 cs[i].cs_flags = state.cs_flags; 396 cs[i].cs_method = state.cs_method; 397 cs[i].cs_latency = state.cs_latency; 398 399 out: 400 if (ACPI_FAILURE(rv)) 401 aprint_error_dev(sc->sc_dev, "failed to add " 402 "C-state: %s\n", AcpiFormatException(rv)); 403 404 return rv; 405 } 406 407 static void 408 acpicpu_cstate_cst_bios(void) 409 { 410 const uint8_t val = AcpiGbl_FADT.CstControl; 411 const uint32_t addr = AcpiGbl_FADT.SmiCommand; 412 413 if (addr == 0 || val == 0) 414 return; 415 416 (void)AcpiOsWritePort(addr, val, 8); 417 } 418 419 static void 420 acpicpu_cstate_memset(struct acpicpu_softc *sc) 421 { 422 uint8_t i = 0; 423 424 while (i < __arraycount(sc->sc_cstate)) { 425 426 sc->sc_cstate[i].cs_addr = 0; 427 sc->sc_cstate[i].cs_power = 0; 428 sc->sc_cstate[i].cs_flags = 0; 429 sc->sc_cstate[i].cs_method = 0; 430 sc->sc_cstate[i].cs_latency = 0; 431 432 i++; 433 } 434 } 435 436 static ACPI_STATUS 437 acpicpu_cstate_dep(struct acpicpu_softc *sc) 438 { 439 ACPI_OBJECT *elm, *obj; 440 ACPI_BUFFER buf; 441 ACPI_STATUS rv; 442 uint32_t val; 443 uint8_t i, n; 444 445 rv = acpi_eval_struct(sc->sc_node->ad_handle, "_CSD", &buf); 446 447 if (ACPI_FAILURE(rv)) 448 goto out; 449 450 obj = buf.Pointer; 451 452 if (obj->Type != ACPI_TYPE_PACKAGE) { 453 rv = AE_TYPE; 454 goto out; 455 } 456 457 if (obj->Package.Count != 1) { 458 rv = AE_LIMIT; 459 goto out; 460 } 461 462 elm = &obj->Package.Elements[0]; 463 464 if (obj->Type != ACPI_TYPE_PACKAGE) { 465 rv = AE_TYPE; 466 goto out; 467 } 468 469 n = elm->Package.Count; 470 471 if (n != 6) { 472 rv = AE_LIMIT; 473 goto out; 474 } 475 476 elm = elm->Package.Elements; 477 478 for (i = 0; i < n; i++) { 479 480 if (elm[i].Type != ACPI_TYPE_INTEGER) { 481 rv = AE_TYPE; 482 goto out; 483 } 484 485 if (elm[i].Integer.Value > UINT32_MAX) { 486 rv = AE_AML_NUMERIC_OVERFLOW; 487 goto out; 488 } 489 } 490 491 val = elm[1].Integer.Value; 492 493 if (val != 0) 494 aprint_debug_dev(sc->sc_dev, "invalid revision in _CSD\n"); 495 496 val = elm[3].Integer.Value; 497 498 if (val < ACPICPU_DEP_SW_ALL || val > ACPICPU_DEP_HW_ALL) { 499 rv = AE_AML_BAD_RESOURCE_VALUE; 500 goto out; 501 } 502 503 val = elm[4].Integer.Value; 504 505 if (val > sc->sc_ncpus) { 506 rv = AE_BAD_VALUE; 507 goto out; 508 } 509 510 sc->sc_cstate_dep.dep_domain = elm[2].Integer.Value; 511 sc->sc_cstate_dep.dep_type = elm[3].Integer.Value; 512 sc->sc_cstate_dep.dep_ncpus = elm[4].Integer.Value; 513 sc->sc_cstate_dep.dep_index = elm[5].Integer.Value; 514 515 out: 516 if (ACPI_FAILURE(rv) && rv != AE_NOT_FOUND) 517 aprint_debug_dev(sc->sc_dev, "failed to evaluate " 518 "_CSD: %s\n", AcpiFormatException(rv)); 519 520 if (buf.Pointer != NULL) 521 ACPI_FREE(buf.Pointer); 522 523 return rv; 524 } 525 526 static void 527 acpicpu_cstate_fadt(struct acpicpu_softc *sc) 528 { 529 struct acpicpu_cstate *cs = sc->sc_cstate; 530 531 acpicpu_cstate_memset(sc); 532 533 /* 534 * All x86 processors should support C1 (a.k.a. HALT). 535 */ 536 cs[ACPI_STATE_C1].cs_method = ACPICPU_C_STATE_HALT; 537 538 if ((AcpiGbl_FADT.Flags & ACPI_FADT_C1_SUPPORTED) == 0) 539 aprint_debug_dev(sc->sc_dev, "HALT not supported?\n"); 540 541 if (sc->sc_object.ao_pblkaddr == 0) 542 return; 543 544 if (sc->sc_ncpus > 1) { 545 546 if ((AcpiGbl_FADT.Flags & ACPI_FADT_C2_MP_SUPPORTED) == 0) 547 return; 548 } 549 550 cs[ACPI_STATE_C2].cs_method = ACPICPU_C_STATE_SYSIO; 551 cs[ACPI_STATE_C3].cs_method = ACPICPU_C_STATE_SYSIO; 552 553 cs[ACPI_STATE_C2].cs_latency = AcpiGbl_FADT.C2Latency; 554 cs[ACPI_STATE_C3].cs_latency = AcpiGbl_FADT.C3Latency; 555 556 cs[ACPI_STATE_C2].cs_addr = sc->sc_object.ao_pblkaddr + 4; 557 cs[ACPI_STATE_C3].cs_addr = sc->sc_object.ao_pblkaddr + 5; 558 559 /* 560 * The P_BLK length should always be 6. If it 561 * is not, reduce functionality accordingly. 562 */ 563 if (sc->sc_object.ao_pblklen < 5) 564 cs[ACPI_STATE_C2].cs_method = 0; 565 566 if (sc->sc_object.ao_pblklen < 6) 567 cs[ACPI_STATE_C3].cs_method = 0; 568 569 /* 570 * Sanity check the latency levels in FADT. 571 * Values above the thresholds are used to 572 * inform that C-states are not supported. 573 */ 574 CTASSERT(ACPICPU_C_C2_LATENCY_MAX == 100); 575 CTASSERT(ACPICPU_C_C3_LATENCY_MAX == 1000); 576 577 if (AcpiGbl_FADT.C2Latency > ACPICPU_C_C2_LATENCY_MAX) 578 cs[ACPI_STATE_C2].cs_method = 0; 579 580 if (AcpiGbl_FADT.C3Latency > ACPICPU_C_C3_LATENCY_MAX) 581 cs[ACPI_STATE_C3].cs_method = 0; 582 } 583 584 static void 585 acpicpu_cstate_quirks(struct acpicpu_softc *sc) 586 { 587 const uint32_t reg = AcpiGbl_FADT.Pm2ControlBlock; 588 const uint32_t len = AcpiGbl_FADT.Pm2ControlLength; 589 590 /* 591 * Disable C3 for PIIX4. 592 */ 593 if ((sc->sc_flags & ACPICPU_FLAG_PIIX4) != 0) { 594 sc->sc_cstate[ACPI_STATE_C3].cs_method = 0; 595 return; 596 } 597 598 /* 599 * Check bus master arbitration. If ARB_DIS 600 * is not available, processor caches must be 601 * flushed before C3 (ACPI 4.0, section 8.2). 602 */ 603 if (reg != 0 && len != 0) { 604 sc->sc_flags |= ACPICPU_FLAG_C_ARB; 605 return; 606 } 607 608 /* 609 * Disable C3 entirely if WBINVD is not present. 610 */ 611 if ((AcpiGbl_FADT.Flags & ACPI_FADT_WBINVD) == 0) 612 sc->sc_cstate[ACPI_STATE_C3].cs_method = 0; 613 else { 614 /* 615 * If WBINVD is present and functioning properly, 616 * flush all processor caches before entering C3. 617 */ 618 if ((AcpiGbl_FADT.Flags & ACPI_FADT_WBINVD_FLUSH) == 0) 619 sc->sc_flags &= ~ACPICPU_FLAG_C_BM; 620 else 621 sc->sc_cstate[ACPI_STATE_C3].cs_method = 0; 622 } 623 } 624 625 static int 626 acpicpu_cstate_latency(struct acpicpu_softc *sc) 627 { 628 static const uint32_t cs_factor = 3; 629 struct acpicpu_cstate *cs; 630 int i; 631 632 for (i = cs_state_max; i > 0; i--) { 633 634 cs = &sc->sc_cstate[i]; 635 636 if (__predict_false(cs->cs_method == 0)) 637 continue; 638 639 /* 640 * Choose a state if we have previously slept 641 * longer than the worst case latency of the 642 * state times an arbitrary multiplier. 643 */ 644 if (sc->sc_cstate_sleep > cs->cs_latency * cs_factor) 645 return i; 646 } 647 648 return ACPI_STATE_C1; 649 } 650 651 /* 652 * The main idle loop. 653 */ 654 void 655 acpicpu_cstate_idle(void) 656 { 657 struct cpu_info *ci = curcpu(); 658 struct acpicpu_softc *sc; 659 int state; 660 661 acpi_md_OsDisableInterrupt(); 662 663 if (__predict_false(ci->ci_want_resched != 0)) 664 goto out; 665 666 KASSERT(acpicpu_sc != NULL); 667 KASSERT(ci->ci_acpiid < maxcpus); 668 669 sc = acpicpu_sc[ci->ci_acpiid]; 670 671 if (__predict_false(sc == NULL)) 672 goto out; 673 674 KASSERT(ci->ci_ilevel == IPL_NONE); 675 KASSERT((sc->sc_flags & ACPICPU_FLAG_C) != 0); 676 677 if (__predict_false(sc->sc_cold != false)) 678 goto out; 679 680 if (__predict_false(mutex_tryenter(&sc->sc_mtx) == 0)) 681 goto out; 682 683 mutex_exit(&sc->sc_mtx); 684 state = acpicpu_cstate_latency(sc); 685 686 /* 687 * Apply AMD C1E quirk. 688 */ 689 if ((sc->sc_flags & ACPICPU_FLAG_C_C1E) != 0) 690 acpicpu_md_quirk_c1e(); 691 692 /* 693 * Check for bus master activity. Note that particularly usb(4) 694 * causes high activity, which may prevent the use of C3 states. 695 */ 696 if ((sc->sc_cstate[state].cs_flags & ACPICPU_FLAG_C_BM_STS) != 0) { 697 698 if (acpicpu_cstate_bm_check() != false) 699 state--; 700 701 if (__predict_false(sc->sc_cstate[state].cs_method == 0)) 702 state = ACPI_STATE_C1; 703 } 704 705 KASSERT(state != ACPI_STATE_C0); 706 707 if (state != ACPI_STATE_C3) { 708 acpicpu_cstate_idle_enter(sc, state); 709 return; 710 } 711 712 /* 713 * On all recent (Intel) CPUs caches are shared 714 * by CPUs and bus master control is required to 715 * keep these coherent while in C3. Flushing the 716 * CPU caches is only the last resort. 717 */ 718 if ((sc->sc_flags & ACPICPU_FLAG_C_BM) == 0) 719 ACPI_FLUSH_CPU_CACHE(); 720 721 /* 722 * Allow the bus master to request that any given 723 * CPU should return immediately to C0 from C3. 724 */ 725 if ((sc->sc_flags & ACPICPU_FLAG_C_BM) != 0) 726 (void)AcpiWriteBitRegister(ACPI_BITREG_BUS_MASTER_RLD, 1); 727 728 /* 729 * It may be necessary to disable bus master arbitration 730 * to ensure that bus master cycles do not occur while 731 * sleeping in C3 (see ACPI 4.0, section 8.1.4). 732 */ 733 if ((sc->sc_flags & ACPICPU_FLAG_C_ARB) != 0) 734 (void)AcpiWriteBitRegister(ACPI_BITREG_ARB_DISABLE, 1); 735 736 acpicpu_cstate_idle_enter(sc, state); 737 738 /* 739 * Disable bus master wake and re-enable the arbiter. 740 */ 741 if ((sc->sc_flags & ACPICPU_FLAG_C_BM) != 0) 742 (void)AcpiWriteBitRegister(ACPI_BITREG_BUS_MASTER_RLD, 0); 743 744 if ((sc->sc_flags & ACPICPU_FLAG_C_ARB) != 0) 745 (void)AcpiWriteBitRegister(ACPI_BITREG_ARB_DISABLE, 0); 746 747 return; 748 749 out: 750 acpi_md_OsEnableInterrupt(); 751 } 752 753 static void 754 acpicpu_cstate_idle_enter(struct acpicpu_softc *sc, int state) 755 { 756 struct acpicpu_cstate *cs = &sc->sc_cstate[state]; 757 uint32_t end, start, val; 758 759 start = acpitimer_read_fast(NULL); 760 761 switch (cs->cs_method) { 762 763 case ACPICPU_C_STATE_FFH: 764 case ACPICPU_C_STATE_HALT: 765 acpicpu_md_cstate_enter(cs->cs_method, state); 766 break; 767 768 case ACPICPU_C_STATE_SYSIO: 769 (void)AcpiOsReadPort(cs->cs_addr, &val, 8); 770 break; 771 } 772 773 acpi_md_OsEnableInterrupt(); 774 775 cs->cs_evcnt.ev_count++; 776 end = acpitimer_read_fast(NULL); 777 sc->sc_cstate_sleep = hztoms(acpitimer_delta(end, start)) * 1000; 778 } 779 780 static bool 781 acpicpu_cstate_bm_check(void) 782 { 783 uint32_t val = 0; 784 ACPI_STATUS rv; 785 786 rv = AcpiReadBitRegister(ACPI_BITREG_BUS_MASTER_STATUS, &val); 787 788 if (ACPI_FAILURE(rv) || val == 0) 789 return false; 790 791 (void)AcpiWriteBitRegister(ACPI_BITREG_BUS_MASTER_STATUS, 1); 792 793 return true; 794 } 795