1 /* $NetBSD: acpi_cpu_cstate.c,v 1.62 2020/06/04 03:14:36 riastradh Exp $ */ 2 3 /*- 4 * Copyright (c) 2010, 2011 Jukka Ruohonen <jruohonen@iki.fi> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: acpi_cpu_cstate.c,v 1.62 2020/06/04 03:14:36 riastradh Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/cpu.h> 34 #include <sys/device.h> 35 #include <sys/kernel.h> 36 #include <sys/mutex.h> 37 #include <sys/timetc.h> 38 39 #include <dev/acpi/acpireg.h> 40 #include <dev/acpi/acpivar.h> 41 #include <dev/acpi/acpi_cpu.h> 42 #include <dev/acpi/acpi_timer.h> 43 44 #include <machine/acpi_machdep.h> 45 46 #define _COMPONENT ACPI_BUS_COMPONENT 47 ACPI_MODULE_NAME ("acpi_cpu_cstate") 48 49 static ACPI_STATUS acpicpu_cstate_cst(struct acpicpu_softc *); 50 static ACPI_STATUS acpicpu_cstate_cst_add(struct acpicpu_softc *, 51 ACPI_OBJECT *); 52 static void acpicpu_cstate_cst_bios(void); 53 static void acpicpu_cstate_memset(struct acpicpu_softc *); 54 static ACPI_STATUS acpicpu_cstate_dep(struct acpicpu_softc *); 55 static void acpicpu_cstate_fadt(struct acpicpu_softc *); 56 static void acpicpu_cstate_quirks(struct acpicpu_softc *); 57 static int acpicpu_cstate_latency(struct acpicpu_softc *); 58 static bool acpicpu_cstate_bm_check(void); 59 static void acpicpu_cstate_idle_enter(struct acpicpu_softc *,int); 60 61 extern struct acpicpu_softc **acpicpu_sc; 62 63 /* 64 * XXX: The local APIC timer (as well as TSC) is typically stopped in C3. 65 * For now, we cannot but disable C3. But there appears to be timer- 66 * related interrupt issues also in C2. The only entirely safe option 67 * at the moment is to use C1. 68 */ 69 #ifdef ACPICPU_ENABLE_C3 70 static int cs_state_max = ACPI_STATE_C3; 71 #else 72 static int cs_state_max = ACPI_STATE_C1; 73 #endif 74 75 void 76 acpicpu_cstate_attach(device_t self) 77 { 78 struct acpicpu_softc *sc = device_private(self); 79 ACPI_STATUS rv; 80 81 /* 82 * Either use the preferred _CST or resort to FADT. 83 */ 84 rv = acpicpu_cstate_cst(sc); 85 86 switch (rv) { 87 88 case AE_OK: 89 acpicpu_cstate_cst_bios(); 90 break; 91 92 default: 93 sc->sc_flags |= ACPICPU_FLAG_C_FADT; 94 acpicpu_cstate_fadt(sc); 95 break; 96 } 97 98 /* 99 * Query the optional _CSD. 100 */ 101 rv = acpicpu_cstate_dep(sc); 102 103 if (ACPI_SUCCESS(rv)) 104 sc->sc_flags |= ACPICPU_FLAG_C_DEP; 105 106 sc->sc_flags |= ACPICPU_FLAG_C; 107 108 acpicpu_cstate_quirks(sc); 109 } 110 111 void 112 acpicpu_cstate_detach(device_t self) 113 { 114 struct acpicpu_softc *sc = device_private(self); 115 116 if ((sc->sc_flags & ACPICPU_FLAG_C) == 0) 117 return; 118 119 (void)acpicpu_md_cstate_stop(); 120 121 sc->sc_flags &= ~ACPICPU_FLAG_C; 122 } 123 124 void 125 acpicpu_cstate_start(device_t self) 126 { 127 struct acpicpu_softc *sc = device_private(self); 128 129 (void)acpicpu_md_cstate_start(sc); 130 } 131 132 void 133 acpicpu_cstate_suspend(void *aux) 134 { 135 /* Nothing. */ 136 } 137 138 void 139 acpicpu_cstate_resume(void *aux) 140 { 141 acpicpu_cstate_callback(aux); 142 } 143 144 void 145 acpicpu_cstate_callback(void *aux) 146 { 147 struct acpicpu_softc *sc; 148 device_t self = aux; 149 150 sc = device_private(self); 151 152 if ((sc->sc_flags & ACPICPU_FLAG_C_FADT) != 0) 153 return; 154 155 mutex_enter(&sc->sc_mtx); 156 (void)acpicpu_cstate_cst(sc); 157 mutex_exit(&sc->sc_mtx); 158 } 159 160 static ACPI_STATUS 161 acpicpu_cstate_cst(struct acpicpu_softc *sc) 162 { 163 struct acpicpu_cstate *cs = sc->sc_cstate; 164 ACPI_OBJECT *elm, *obj; 165 ACPI_BUFFER buf; 166 ACPI_STATUS rv; 167 uint32_t i, n; 168 uint8_t count; 169 170 rv = acpi_eval_struct(sc->sc_node->ad_handle, "_CST", &buf); 171 172 if (ACPI_FAILURE(rv)) 173 return rv; 174 175 obj = buf.Pointer; 176 177 if (obj->Type != ACPI_TYPE_PACKAGE) { 178 rv = AE_TYPE; 179 goto out; 180 } 181 182 if (obj->Package.Count < 2) { 183 rv = AE_LIMIT; 184 goto out; 185 } 186 187 elm = obj->Package.Elements; 188 189 if (elm[0].Type != ACPI_TYPE_INTEGER) { 190 rv = AE_TYPE; 191 goto out; 192 } 193 194 n = elm[0].Integer.Value; 195 196 if (n != obj->Package.Count - 1) { 197 rv = AE_BAD_VALUE; 198 goto out; 199 } 200 201 if (n > ACPI_C_STATES_MAX) { 202 rv = AE_LIMIT; 203 goto out; 204 } 205 206 acpicpu_cstate_memset(sc); 207 208 /* 209 * All x86 processors should support C1 (a.k.a. HALT). 210 */ 211 cs[ACPI_STATE_C1].cs_method = ACPICPU_C_STATE_HALT; 212 213 CTASSERT(ACPI_STATE_C0 == 0 && ACPI_STATE_C1 == 1); 214 CTASSERT(ACPI_STATE_C2 == 2 && ACPI_STATE_C3 == 3); 215 216 for (count = 0, i = 1; i <= n; i++) { 217 218 elm = &obj->Package.Elements[i]; 219 rv = acpicpu_cstate_cst_add(sc, elm); 220 221 if (ACPI_SUCCESS(rv)) 222 count++; 223 } 224 225 rv = (count != 0) ? AE_OK : AE_NOT_EXIST; 226 227 out: 228 if (buf.Pointer != NULL) 229 ACPI_FREE(buf.Pointer); 230 231 return rv; 232 } 233 234 static ACPI_STATUS 235 acpicpu_cstate_cst_add(struct acpicpu_softc *sc, ACPI_OBJECT *elm) 236 { 237 struct acpicpu_cstate *cs = sc->sc_cstate; 238 struct acpicpu_cstate state; 239 struct acpicpu_reg *reg; 240 ACPI_STATUS rv = AE_OK; 241 ACPI_OBJECT *obj; 242 uint32_t type; 243 244 (void)memset(&state, 0, sizeof(*cs)); 245 246 if (elm->Type != ACPI_TYPE_PACKAGE) { 247 rv = AE_TYPE; 248 goto out; 249 } 250 251 if (elm->Package.Count != 4) { 252 rv = AE_LIMIT; 253 goto out; 254 } 255 256 /* 257 * Type. 258 */ 259 obj = &elm->Package.Elements[1]; 260 261 if (obj->Type != ACPI_TYPE_INTEGER) { 262 rv = AE_TYPE; 263 goto out; 264 } 265 266 type = obj->Integer.Value; 267 268 if (type < ACPI_STATE_C1 || type > ACPI_STATE_C3) { 269 rv = AE_TYPE; 270 goto out; 271 } 272 273 /* 274 * Latency. 275 */ 276 obj = &elm->Package.Elements[2]; 277 278 if (obj->Type != ACPI_TYPE_INTEGER) { 279 rv = AE_TYPE; 280 goto out; 281 } 282 283 state.cs_latency = obj->Integer.Value; 284 285 /* 286 * Power. 287 */ 288 obj = &elm->Package.Elements[3]; 289 290 if (obj->Type != ACPI_TYPE_INTEGER) { 291 rv = AE_TYPE; 292 goto out; 293 } 294 295 state.cs_power = obj->Integer.Value; 296 297 /* 298 * Register. 299 */ 300 obj = &elm->Package.Elements[0]; 301 302 if (obj->Type != ACPI_TYPE_BUFFER) { 303 rv = AE_TYPE; 304 goto out; 305 } 306 307 CTASSERT(sizeof(struct acpicpu_reg) == 15); 308 309 if (obj->Buffer.Length < sizeof(struct acpicpu_reg)) { 310 rv = AE_LIMIT; 311 goto out; 312 } 313 314 reg = (struct acpicpu_reg *)obj->Buffer.Pointer; 315 316 switch (reg->reg_spaceid) { 317 318 case ACPI_ADR_SPACE_SYSTEM_IO: 319 state.cs_method = ACPICPU_C_STATE_SYSIO; 320 321 if (reg->reg_addr == 0) { 322 rv = AE_AML_ILLEGAL_ADDRESS; 323 goto out; 324 } 325 326 if (reg->reg_bitwidth != 8) { 327 rv = AE_AML_BAD_RESOURCE_LENGTH; 328 goto out; 329 } 330 331 state.cs_addr = reg->reg_addr; 332 break; 333 334 case ACPI_ADR_SPACE_FIXED_HARDWARE: 335 state.cs_method = ACPICPU_C_STATE_FFH; 336 337 switch (type) { 338 339 case ACPI_STATE_C1: 340 341 /* 342 * If ACPI wants native access (FFH), but the 343 * MD code does not support MONITOR/MWAIT, use 344 * HLT for C1 and error out for higher C-states. 345 */ 346 if ((sc->sc_flags & ACPICPU_FLAG_C_FFH) == 0) 347 state.cs_method = ACPICPU_C_STATE_HALT; 348 349 break; 350 351 case ACPI_STATE_C3: 352 state.cs_flags = ACPICPU_FLAG_C_BM_STS; 353 354 /* FALLTHROUGH */ 355 default: 356 357 if ((sc->sc_flags & ACPICPU_FLAG_C_FFH) == 0) { 358 rv = AE_SUPPORT; 359 goto out; 360 } 361 } 362 363 if (sc->sc_cap != 0) { 364 365 /* 366 * The _CST FFH GAS encoding may contain 367 * additional hints on Intel processors. 368 * Use these to determine whether we can 369 * avoid the bus master activity check. 370 */ 371 if ((reg->reg_accesssize & ACPICPU_PDC_GAS_BM) == 0) 372 state.cs_flags &= ~ACPICPU_FLAG_C_BM_STS; 373 } 374 375 break; 376 377 default: 378 rv = AE_AML_INVALID_SPACE_ID; 379 goto out; 380 } 381 382 cs[type].cs_addr = state.cs_addr; 383 cs[type].cs_power = state.cs_power; 384 cs[type].cs_flags = state.cs_flags; 385 cs[type].cs_method = state.cs_method; 386 cs[type].cs_latency = state.cs_latency; 387 388 out: 389 if (ACPI_FAILURE(rv)) 390 aprint_error_dev(sc->sc_dev, "failed to add " 391 "C-state: %s\n", AcpiFormatException(rv)); 392 393 return rv; 394 } 395 396 static void 397 acpicpu_cstate_cst_bios(void) 398 { 399 const uint8_t val = AcpiGbl_FADT.CstControl; 400 const uint32_t addr = AcpiGbl_FADT.SmiCommand; 401 402 if (addr == 0 || val == 0) 403 return; 404 405 (void)AcpiOsWritePort(addr, val, 8); 406 } 407 408 static void 409 acpicpu_cstate_memset(struct acpicpu_softc *sc) 410 { 411 uint8_t i = 0; 412 413 while (i < __arraycount(sc->sc_cstate)) { 414 415 sc->sc_cstate[i].cs_addr = 0; 416 sc->sc_cstate[i].cs_power = 0; 417 sc->sc_cstate[i].cs_flags = 0; 418 sc->sc_cstate[i].cs_method = 0; 419 sc->sc_cstate[i].cs_latency = 0; 420 421 i++; 422 } 423 } 424 425 static ACPI_STATUS 426 acpicpu_cstate_dep(struct acpicpu_softc *sc) 427 { 428 ACPI_OBJECT *elm, *obj; 429 ACPI_BUFFER buf; 430 ACPI_STATUS rv; 431 uint32_t val; 432 uint8_t i, n; 433 434 rv = acpi_eval_struct(sc->sc_node->ad_handle, "_CSD", &buf); 435 436 if (ACPI_FAILURE(rv)) 437 goto out; 438 439 obj = buf.Pointer; 440 441 if (obj->Type != ACPI_TYPE_PACKAGE) { 442 rv = AE_TYPE; 443 goto out; 444 } 445 446 if (obj->Package.Count != 1) { 447 rv = AE_LIMIT; 448 goto out; 449 } 450 451 elm = &obj->Package.Elements[0]; 452 453 if (obj->Type != ACPI_TYPE_PACKAGE) { 454 rv = AE_TYPE; 455 goto out; 456 } 457 458 n = elm->Package.Count; 459 460 if (n != 6) { 461 rv = AE_LIMIT; 462 goto out; 463 } 464 465 elm = elm->Package.Elements; 466 467 for (i = 0; i < n; i++) { 468 469 if (elm[i].Type != ACPI_TYPE_INTEGER) { 470 rv = AE_TYPE; 471 goto out; 472 } 473 474 if (elm[i].Integer.Value > UINT32_MAX) { 475 rv = AE_AML_NUMERIC_OVERFLOW; 476 goto out; 477 } 478 } 479 480 val = elm[1].Integer.Value; 481 482 if (val != 0) 483 aprint_debug_dev(sc->sc_dev, "invalid revision in _CSD\n"); 484 485 val = elm[3].Integer.Value; 486 487 if (val < ACPICPU_DEP_SW_ALL || val > ACPICPU_DEP_HW_ALL) { 488 rv = AE_AML_BAD_RESOURCE_VALUE; 489 goto out; 490 } 491 492 val = elm[4].Integer.Value; 493 494 if (val > sc->sc_ncpus) { 495 rv = AE_BAD_VALUE; 496 goto out; 497 } 498 499 sc->sc_cstate_dep.dep_domain = elm[2].Integer.Value; 500 sc->sc_cstate_dep.dep_type = elm[3].Integer.Value; 501 sc->sc_cstate_dep.dep_ncpus = elm[4].Integer.Value; 502 sc->sc_cstate_dep.dep_index = elm[5].Integer.Value; 503 504 out: 505 if (ACPI_FAILURE(rv) && rv != AE_NOT_FOUND) 506 aprint_debug_dev(sc->sc_dev, "failed to evaluate " 507 "_CSD: %s\n", AcpiFormatException(rv)); 508 509 if (buf.Pointer != NULL) 510 ACPI_FREE(buf.Pointer); 511 512 return rv; 513 } 514 515 static void 516 acpicpu_cstate_fadt(struct acpicpu_softc *sc) 517 { 518 struct acpicpu_cstate *cs = sc->sc_cstate; 519 520 acpicpu_cstate_memset(sc); 521 522 /* 523 * All x86 processors should support C1 (a.k.a. HALT). 524 */ 525 cs[ACPI_STATE_C1].cs_method = ACPICPU_C_STATE_HALT; 526 527 if ((AcpiGbl_FADT.Flags & ACPI_FADT_C1_SUPPORTED) == 0) 528 aprint_debug_dev(sc->sc_dev, "HALT not supported?\n"); 529 530 if (sc->sc_object.ao_pblkaddr == 0) 531 return; 532 533 if (sc->sc_ncpus > 1) { 534 535 if ((AcpiGbl_FADT.Flags & ACPI_FADT_C2_MP_SUPPORTED) == 0) 536 return; 537 } 538 539 cs[ACPI_STATE_C2].cs_method = ACPICPU_C_STATE_SYSIO; 540 cs[ACPI_STATE_C3].cs_method = ACPICPU_C_STATE_SYSIO; 541 542 cs[ACPI_STATE_C2].cs_latency = AcpiGbl_FADT.C2Latency; 543 cs[ACPI_STATE_C3].cs_latency = AcpiGbl_FADT.C3Latency; 544 545 cs[ACPI_STATE_C2].cs_addr = sc->sc_object.ao_pblkaddr + 4; 546 cs[ACPI_STATE_C3].cs_addr = sc->sc_object.ao_pblkaddr + 5; 547 548 /* 549 * The P_BLK length should always be 6. If it 550 * is not, reduce functionality accordingly. 551 */ 552 if (sc->sc_object.ao_pblklen < 5) 553 cs[ACPI_STATE_C2].cs_method = 0; 554 555 if (sc->sc_object.ao_pblklen < 6) 556 cs[ACPI_STATE_C3].cs_method = 0; 557 558 /* 559 * Sanity check the latency levels in FADT. Values above 560 * the thresholds may be used to inform that C2 and C3 are 561 * not supported -- AMD family 11h is an example; 562 * 563 * Advanced Micro Devices: BIOS and Kernel Developer's 564 * Guide (BKDG) for AMD Family 11h Processors. Section 565 * 2.4.3, Revision 3.00, July, 2008. 566 */ 567 CTASSERT(ACPICPU_C_C2_LATENCY_MAX == 100); 568 CTASSERT(ACPICPU_C_C3_LATENCY_MAX == 1000); 569 570 if (AcpiGbl_FADT.C2Latency > ACPICPU_C_C2_LATENCY_MAX) 571 cs[ACPI_STATE_C2].cs_method = 0; 572 573 if (AcpiGbl_FADT.C3Latency > ACPICPU_C_C3_LATENCY_MAX) 574 cs[ACPI_STATE_C3].cs_method = 0; 575 } 576 577 static void 578 acpicpu_cstate_quirks(struct acpicpu_softc *sc) 579 { 580 const uint32_t reg = AcpiGbl_FADT.Pm2ControlBlock; 581 const uint32_t len = AcpiGbl_FADT.Pm2ControlLength; 582 583 /* 584 * Disable C3 for PIIX4. 585 */ 586 if ((sc->sc_flags & ACPICPU_FLAG_PIIX4) != 0) { 587 sc->sc_cstate[ACPI_STATE_C3].cs_method = 0; 588 return; 589 } 590 591 /* 592 * Check bus master arbitration. If ARB_DIS 593 * is not available, processor caches must be 594 * flushed before C3 (ACPI 4.0, section 8.2). 595 */ 596 if (reg != 0 && len != 0) { 597 sc->sc_flags |= ACPICPU_FLAG_C_ARB; 598 return; 599 } 600 601 /* 602 * Disable C3 entirely if WBINVD is not present. 603 */ 604 if ((AcpiGbl_FADT.Flags & ACPI_FADT_WBINVD) == 0) 605 sc->sc_cstate[ACPI_STATE_C3].cs_method = 0; 606 else { 607 /* 608 * If WBINVD is present and functioning properly, 609 * flush all processor caches before entering C3. 610 */ 611 if ((AcpiGbl_FADT.Flags & ACPI_FADT_WBINVD_FLUSH) == 0) 612 sc->sc_flags &= ~ACPICPU_FLAG_C_BM; 613 else 614 sc->sc_cstate[ACPI_STATE_C3].cs_method = 0; 615 } 616 } 617 618 static int 619 acpicpu_cstate_latency(struct acpicpu_softc *sc) 620 { 621 static const uint32_t cs_factor = 3; 622 struct acpicpu_cstate *cs; 623 int i; 624 625 KASSERT(mutex_owned(&sc->sc_mtx) != 0); 626 627 for (i = cs_state_max; i > 0; i--) { 628 629 cs = &sc->sc_cstate[i]; 630 631 if (__predict_false(cs->cs_method == 0)) 632 continue; 633 634 /* 635 * Choose a state if we have previously slept 636 * longer than the worst case latency of the 637 * state times an arbitrary multiplier. 638 */ 639 if (sc->sc_cstate_sleep > cs->cs_latency * cs_factor) 640 return i; 641 } 642 643 return ACPI_STATE_C1; 644 } 645 646 /* 647 * The main idle loop. 648 */ 649 void 650 acpicpu_cstate_idle(void) 651 { 652 struct cpu_info *ci = curcpu(); 653 struct acpicpu_softc *sc; 654 int state; 655 656 KASSERT(acpicpu_sc != NULL); 657 KASSERT(ci->ci_acpiid < maxcpus); 658 659 sc = acpicpu_sc[ci->ci_acpiid]; 660 661 if (__predict_false(sc == NULL)) 662 return; 663 664 KASSERT(ci->ci_ilevel == IPL_NONE); 665 KASSERT((sc->sc_flags & ACPICPU_FLAG_C) != 0); 666 667 if (__predict_false(sc->sc_cold != false)) 668 return; 669 670 if (__predict_false(mutex_tryenter(&sc->sc_mtx) == 0)) 671 return; 672 673 state = acpicpu_cstate_latency(sc); 674 mutex_exit(&sc->sc_mtx); 675 676 /* 677 * Apply AMD C1E quirk. 678 */ 679 if ((sc->sc_flags & ACPICPU_FLAG_C_C1E) != 0) 680 acpicpu_md_quirk_c1e(); 681 682 /* 683 * Check for bus master activity. Note that particularly usb(4) 684 * causes high activity, which may prevent the use of C3 states. 685 */ 686 if ((sc->sc_cstate[state].cs_flags & ACPICPU_FLAG_C_BM_STS) != 0) { 687 688 if (acpicpu_cstate_bm_check() != false) 689 state--; 690 691 if (__predict_false(sc->sc_cstate[state].cs_method == 0)) 692 state = ACPI_STATE_C1; 693 } 694 695 KASSERT(state != ACPI_STATE_C0); 696 697 if (state != ACPI_STATE_C3) { 698 acpicpu_cstate_idle_enter(sc, state); 699 return; 700 } 701 702 /* 703 * On all recent (Intel) CPUs caches are shared 704 * by CPUs and bus master control is required to 705 * keep these coherent while in C3. Flushing the 706 * CPU caches is only the last resort. 707 */ 708 if ((sc->sc_flags & ACPICPU_FLAG_C_BM) == 0) 709 ACPI_FLUSH_CPU_CACHE(); 710 711 /* 712 * Allow the bus master to request that any given 713 * CPU should return immediately to C0 from C3. 714 */ 715 if ((sc->sc_flags & ACPICPU_FLAG_C_BM) != 0) 716 (void)AcpiWriteBitRegister(ACPI_BITREG_BUS_MASTER_RLD, 1); 717 718 /* 719 * It may be necessary to disable bus master arbitration 720 * to ensure that bus master cycles do not occur while 721 * sleeping in C3 (see ACPI 4.0, section 8.1.4). 722 */ 723 if ((sc->sc_flags & ACPICPU_FLAG_C_ARB) != 0) 724 (void)AcpiWriteBitRegister(ACPI_BITREG_ARB_DISABLE, 1); 725 726 acpicpu_cstate_idle_enter(sc, state); 727 728 /* 729 * Disable bus master wake and re-enable the arbiter. 730 */ 731 if ((sc->sc_flags & ACPICPU_FLAG_C_BM) != 0) 732 (void)AcpiWriteBitRegister(ACPI_BITREG_BUS_MASTER_RLD, 0); 733 734 if ((sc->sc_flags & ACPICPU_FLAG_C_ARB) != 0) 735 (void)AcpiWriteBitRegister(ACPI_BITREG_ARB_DISABLE, 0); 736 } 737 738 static void 739 acpicpu_cstate_idle_enter(struct acpicpu_softc *sc, int state) 740 { 741 struct acpicpu_cstate *cs = &sc->sc_cstate[state]; 742 uint32_t val; 743 744 #ifdef notyet 745 /* 746 * XXX This has a significant performance impact because the ACPI 747 * timer seems very slow and with many CPUs becomes a chokepoint. 748 * Better to use the TSC (if invariant) or APIC timer instead. 749 * Proably even getbintime(). Disabled for now as no functional 750 * change - only C1 sleep is enabled. 751 */ 752 start = acpitimer_read_fast(NULL); 753 #endif 754 755 switch (cs->cs_method) { 756 757 case ACPICPU_C_STATE_FFH: 758 case ACPICPU_C_STATE_HALT: 759 acpicpu_md_cstate_enter(cs->cs_method, state); 760 break; 761 762 case ACPICPU_C_STATE_SYSIO: 763 (void)AcpiOsReadPort(cs->cs_addr, &val, 8); 764 break; 765 } 766 767 cs->cs_evcnt.ev_count++; 768 769 #ifdef notyet 770 /* 771 * XXX As above. Also, hztoms() seems incorrect as the ACPI timer 772 * is running the MHz region. 773 */ 774 end = acpitimer_read_fast(NULL); 775 sc->sc_cstate_sleep = hztoms(acpitimer_delta(end, start)) * 1000; 776 #endif 777 } 778 779 static bool 780 acpicpu_cstate_bm_check(void) 781 { 782 uint32_t val = 0; 783 ACPI_STATUS rv; 784 785 rv = AcpiReadBitRegister(ACPI_BITREG_BUS_MASTER_STATUS, &val); 786 787 if (ACPI_FAILURE(rv) || val == 0) 788 return false; 789 790 (void)AcpiWriteBitRegister(ACPI_BITREG_BUS_MASTER_STATUS, 1); 791 792 return true; 793 } 794