xref: /netbsd-src/sys/arch/zaurus/dev/zssp.c (revision b1c86f5f087524e68db12794ee9c3e3da1ab17a0) 
1 /*	$NetBSD: zssp.c,v 1.9 2010/02/24 22:37:56 dyoung Exp $	*/
2 /*	$OpenBSD: zaurus_ssp.c,v 1.6 2005/04/08 21:58:49 uwe Exp $	*/
3 
4 /*
5  * Copyright (c) 2005 Uwe Stuehler <uwe@bsdx.de>
6  *
7  * Permission to use, copy, modify, and distribute this software for any
8  * purpose with or without fee is hereby granted, provided that the above
9  * copyright notice and this permission notice appear in all copies.
10  *
11  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18  */
19 
20 #include <sys/cdefs.h>
21 __KERNEL_RCSID(0, "$NetBSD: zssp.c,v 1.9 2010/02/24 22:37:56 dyoung Exp $");
22 
23 #include <sys/param.h>
24 #include <sys/systm.h>
25 #include <sys/device.h>
26 
27 #include <machine/bus.h>
28 
29 #include <arm/xscale/pxa2x0reg.h>
30 #include <arm/xscale/pxa2x0var.h>
31 #include <arm/xscale/pxa2x0_gpio.h>
32 
33 #include <zaurus/dev/zsspvar.h>
34 #include <zaurus/zaurus/zaurus_var.h>
35 
36 #define GPIO_ADS7846_CS_C3000	14	/* SSP SFRM */
37 #define GPIO_MAX1111_CS_C3000	20
38 #define GPIO_TG_CS_C3000	53
39 
40 #define SSCR0_ADS7846_C3000	0x06ab /* 12bit/Microwire/div by 7 */
41 #define SSCR0_MAX1111		0x0387
42 #define	SSCR0_LZ9JG18		0x01ab
43 
44 struct zssp_softc {
45 	device_t sc_dev;
46 	bus_space_tag_t sc_iot;
47 	bus_space_handle_t sc_ioh;
48 };
49 
50 static int	zssp_match(device_t, cfdata_t, void *);
51 static void	zssp_attach(device_t, device_t, void *);
52 
53 CFATTACH_DECL_NEW(zssp, sizeof(struct zssp_softc),
54 	zssp_match, zssp_attach, NULL, NULL);
55 
56 static void	zssp_init(void);
57 static bool	zssp_resume(device_t dv, const pmf_qual_t *);
58 
59 static struct zssp_softc *zssp_sc;
60 
61 static int
62 zssp_match(device_t parent, cfdata_t cf, void *aux)
63 {
64 
65 	if (zssp_sc != NULL)
66 		return 0;
67 
68 	return 1;
69 }
70 
71 static void
72 zssp_attach(device_t parent, device_t self, void *aux)
73 {
74 	struct zssp_softc *sc = device_private(self);
75 
76 	sc->sc_dev = self;
77 	zssp_sc = sc;
78 
79 	aprint_normal("\n");
80 	aprint_naive("\n");
81 
82 	sc->sc_iot = &pxa2x0_bs_tag;
83 	if (bus_space_map(sc->sc_iot, PXA2X0_SSP1_BASE, PXA2X0_SSP_SIZE,
84 	    0, &sc->sc_ioh)) {
85 		aprint_error_dev(sc->sc_dev, "can't map bus space\n");
86 		return;
87 	}
88 
89 	if (!pmf_device_register(sc->sc_dev, NULL, zssp_resume))
90 		aprint_error_dev(sc->sc_dev,
91 		    "couldn't establish power handler\n");
92 
93 	zssp_init();
94 }
95 
96 /*
97  * Initialize the dedicated SSP unit and disable all chip selects.
98  * This function is called with interrupts disabled.
99  */
100 static void
101 zssp_init(void)
102 {
103 	struct zssp_softc *sc;
104 
105 	KASSERT(zssp_sc != NULL);
106 	sc = zssp_sc;
107 
108 	pxa2x0_clkman_config(CKEN_SSP, 1);
109 
110 	bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSCR0, SSCR0_LZ9JG18);
111 	bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSCR1, 0);
112 
113 	pxa2x0_gpio_set_function(GPIO_ADS7846_CS_C3000, GPIO_OUT|GPIO_SET);
114 	pxa2x0_gpio_set_function(GPIO_MAX1111_CS_C3000, GPIO_OUT|GPIO_SET);
115 	pxa2x0_gpio_set_function(GPIO_TG_CS_C3000, GPIO_OUT|GPIO_SET);
116 }
117 
118 static bool
119 zssp_resume(device_t dv, const pmf_qual_t *qual)
120 {
121 	int s;
122 
123 	s = splhigh();
124 	zssp_init();
125 	splx(s);
126 
127 	return true;
128 }
129 
130 /*
131  * Transmit a single data word to one of the ICs, keep the chip selected
132  * afterwards, and don't wait for data to be returned in SSDR.  Interrupts
133  * must be held off until zssp_ic_stop() gets called.
134  */
135 void
136 zssp_ic_start(int ic, uint32_t data)
137 {
138 	struct zssp_softc *sc;
139 
140 	KASSERT(zssp_sc != NULL);
141 	sc = zssp_sc;
142 
143 	/* disable other ICs */
144 	bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSCR0, 0);
145 	if (ic != ZSSP_IC_ADS7846)
146 		pxa2x0_gpio_set_bit(GPIO_ADS7846_CS_C3000);
147 	if (ic != ZSSP_IC_LZ9JG18)
148 		pxa2x0_gpio_set_bit(GPIO_TG_CS_C3000);
149 	if (ic != ZSSP_IC_MAX1111)
150 		pxa2x0_gpio_set_bit(GPIO_MAX1111_CS_C3000);
151 
152 	/* activate the chosen one */
153 	switch (ic) {
154 	case ZSSP_IC_ADS7846:
155 		bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSCR0,
156 		    SSCR0_ADS7846_C3000);
157 		pxa2x0_gpio_clear_bit(GPIO_ADS7846_CS_C3000);
158 		bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSDR, data);
159 		while ((bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSSR)
160 		    & SSSR_TNF) != SSSR_TNF)
161 			continue;	/* poll */
162 		break;
163 	case ZSSP_IC_LZ9JG18:
164 		pxa2x0_gpio_clear_bit(GPIO_TG_CS_C3000);
165 		break;
166 	case ZSSP_IC_MAX1111:
167 		pxa2x0_gpio_clear_bit(GPIO_MAX1111_CS_C3000);
168 		break;
169 	}
170 }
171 
172 /*
173  * Read the last value from SSDR and deactivate all chip-selects.
174  */
175 uint32_t
176 zssp_ic_stop(int ic)
177 {
178 	struct zssp_softc *sc;
179 	uint32_t rv;
180 
181 	KASSERT(zssp_sc != NULL);
182 	sc = zssp_sc;
183 
184 	switch (ic) {
185 	case ZSSP_IC_ADS7846:
186 		/* read result of last command */
187 		while ((bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSSR)
188 		    & SSSR_RNE) != SSSR_RNE)
189 			continue;	/* poll */
190 		rv = bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSDR);
191 		break;
192 	case ZSSP_IC_LZ9JG18:
193 	case ZSSP_IC_MAX1111:
194 		/* last value received is irrelevant or undefined */
195 	default:
196 		rv = 0;
197 		break;
198 	}
199 
200 	pxa2x0_gpio_set_bit(GPIO_ADS7846_CS_C3000);
201 	pxa2x0_gpio_set_bit(GPIO_TG_CS_C3000);
202 	pxa2x0_gpio_set_bit(GPIO_MAX1111_CS_C3000);
203 
204 	return rv;
205 }
206 
207 /*
208  * Activate one of the chip-select lines, transmit one word value in
209  * each direction, and deactivate the chip-select again.
210  */
211 uint32_t
212 zssp_ic_send(int ic, uint32_t data)
213 {
214 
215 	switch (ic) {
216 	case ZSSP_IC_MAX1111:
217 		return (zssp_read_max1111(data));
218 	case ZSSP_IC_ADS7846:
219 		return (zssp_read_ads7846(data));
220 	case ZSSP_IC_LZ9JG18:
221 		zssp_write_lz9jg18(data);
222 		return 0;
223 	default:
224 		aprint_error("zssp: zssp_ic_send: invalid IC %d\n", ic);
225 		return 0;
226 	}
227 }
228 
229 int
230 zssp_read_max1111(uint32_t cmd)
231 {
232 	struct zssp_softc *sc;
233 	int data[3];
234 	int voltage[3];	/* voltage[0]: dummy */
235 	int i;
236 	int s;
237 
238 	KASSERT(zssp_sc != NULL);
239 	sc = zssp_sc;
240 
241 	s = splhigh();
242 
243 	bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSCR0, 0);
244 	bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSCR0, SSCR0_MAX1111);
245 
246 	pxa2x0_gpio_set_bit(GPIO_TG_CS_C3000);
247 	pxa2x0_gpio_set_bit(GPIO_ADS7846_CS_C3000);
248 	pxa2x0_gpio_clear_bit(GPIO_MAX1111_CS_C3000);
249 
250 	delay(1);
251 
252 	memset(data, 0, sizeof(data));
253 	data[0] = cmd;
254 	for (i = 0; i < __arraycount(data); i++) {
255 		bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSDR, data[i]);
256 		while ((bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSSR)
257 		    & SSSR_TNF) != SSSR_TNF)
258 			continue;	/* poll */
259 		/* XXX is this delay necessary? */
260 		delay(1);
261 		while ((bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSSR)
262 		    & SSSR_RNE) != SSSR_RNE)
263 			continue;	/* poll */
264 		voltage[i] = bus_space_read_4(sc->sc_iot, sc->sc_ioh,
265 		    SSP_SSDR);
266 	}
267 
268 	pxa2x0_gpio_set_bit(GPIO_TG_CS_C3000);
269 	pxa2x0_gpio_set_bit(GPIO_ADS7846_CS_C3000);
270 	pxa2x0_gpio_set_bit(GPIO_MAX1111_CS_C3000);
271 
272 	bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSCR0, 0);
273 
274 	splx(s);
275 
276 	/* XXX no idea what this means, but it's what Linux would do. */
277 	if ((voltage[1] & 0xc0) != 0 || (voltage[2] & 0x3f) != 0)
278 		return -1;
279 	return ((voltage[1] << 2) & 0xfc) | ((voltage[2] >> 6) & 0x03);
280 }
281 
282 /* XXX - only does CS_ADS7846 */
283 uint32_t
284 zssp_read_ads7846(uint32_t cmd)
285 {
286 	struct zssp_softc *sc;
287 	unsigned int cr0;
288 	uint32_t val;
289 	int s;
290 
291 	if (zssp_sc == NULL) {
292 		printf("zssp_read_ads7846: not configured\n");
293 		return 0;
294 	}
295 	sc = zssp_sc;
296 
297 	s = splhigh();
298 
299 	if (ZAURUS_ISC3000) {
300 		cr0 = SSCR0_ADS7846_C3000;
301 	} else {
302 		cr0 = 0x00ab;
303 	}
304         bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSCR0, 0);
305 	bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSCR0, cr0);
306 
307 	pxa2x0_gpio_set_bit(GPIO_TG_CS_C3000);
308 	pxa2x0_gpio_set_bit(GPIO_MAX1111_CS_C3000);
309 	pxa2x0_gpio_clear_bit(GPIO_ADS7846_CS_C3000);
310 
311 	bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSDR, cmd);
312 
313 	while ((bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSSR)
314 	    & SSSR_TNF) != SSSR_TNF)
315 		continue;	/* poll */
316 
317 	delay(1);
318 
319 	while ((bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSSR)
320 	    & SSSR_RNE) != SSSR_RNE)
321 		continue;	/* poll */
322 
323 	val = bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSDR);
324 
325 	pxa2x0_gpio_set_bit(GPIO_ADS7846_CS_C3000);
326 
327 	splx(s);
328 
329 	return val;
330 }
331 
332 void
333 zssp_write_lz9jg18(uint32_t data)
334 {
335 	int sclk_pin, sclk_fn;
336 	int sfrm_pin, sfrm_fn;
337 	int txd_pin, txd_fn;
338 	int rxd_pin, rxd_fn;
339 	int i;
340 	int s;
341 
342 	/* XXX this creates a DAC command from a backlight duty value. */
343 	data = 0x40 | (data & 0x1f);
344 
345 	if (ZAURUS_ISC3000) {
346 		sclk_pin = 19;
347 		sfrm_pin = 14;
348 		txd_pin = 87;
349 		rxd_pin = 86;
350 	} else {
351 		sclk_pin = 23;
352 		sfrm_pin = 24;
353 		txd_pin = 25;
354 		rxd_pin = 26;
355 	}
356 
357 	s = splhigh();
358 
359 	sclk_fn = pxa2x0_gpio_get_function(sclk_pin);
360 	sfrm_fn = pxa2x0_gpio_get_function(sfrm_pin);
361 	txd_fn = pxa2x0_gpio_get_function(txd_pin);
362 	rxd_fn = pxa2x0_gpio_get_function(rxd_pin);
363 
364 	pxa2x0_gpio_set_function(sfrm_pin, GPIO_OUT | GPIO_SET);
365 	pxa2x0_gpio_set_function(sclk_pin, GPIO_OUT | GPIO_CLR);
366 	pxa2x0_gpio_set_function(txd_pin, GPIO_OUT | GPIO_CLR);
367 	pxa2x0_gpio_set_function(rxd_pin, GPIO_IN);
368 
369 	pxa2x0_gpio_set_bit(GPIO_MAX1111_CS_C3000);
370 	pxa2x0_gpio_set_bit(GPIO_ADS7846_CS_C3000);
371 	pxa2x0_gpio_clear_bit(GPIO_TG_CS_C3000);
372 
373 	delay(10);
374 
375 	for (i = 0; i < 8; i++) {
376 		if (data & 0x80)
377 			pxa2x0_gpio_set_bit(txd_pin);
378 		else
379 			pxa2x0_gpio_clear_bit(txd_pin);
380 		delay(10);
381 		pxa2x0_gpio_set_bit(sclk_pin);
382 		delay(10);
383 		pxa2x0_gpio_clear_bit(sclk_pin);
384 		delay(10);
385 		data <<= 1;
386 	}
387 
388 	pxa2x0_gpio_clear_bit(txd_pin);
389 	pxa2x0_gpio_set_bit(GPIO_TG_CS_C3000);
390 
391 	pxa2x0_gpio_set_function(sclk_pin, sclk_fn);
392 	pxa2x0_gpio_set_function(sfrm_pin, sfrm_fn);
393 	pxa2x0_gpio_set_function(txd_pin, txd_fn);
394 	pxa2x0_gpio_set_function(rxd_pin, rxd_fn);
395 
396 	splx(s);
397 }
398