xref: /netbsd-src/sys/arch/zaurus/dev/zssp.c (revision a5847cc334d9a7029f6352b847e9e8d71a0f9e0c) 
1 /*	$NetBSD: zssp.c,v 1.11 2011/07/19 15:11:49 dyoung Exp $	*/
2 /*	$OpenBSD: zaurus_ssp.c,v 1.6 2005/04/08 21:58:49 uwe Exp $	*/
3 
4 /*
5  * Copyright (c) 2005 Uwe Stuehler <uwe@bsdx.de>
6  *
7  * Permission to use, copy, modify, and distribute this software for any
8  * purpose with or without fee is hereby granted, provided that the above
9  * copyright notice and this permission notice appear in all copies.
10  *
11  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18  */
19 
20 #include <sys/cdefs.h>
21 __KERNEL_RCSID(0, "$NetBSD: zssp.c,v 1.11 2011/07/19 15:11:49 dyoung Exp $");
22 
23 #include <sys/param.h>
24 #include <sys/systm.h>
25 #include <sys/device.h>
26 #include <sys/bus.h>
27 
28 #include <arm/xscale/pxa2x0reg.h>
29 #include <arm/xscale/pxa2x0var.h>
30 #include <arm/xscale/pxa2x0_gpio.h>
31 
32 #include <zaurus/dev/zsspvar.h>
33 #include <zaurus/zaurus/zaurus_var.h>
34 
35 #define GPIO_ADS7846_CS_C3000	14	/* SSP SFRM */
36 #define GPIO_MAX1111_CS_C3000	20
37 #define GPIO_TG_CS_C3000	53
38 
39 #define SSCR0_ADS7846_C3000	0x06ab /* 12bit/Microwire/div by 7 */
40 #define SSCR0_MAX1111		0x0387
41 #define	SSCR0_LZ9JG18		0x01ab
42 
43 struct zssp_softc {
44 	device_t sc_dev;
45 	bus_space_tag_t sc_iot;
46 	bus_space_handle_t sc_ioh;
47 };
48 
49 static int	zssp_match(device_t, cfdata_t, void *);
50 static void	zssp_attach(device_t, device_t, void *);
51 
52 CFATTACH_DECL_NEW(zssp, sizeof(struct zssp_softc),
53 	zssp_match, zssp_attach, NULL, NULL);
54 
55 static void	zssp_init(void);
56 static bool	zssp_resume(device_t dv, const pmf_qual_t *);
57 
58 static struct zssp_softc *zssp_sc;
59 
60 static int
61 zssp_match(device_t parent, cfdata_t cf, void *aux)
62 {
63 
64 	if (zssp_sc != NULL)
65 		return 0;
66 	return 1;
67 }
68 
69 static void
70 zssp_attach(device_t parent, device_t self, void *aux)
71 {
72 	struct zssp_softc *sc = device_private(self);
73 
74 	sc->sc_dev = self;
75 	zssp_sc = sc;
76 
77 	aprint_normal("\n");
78 	aprint_naive("\n");
79 
80 	sc->sc_iot = &pxa2x0_bs_tag;
81 	if (bus_space_map(sc->sc_iot, PXA2X0_SSP1_BASE, PXA2X0_SSP_SIZE,
82 	    0, &sc->sc_ioh)) {
83 		aprint_error_dev(sc->sc_dev, "can't map bus space\n");
84 		return;
85 	}
86 
87 	if (!pmf_device_register(sc->sc_dev, NULL, zssp_resume))
88 		aprint_error_dev(sc->sc_dev,
89 		    "couldn't establish power handler\n");
90 
91 	zssp_init();
92 }
93 
94 /*
95  * Initialize the dedicated SSP unit and disable all chip selects.
96  * This function is called with interrupts disabled.
97  */
98 static void
99 zssp_init(void)
100 {
101 	struct zssp_softc *sc;
102 
103 	KASSERT(zssp_sc != NULL);
104 	sc = zssp_sc;
105 
106 	pxa2x0_clkman_config(CKEN_SSP, 1);
107 
108 	bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSCR0, SSCR0_LZ9JG18);
109 	bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSCR1, 0);
110 
111 	pxa2x0_gpio_set_function(GPIO_ADS7846_CS_C3000, GPIO_OUT|GPIO_SET);
112 	pxa2x0_gpio_set_function(GPIO_MAX1111_CS_C3000, GPIO_OUT|GPIO_SET);
113 	pxa2x0_gpio_set_function(GPIO_TG_CS_C3000, GPIO_OUT|GPIO_SET);
114 }
115 
116 static bool
117 zssp_resume(device_t dv, const pmf_qual_t *qual)
118 {
119 	int s;
120 
121 	s = splhigh();
122 	zssp_init();
123 	splx(s);
124 
125 	return true;
126 }
127 
128 /*
129  * Transmit a single data word to one of the ICs, keep the chip selected
130  * afterwards, and don't wait for data to be returned in SSDR.  Interrupts
131  * must be held off until zssp_ic_stop() gets called.
132  */
133 void
134 zssp_ic_start(int ic, uint32_t data)
135 {
136 	struct zssp_softc *sc;
137 
138 	KASSERT(zssp_sc != NULL);
139 	sc = zssp_sc;
140 
141 	/* disable other ICs */
142 	bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSCR0, 0);
143 	if (ic != ZSSP_IC_ADS7846)
144 		pxa2x0_gpio_set_bit(GPIO_ADS7846_CS_C3000);
145 	if (ic != ZSSP_IC_LZ9JG18)
146 		pxa2x0_gpio_set_bit(GPIO_TG_CS_C3000);
147 	if (ic != ZSSP_IC_MAX1111)
148 		pxa2x0_gpio_set_bit(GPIO_MAX1111_CS_C3000);
149 
150 	/* activate the chosen one */
151 	switch (ic) {
152 	case ZSSP_IC_ADS7846:
153 		bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSCR0,
154 		    SSCR0_ADS7846_C3000);
155 		pxa2x0_gpio_clear_bit(GPIO_ADS7846_CS_C3000);
156 		bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSDR, data);
157 		while ((bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSSR)
158 		    & SSSR_TNF) != SSSR_TNF)
159 			continue;	/* poll */
160 		break;
161 	case ZSSP_IC_LZ9JG18:
162 		pxa2x0_gpio_clear_bit(GPIO_TG_CS_C3000);
163 		break;
164 	case ZSSP_IC_MAX1111:
165 		pxa2x0_gpio_clear_bit(GPIO_MAX1111_CS_C3000);
166 		break;
167 	}
168 }
169 
170 /*
171  * Read the last value from SSDR and deactivate all chip-selects.
172  */
173 uint32_t
174 zssp_ic_stop(int ic)
175 {
176 	struct zssp_softc *sc;
177 	uint32_t rv;
178 
179 	KASSERT(zssp_sc != NULL);
180 	sc = zssp_sc;
181 
182 	switch (ic) {
183 	case ZSSP_IC_ADS7846:
184 		/* read result of last command */
185 		while ((bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSSR)
186 		    & SSSR_RNE) != SSSR_RNE)
187 			continue;	/* poll */
188 		rv = bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSDR);
189 		break;
190 	case ZSSP_IC_LZ9JG18:
191 	case ZSSP_IC_MAX1111:
192 		/* last value received is irrelevant or undefined */
193 	default:
194 		rv = 0;
195 		break;
196 	}
197 
198 	pxa2x0_gpio_set_bit(GPIO_ADS7846_CS_C3000);
199 	pxa2x0_gpio_set_bit(GPIO_TG_CS_C3000);
200 	pxa2x0_gpio_set_bit(GPIO_MAX1111_CS_C3000);
201 
202 	return rv;
203 }
204 
205 /*
206  * Activate one of the chip-select lines, transmit one word value in
207  * each direction, and deactivate the chip-select again.
208  */
209 uint32_t
210 zssp_ic_send(int ic, uint32_t data)
211 {
212 
213 	switch (ic) {
214 	case ZSSP_IC_MAX1111:
215 		return (zssp_read_max1111(data));
216 	case ZSSP_IC_ADS7846:
217 		return (zssp_read_ads7846(data));
218 	case ZSSP_IC_LZ9JG18:
219 		zssp_write_lz9jg18(data);
220 		return 0;
221 	default:
222 		aprint_error("zssp: zssp_ic_send: invalid IC %d\n", ic);
223 		return 0;
224 	}
225 }
226 
227 int
228 zssp_read_max1111(uint32_t cmd)
229 {
230 	struct zssp_softc *sc;
231 	int data[3];
232 	int voltage[3];	/* voltage[0]: dummy */
233 	int i;
234 	int s;
235 
236 	KASSERT(zssp_sc != NULL);
237 	sc = zssp_sc;
238 
239 	s = splhigh();
240 
241 	bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSCR0, 0);
242 	bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSCR0, SSCR0_MAX1111);
243 
244 	pxa2x0_gpio_set_bit(GPIO_TG_CS_C3000);
245 	pxa2x0_gpio_set_bit(GPIO_ADS7846_CS_C3000);
246 	pxa2x0_gpio_clear_bit(GPIO_MAX1111_CS_C3000);
247 
248 	delay(1);
249 
250 	memset(data, 0, sizeof(data));
251 	data[0] = cmd;
252 	for (i = 0; i < __arraycount(data); i++) {
253 		bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSDR, data[i]);
254 		while ((bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSSR)
255 		    & SSSR_TNF) != SSSR_TNF)
256 			continue;	/* poll */
257 		/* XXX is this delay necessary? */
258 		delay(1);
259 		while ((bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSSR)
260 		    & SSSR_RNE) != SSSR_RNE)
261 			continue;	/* poll */
262 		voltage[i] = bus_space_read_4(sc->sc_iot, sc->sc_ioh,
263 		    SSP_SSDR);
264 	}
265 
266 	pxa2x0_gpio_set_bit(GPIO_TG_CS_C3000);
267 	pxa2x0_gpio_set_bit(GPIO_ADS7846_CS_C3000);
268 	pxa2x0_gpio_set_bit(GPIO_MAX1111_CS_C3000);
269 
270 	bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSCR0, 0);
271 
272 	splx(s);
273 
274 	/* XXX no idea what this means, but it's what Linux would do. */
275 	if ((voltage[1] & 0xc0) != 0 || (voltage[2] & 0x3f) != 0)
276 		return -1;
277 	return ((voltage[1] << 2) & 0xfc) | ((voltage[2] >> 6) & 0x03);
278 }
279 
280 /* XXX - only does CS_ADS7846 */
281 uint32_t
282 zssp_read_ads7846(uint32_t cmd)
283 {
284 	struct zssp_softc *sc;
285 	unsigned int cr0;
286 	uint32_t val;
287 	int s;
288 
289 	if (zssp_sc == NULL) {
290 		printf("zssp_read_ads7846: not configured\n");
291 		return 0;
292 	}
293 	sc = zssp_sc;
294 
295 	s = splhigh();
296 
297 	if (ZAURUS_ISC1000 || ZAURUS_ISC3000) {
298 		cr0 = SSCR0_ADS7846_C3000;
299 	} else {
300 		cr0 = 0x00ab;
301 	}
302         bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSCR0, 0);
303 	bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSCR0, cr0);
304 
305 	pxa2x0_gpio_set_bit(GPIO_TG_CS_C3000);
306 	pxa2x0_gpio_set_bit(GPIO_MAX1111_CS_C3000);
307 	pxa2x0_gpio_clear_bit(GPIO_ADS7846_CS_C3000);
308 
309 	bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSDR, cmd);
310 
311 	while ((bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSSR)
312 	    & SSSR_TNF) != SSSR_TNF)
313 		continue;	/* poll */
314 
315 	delay(1);
316 
317 	while ((bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSSR)
318 	    & SSSR_RNE) != SSSR_RNE)
319 		continue;	/* poll */
320 
321 	val = bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSDR);
322 
323 	pxa2x0_gpio_set_bit(GPIO_ADS7846_CS_C3000);
324 
325 	splx(s);
326 
327 	return val;
328 }
329 
330 void
331 zssp_write_lz9jg18(uint32_t data)
332 {
333 	int sclk_pin, sclk_fn;
334 	int sfrm_pin, sfrm_fn;
335 	int txd_pin, txd_fn;
336 	int rxd_pin, rxd_fn;
337 	int i;
338 	int s;
339 
340 	/* XXX this creates a DAC command from a backlight duty value. */
341 	data = 0x40 | (data & 0x1f);
342 
343 	if (ZAURUS_ISC1000 || ZAURUS_ISC3000) {
344 		sclk_pin = 19;
345 		sfrm_pin = 14;
346 		txd_pin = 87;
347 		rxd_pin = 86;
348 	} else {
349 		sclk_pin = 23;
350 		sfrm_pin = 24;
351 		txd_pin = 25;
352 		rxd_pin = 26;
353 	}
354 
355 	s = splhigh();
356 
357 	sclk_fn = pxa2x0_gpio_get_function(sclk_pin);
358 	sfrm_fn = pxa2x0_gpio_get_function(sfrm_pin);
359 	txd_fn = pxa2x0_gpio_get_function(txd_pin);
360 	rxd_fn = pxa2x0_gpio_get_function(rxd_pin);
361 
362 	pxa2x0_gpio_set_function(sfrm_pin, GPIO_OUT | GPIO_SET);
363 	pxa2x0_gpio_set_function(sclk_pin, GPIO_OUT | GPIO_CLR);
364 	pxa2x0_gpio_set_function(txd_pin, GPIO_OUT | GPIO_CLR);
365 	pxa2x0_gpio_set_function(rxd_pin, GPIO_IN);
366 
367 	pxa2x0_gpio_set_bit(GPIO_MAX1111_CS_C3000);
368 	pxa2x0_gpio_set_bit(GPIO_ADS7846_CS_C3000);
369 	pxa2x0_gpio_clear_bit(GPIO_TG_CS_C3000);
370 
371 	delay(10);
372 
373 	for (i = 0; i < 8; i++) {
374 		if (data & 0x80)
375 			pxa2x0_gpio_set_bit(txd_pin);
376 		else
377 			pxa2x0_gpio_clear_bit(txd_pin);
378 		delay(10);
379 		pxa2x0_gpio_set_bit(sclk_pin);
380 		delay(10);
381 		pxa2x0_gpio_clear_bit(sclk_pin);
382 		delay(10);
383 		data <<= 1;
384 	}
385 
386 	pxa2x0_gpio_clear_bit(txd_pin);
387 	pxa2x0_gpio_set_bit(GPIO_TG_CS_C3000);
388 
389 	pxa2x0_gpio_set_function(sclk_pin, sclk_fn);
390 	pxa2x0_gpio_set_function(sfrm_pin, sfrm_fn);
391 	pxa2x0_gpio_set_function(txd_pin, txd_fn);
392 	pxa2x0_gpio_set_function(rxd_pin, rxd_fn);
393 
394 	splx(s);
395 }
396