xref: /netbsd-src/sys/arch/zaurus/dev/zssp.c (revision 82d56013d7b633d116a93943de88e08335357a7c) 
1 /*	$NetBSD: zssp.c,v 1.14 2021/04/24 23:36:52 thorpej Exp $	*/
2 /*	$OpenBSD: zaurus_ssp.c,v 1.6 2005/04/08 21:58:49 uwe Exp $	*/
3 
4 /*
5  * Copyright (c) 2005 Uwe Stuehler <uwe@bsdx.de>
6  *
7  * Permission to use, copy, modify, and distribute this software for any
8  * purpose with or without fee is hereby granted, provided that the above
9  * copyright notice and this permission notice appear in all copies.
10  *
11  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18  */
19 
20 #include <sys/cdefs.h>
21 __KERNEL_RCSID(0, "$NetBSD: zssp.c,v 1.14 2021/04/24 23:36:52 thorpej Exp $");
22 
23 #include <sys/param.h>
24 #include <sys/systm.h>
25 #include <sys/device.h>
26 #include <sys/bus.h>
27 
28 #include <arm/xscale/pxa2x0reg.h>
29 #include <arm/xscale/pxa2x0var.h>
30 #include <arm/xscale/pxa2x0_gpio.h>
31 
32 #include <zaurus/dev/zsspvar.h>
33 #include <zaurus/zaurus/zaurus_var.h>
34 
35 #define GPIO_ADS7846_CS_C3000	14	/* SSP SFRM */
36 #define GPIO_MAX1111_CS_C3000	20
37 #define GPIO_TG_CS_C3000	53
38 #define GPIO_ADS7846_CS_C860	24	/* SSP SFRM */
39 #define GPIO_MAX1111_CS_C860	20
40 #define GPIO_TG_CS_C860		19
41 
42 #define SSCR0_ADS7846_C3000	0x06ab /* 12bit/Microwire/div by 7 */
43 #define SSCR0_MAX1111		0x0387
44 #define	SSCR0_LZ9JG18		0x01ab
45 #define SSCR0_ADS7846_C860	0x00ab /* 12bit/Microwire/div by 7 */
46 
47 struct zssp_ads7846 {
48 	u_int gpio;
49 	uint32_t sscr0;
50 };
51 struct zssp_max1111 {
52 	u_int gpio;
53 	uint32_t sscr0;
54 };
55 struct zssp_lz9jg18 {
56 	u_int gpio;
57 	uint32_t sscr0;
58 	int sclk_pin;
59 	int sfrm_pin;
60 	int txd_pin;
61 	int rxd_pin;
62 };
63 
64 struct zssp_softc {
65 	device_t sc_dev;
66 	bus_space_tag_t sc_iot;
67 	bus_space_handle_t sc_ioh;
68 	bus_addr_t sc_ssp;
69 	struct zssp_ads7846 ads7846;
70 	struct zssp_max1111 max1111;
71 	struct zssp_lz9jg18 lz9jg18;
72 };
73 
74 static int	zssp_match(device_t, cfdata_t, void *);
75 static void	zssp_attach(device_t, device_t, void *);
76 static int	zssp_search(device_t, cfdata_t, const int *, void *);
77 static int	zssp_print(void *, const char *);
78 
79 CFATTACH_DECL_NEW(zssp, sizeof(struct zssp_softc),
80 	zssp_match, zssp_attach, NULL, NULL);
81 
82 static void	zssp_init(void);
83 static bool	zssp_resume(device_t dv, const pmf_qual_t *);
84 
85 static struct zssp_softc *zssp_sc;
86 
87 static int
88 zssp_match(device_t parent, cfdata_t cf, void *aux)
89 {
90 
91 	if (zssp_sc != NULL)
92 		return 0;
93 	return 1;
94 }
95 
96 static void
97 zssp_attach(device_t parent, device_t self, void *aux)
98 {
99 	struct zssp_softc *sc = device_private(self);
100 
101 	sc->sc_dev = self;
102 	zssp_sc = sc;
103 
104 	aprint_normal("\n");
105 	aprint_naive("\n");
106 
107 	sc->sc_iot = &pxa2x0_bs_tag;
108 	if (ZAURUS_ISC1000 || ZAURUS_ISC3000) {
109 		sc->sc_ssp = PXA2X0_SSP1_BASE;
110 		sc->ads7846.gpio     = GPIO_ADS7846_CS_C3000;
111 		sc->ads7846.sscr0    = SSCR0_ADS7846_C3000;
112 		sc->max1111.gpio     = GPIO_MAX1111_CS_C3000;
113 		sc->max1111.sscr0    = SSCR0_MAX1111;
114 		sc->lz9jg18.gpio     = GPIO_TG_CS_C3000;
115 		sc->lz9jg18.sscr0    = SSCR0_LZ9JG18;
116 		sc->lz9jg18.sclk_pin = 19;
117 		sc->lz9jg18.sfrm_pin = 14;
118 		sc->lz9jg18.txd_pin  = 87;
119 		sc->lz9jg18.rxd_pin  = 86;
120 	} else {
121 		sc->sc_ssp = PXA2X0_SSP_BASE;
122 		sc->ads7846.gpio     = GPIO_ADS7846_CS_C860;
123 		sc->ads7846.sscr0    = SSCR0_ADS7846_C860;
124 		sc->max1111.gpio     = GPIO_MAX1111_CS_C860;
125 		sc->max1111.sscr0    = SSCR0_MAX1111;
126 		sc->lz9jg18.gpio     = GPIO_TG_CS_C860;
127 		sc->lz9jg18.sscr0    = SSCR0_LZ9JG18;
128 		sc->lz9jg18.sclk_pin = 23;
129 		sc->lz9jg18.sfrm_pin = 24;
130 		sc->lz9jg18.txd_pin  = 25;
131 		sc->lz9jg18.rxd_pin  = 26;
132 	}
133 
134 	if (bus_space_map(sc->sc_iot, sc->sc_ssp, PXA2X0_SSP_SIZE,
135 	    0, &sc->sc_ioh)) {
136 		aprint_error_dev(sc->sc_dev, "can't map bus space\n");
137 		return;
138 	}
139 
140 	if (!pmf_device_register(sc->sc_dev, NULL, zssp_resume))
141 		aprint_error_dev(sc->sc_dev,
142 		    "couldn't establish power handler\n");
143 
144 	zssp_init();
145 
146 	/* Attach all devices */
147 	config_search(self, NULL,
148 	    CFARG_SEARCH, zssp_search,
149 	    CFARG_EOL);
150 }
151 
152 static int
153 zssp_search(device_t parent, cfdata_t cf, const int *ldesc, void *aux)
154 {
155 	struct zssp_attach_args aa;
156 
157 	aa.zaa_name = cf->cf_name;
158 
159 	if (config_probe(parent, cf, &aa))
160 		config_attach(parent, cf, &aa, zssp_print, CFARG_EOL);
161 
162 	return 0;
163 }
164 
165 static int
166 zssp_print(void *aux, const char *name)
167 {
168 
169 	return UNCONF;
170 }
171 
172 /*
173  * Initialize the dedicated SSP unit and disable all chip selects.
174  * This function is called with interrupts disabled.
175  */
176 static void
177 zssp_init(void)
178 {
179 	struct zssp_softc *sc;
180 
181 	if (__predict_false(zssp_sc == NULL)) {
182 		aprint_error("%s: not configured.\n", __func__);
183 		return;
184 	}
185 	sc = zssp_sc;
186 
187 	pxa2x0_clkman_config(CKEN_SSP, 1);
188 
189 	bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSCR0, sc->lz9jg18.sscr0);
190 	bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSCR1, 0);
191 
192 	pxa2x0_gpio_set_function(sc->ads7846.gpio, GPIO_OUT|GPIO_SET);
193 	pxa2x0_gpio_set_function(sc->max1111.gpio, GPIO_OUT|GPIO_SET);
194 	pxa2x0_gpio_set_function(sc->lz9jg18.gpio, GPIO_OUT|GPIO_SET);
195 }
196 
197 static bool
198 zssp_resume(device_t dv, const pmf_qual_t *qual)
199 {
200 	int s;
201 
202 	s = splhigh();
203 	zssp_init();
204 	splx(s);
205 
206 	return true;
207 }
208 
209 /*
210  * Transmit a single data word to one of the ICs, keep the chip selected
211  * afterwards, and don't wait for data to be returned in SSDR.  Interrupts
212  * must be held off until zssp_ic_stop() gets called.
213  */
214 void
215 zssp_ic_start(int ic, uint32_t data)
216 {
217 	struct zssp_softc *sc;
218 
219 	if (__predict_false(zssp_sc == NULL)) {
220 		aprint_error("%s: not configured.\n", __func__);
221 		return;
222 	}
223 	sc = zssp_sc;
224 
225 	/* disable other ICs */
226 	bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSCR0, 0);
227 	if (ic != ZSSP_IC_ADS7846)
228 		pxa2x0_gpio_set_bit(sc->ads7846.gpio);
229 	if (ic != ZSSP_IC_LZ9JG18)
230 		pxa2x0_gpio_set_bit(sc->lz9jg18.gpio);
231 	if (ic != ZSSP_IC_MAX1111)
232 		pxa2x0_gpio_set_bit(sc->max1111.gpio);
233 
234 	/* activate the chosen one */
235 	switch (ic) {
236 	case ZSSP_IC_ADS7846:
237 		bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSCR0,
238 		    sc->ads7846.sscr0);
239 		pxa2x0_gpio_clear_bit(sc->ads7846.gpio);
240 		delay(1);	/* ADS7846 Tcss = 100ns */
241 		bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSDR, data);
242 		while ((bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSSR)
243 		    & SSSR_TNF) != SSSR_TNF)
244 			continue;	/* poll */
245 		break;
246 	case ZSSP_IC_LZ9JG18:
247 		pxa2x0_gpio_clear_bit(sc->lz9jg18.gpio);
248 		break;
249 	case ZSSP_IC_MAX1111:
250 		pxa2x0_gpio_clear_bit(sc->max1111.gpio);
251 		break;
252 	}
253 }
254 
255 /*
256  * Read the last value from SSDR and deactivate all chip-selects.
257  */
258 uint32_t
259 zssp_ic_stop(int ic)
260 {
261 	struct zssp_softc *sc;
262 	uint32_t rv;
263 
264 	if (__predict_false(zssp_sc == NULL)) {
265 		aprint_error("%s: not configured.\n", __func__);
266 		return 0;
267 	}
268 	sc = zssp_sc;
269 
270 	switch (ic) {
271 	case ZSSP_IC_ADS7846:
272 		/* read result of last command */
273 		while ((bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSSR)
274 		    & SSSR_RNE) != SSSR_RNE)
275 			continue;	/* poll */
276 		rv = bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSDR);
277 		break;
278 	case ZSSP_IC_LZ9JG18:
279 	case ZSSP_IC_MAX1111:
280 		/* last value received is irrelevant or undefined */
281 	default:
282 		rv = 0;
283 		break;
284 	}
285 
286 	pxa2x0_gpio_set_bit(sc->ads7846.gpio);
287 	pxa2x0_gpio_set_bit(sc->lz9jg18.gpio);
288 	pxa2x0_gpio_set_bit(sc->max1111.gpio);
289 
290 	return rv;
291 }
292 
293 /*
294  * Activate one of the chip-select lines, transmit one word value in
295  * each direction, and deactivate the chip-select again.
296  */
297 uint32_t
298 zssp_ic_send(int ic, uint32_t data)
299 {
300 
301 	switch (ic) {
302 	case ZSSP_IC_MAX1111:
303 		return (zssp_read_max1111(data));
304 	case ZSSP_IC_ADS7846:
305 		return (zssp_read_ads7846(data));
306 	case ZSSP_IC_LZ9JG18:
307 		zssp_write_lz9jg18(data);
308 		return 0;
309 	default:
310 		aprint_error("zssp: zssp_ic_send: invalid IC %d\n", ic);
311 		return 0;
312 	}
313 }
314 
315 int
316 zssp_read_max1111(uint32_t cmd)
317 {
318 	struct zssp_softc *sc;
319 	int data[3];
320 	int voltage[3];	/* voltage[0]: dummy */
321 	int i;
322 	int s;
323 
324 	if (__predict_false(zssp_sc == NULL)) {
325 		aprint_error("%s: not configured.\n", __func__);
326 		return 0;
327 	}
328 	sc = zssp_sc;
329 
330 	s = splhigh();
331 
332 	bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSCR0, 0);
333 	bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSCR0, sc->max1111.sscr0);
334 
335 	pxa2x0_gpio_set_bit(sc->lz9jg18.gpio);
336 	pxa2x0_gpio_set_bit(sc->ads7846.gpio);
337 	pxa2x0_gpio_clear_bit(sc->max1111.gpio);
338 
339 	delay(1);
340 
341 	memset(data, 0, sizeof(data));
342 	data[0] = cmd;
343 	for (i = 0; i < __arraycount(data); i++) {
344 		bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSDR, data[i]);
345 		while ((bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSSR)
346 		    & SSSR_TNF) != SSSR_TNF)
347 			continue;	/* poll */
348 		/* XXX is this delay necessary? */
349 		delay(1);
350 		while ((bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSSR)
351 		    & SSSR_RNE) != SSSR_RNE)
352 			continue;	/* poll */
353 		voltage[i] = bus_space_read_4(sc->sc_iot, sc->sc_ioh,
354 		    SSP_SSDR);
355 	}
356 
357 	pxa2x0_gpio_set_bit(sc->lz9jg18.gpio);
358 	pxa2x0_gpio_set_bit(sc->ads7846.gpio);
359 	pxa2x0_gpio_set_bit(sc->max1111.gpio);
360 
361 	bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSCR0, 0);
362 
363 	splx(s);
364 
365 	/* XXX no idea what this means, but it's what Linux would do. */
366 	if ((voltage[1] & 0xc0) != 0 || (voltage[2] & 0x3f) != 0)
367 		return -1;
368 	return ((voltage[1] << 2) & 0xfc) | ((voltage[2] >> 6) & 0x03);
369 }
370 
371 /* XXX - only does CS_ADS7846 */
372 uint32_t
373 zssp_read_ads7846(uint32_t cmd)
374 {
375 	struct zssp_softc *sc;
376 	uint32_t val;
377 	int s;
378 
379 	if (__predict_false(zssp_sc == NULL)) {
380 		aprint_error("%s: not configured\n", __func__);
381 		return 0;
382 	}
383 	sc = zssp_sc;
384 
385 	s = splhigh();
386 
387 	bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSCR0, 0);
388 	bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSCR0, sc->ads7846.sscr0);
389 
390 	pxa2x0_gpio_set_bit(sc->lz9jg18.gpio);
391 	pxa2x0_gpio_set_bit(sc->max1111.gpio);
392 	pxa2x0_gpio_clear_bit(sc->ads7846.gpio);
393 	delay(1);	/* ADS7846 Tcss = 100ns */
394 
395 	bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSDR, cmd);
396 
397 	while ((bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSSR)
398 	    & SSSR_TNF) != SSSR_TNF)
399 		continue;	/* poll */
400 
401 	delay(1);
402 
403 	while ((bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSSR)
404 	    & SSSR_RNE) != SSSR_RNE)
405 		continue;	/* poll */
406 
407 	val = bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSDR);
408 
409 	pxa2x0_gpio_set_bit(sc->ads7846.gpio);
410 
411 	splx(s);
412 
413 	return val;
414 }
415 
416 void
417 zssp_write_lz9jg18(uint32_t data)
418 {
419 	struct zssp_softc *sc;
420 	int sclk_fn;
421 	int sfrm_fn;
422 	int txd_fn;
423 	int rxd_fn;
424 	int i;
425 	int s;
426 
427 	KASSERT(zssp_sc != NULL);
428 	sc = zssp_sc;
429 
430 	/* XXX this creates a DAC command from a backlight duty value. */
431 	data = 0x40 | (data & 0x1f);
432 
433 	s = splhigh();
434 
435 	sclk_fn = pxa2x0_gpio_get_function(sc->lz9jg18.sclk_pin);
436 	sfrm_fn = pxa2x0_gpio_get_function(sc->lz9jg18.sfrm_pin);
437 	txd_fn = pxa2x0_gpio_get_function(sc->lz9jg18.txd_pin);
438 	rxd_fn = pxa2x0_gpio_get_function(sc->lz9jg18.rxd_pin);
439 
440 	pxa2x0_gpio_set_function(sc->lz9jg18.sfrm_pin, GPIO_OUT | GPIO_SET);
441 	pxa2x0_gpio_set_function(sc->lz9jg18.sclk_pin, GPIO_OUT | GPIO_CLR);
442 	pxa2x0_gpio_set_function(sc->lz9jg18.txd_pin, GPIO_OUT | GPIO_CLR);
443 	pxa2x0_gpio_set_function(sc->lz9jg18.rxd_pin, GPIO_IN);
444 
445 	pxa2x0_gpio_set_bit(sc->max1111.gpio);
446 	pxa2x0_gpio_set_bit(sc->ads7846.gpio);
447 	pxa2x0_gpio_clear_bit(sc->lz9jg18.gpio);
448 
449 	delay(10);
450 
451 	for (i = 0; i < 8; i++) {
452 		if (data & 0x80)
453 			pxa2x0_gpio_set_bit(sc->lz9jg18.txd_pin);
454 		else
455 			pxa2x0_gpio_clear_bit(sc->lz9jg18.txd_pin);
456 		delay(10);
457 		pxa2x0_gpio_set_bit(sc->lz9jg18.sclk_pin);
458 		delay(10);
459 		pxa2x0_gpio_clear_bit(sc->lz9jg18.sclk_pin);
460 		delay(10);
461 		data <<= 1;
462 	}
463 
464 	pxa2x0_gpio_clear_bit(sc->lz9jg18.txd_pin);
465 	pxa2x0_gpio_set_bit(sc->lz9jg18.gpio);
466 
467 	pxa2x0_gpio_set_function(sc->lz9jg18.sclk_pin, sclk_fn);
468 	pxa2x0_gpio_set_function(sc->lz9jg18.sfrm_pin, sfrm_fn);
469 	pxa2x0_gpio_set_function(sc->lz9jg18.txd_pin, txd_fn);
470 	pxa2x0_gpio_set_function(sc->lz9jg18.rxd_pin, rxd_fn);
471 
472 	splx(s);
473 }
474