xref: /netbsd-src/sys/arch/zaurus/dev/zssp.c (revision 4fee23f98c45552038ad6b5bd05124a41302fb01) 
1 /*	$NetBSD: zssp.c,v 1.10 2011/06/19 16:20:09 nonaka Exp $	*/
2 /*	$OpenBSD: zaurus_ssp.c,v 1.6 2005/04/08 21:58:49 uwe Exp $	*/
3 
4 /*
5  * Copyright (c) 2005 Uwe Stuehler <uwe@bsdx.de>
6  *
7  * Permission to use, copy, modify, and distribute this software for any
8  * purpose with or without fee is hereby granted, provided that the above
9  * copyright notice and this permission notice appear in all copies.
10  *
11  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18  */
19 
20 #include <sys/cdefs.h>
21 __KERNEL_RCSID(0, "$NetBSD: zssp.c,v 1.10 2011/06/19 16:20:09 nonaka Exp $");
22 
23 #include <sys/param.h>
24 #include <sys/systm.h>
25 #include <sys/device.h>
26 
27 #include <machine/bus.h>
28 
29 #include <arm/xscale/pxa2x0reg.h>
30 #include <arm/xscale/pxa2x0var.h>
31 #include <arm/xscale/pxa2x0_gpio.h>
32 
33 #include <zaurus/dev/zsspvar.h>
34 #include <zaurus/zaurus/zaurus_var.h>
35 
36 #define GPIO_ADS7846_CS_C3000	14	/* SSP SFRM */
37 #define GPIO_MAX1111_CS_C3000	20
38 #define GPIO_TG_CS_C3000	53
39 
40 #define SSCR0_ADS7846_C3000	0x06ab /* 12bit/Microwire/div by 7 */
41 #define SSCR0_MAX1111		0x0387
42 #define	SSCR0_LZ9JG18		0x01ab
43 
44 struct zssp_softc {
45 	device_t sc_dev;
46 	bus_space_tag_t sc_iot;
47 	bus_space_handle_t sc_ioh;
48 };
49 
50 static int	zssp_match(device_t, cfdata_t, void *);
51 static void	zssp_attach(device_t, device_t, void *);
52 
53 CFATTACH_DECL_NEW(zssp, sizeof(struct zssp_softc),
54 	zssp_match, zssp_attach, NULL, NULL);
55 
56 static void	zssp_init(void);
57 static bool	zssp_resume(device_t dv, const pmf_qual_t *);
58 
59 static struct zssp_softc *zssp_sc;
60 
61 static int
62 zssp_match(device_t parent, cfdata_t cf, void *aux)
63 {
64 
65 	if (zssp_sc != NULL)
66 		return 0;
67 	return 1;
68 }
69 
70 static void
71 zssp_attach(device_t parent, device_t self, void *aux)
72 {
73 	struct zssp_softc *sc = device_private(self);
74 
75 	sc->sc_dev = self;
76 	zssp_sc = sc;
77 
78 	aprint_normal("\n");
79 	aprint_naive("\n");
80 
81 	sc->sc_iot = &pxa2x0_bs_tag;
82 	if (bus_space_map(sc->sc_iot, PXA2X0_SSP1_BASE, PXA2X0_SSP_SIZE,
83 	    0, &sc->sc_ioh)) {
84 		aprint_error_dev(sc->sc_dev, "can't map bus space\n");
85 		return;
86 	}
87 
88 	if (!pmf_device_register(sc->sc_dev, NULL, zssp_resume))
89 		aprint_error_dev(sc->sc_dev,
90 		    "couldn't establish power handler\n");
91 
92 	zssp_init();
93 }
94 
95 /*
96  * Initialize the dedicated SSP unit and disable all chip selects.
97  * This function is called with interrupts disabled.
98  */
99 static void
100 zssp_init(void)
101 {
102 	struct zssp_softc *sc;
103 
104 	KASSERT(zssp_sc != NULL);
105 	sc = zssp_sc;
106 
107 	pxa2x0_clkman_config(CKEN_SSP, 1);
108 
109 	bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSCR0, SSCR0_LZ9JG18);
110 	bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSCR1, 0);
111 
112 	pxa2x0_gpio_set_function(GPIO_ADS7846_CS_C3000, GPIO_OUT|GPIO_SET);
113 	pxa2x0_gpio_set_function(GPIO_MAX1111_CS_C3000, GPIO_OUT|GPIO_SET);
114 	pxa2x0_gpio_set_function(GPIO_TG_CS_C3000, GPIO_OUT|GPIO_SET);
115 }
116 
117 static bool
118 zssp_resume(device_t dv, const pmf_qual_t *qual)
119 {
120 	int s;
121 
122 	s = splhigh();
123 	zssp_init();
124 	splx(s);
125 
126 	return true;
127 }
128 
129 /*
130  * Transmit a single data word to one of the ICs, keep the chip selected
131  * afterwards, and don't wait for data to be returned in SSDR.  Interrupts
132  * must be held off until zssp_ic_stop() gets called.
133  */
134 void
135 zssp_ic_start(int ic, uint32_t data)
136 {
137 	struct zssp_softc *sc;
138 
139 	KASSERT(zssp_sc != NULL);
140 	sc = zssp_sc;
141 
142 	/* disable other ICs */
143 	bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSCR0, 0);
144 	if (ic != ZSSP_IC_ADS7846)
145 		pxa2x0_gpio_set_bit(GPIO_ADS7846_CS_C3000);
146 	if (ic != ZSSP_IC_LZ9JG18)
147 		pxa2x0_gpio_set_bit(GPIO_TG_CS_C3000);
148 	if (ic != ZSSP_IC_MAX1111)
149 		pxa2x0_gpio_set_bit(GPIO_MAX1111_CS_C3000);
150 
151 	/* activate the chosen one */
152 	switch (ic) {
153 	case ZSSP_IC_ADS7846:
154 		bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSCR0,
155 		    SSCR0_ADS7846_C3000);
156 		pxa2x0_gpio_clear_bit(GPIO_ADS7846_CS_C3000);
157 		bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSDR, data);
158 		while ((bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSSR)
159 		    & SSSR_TNF) != SSSR_TNF)
160 			continue;	/* poll */
161 		break;
162 	case ZSSP_IC_LZ9JG18:
163 		pxa2x0_gpio_clear_bit(GPIO_TG_CS_C3000);
164 		break;
165 	case ZSSP_IC_MAX1111:
166 		pxa2x0_gpio_clear_bit(GPIO_MAX1111_CS_C3000);
167 		break;
168 	}
169 }
170 
171 /*
172  * Read the last value from SSDR and deactivate all chip-selects.
173  */
174 uint32_t
175 zssp_ic_stop(int ic)
176 {
177 	struct zssp_softc *sc;
178 	uint32_t rv;
179 
180 	KASSERT(zssp_sc != NULL);
181 	sc = zssp_sc;
182 
183 	switch (ic) {
184 	case ZSSP_IC_ADS7846:
185 		/* read result of last command */
186 		while ((bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSSR)
187 		    & SSSR_RNE) != SSSR_RNE)
188 			continue;	/* poll */
189 		rv = bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSDR);
190 		break;
191 	case ZSSP_IC_LZ9JG18:
192 	case ZSSP_IC_MAX1111:
193 		/* last value received is irrelevant or undefined */
194 	default:
195 		rv = 0;
196 		break;
197 	}
198 
199 	pxa2x0_gpio_set_bit(GPIO_ADS7846_CS_C3000);
200 	pxa2x0_gpio_set_bit(GPIO_TG_CS_C3000);
201 	pxa2x0_gpio_set_bit(GPIO_MAX1111_CS_C3000);
202 
203 	return rv;
204 }
205 
206 /*
207  * Activate one of the chip-select lines, transmit one word value in
208  * each direction, and deactivate the chip-select again.
209  */
210 uint32_t
211 zssp_ic_send(int ic, uint32_t data)
212 {
213 
214 	switch (ic) {
215 	case ZSSP_IC_MAX1111:
216 		return (zssp_read_max1111(data));
217 	case ZSSP_IC_ADS7846:
218 		return (zssp_read_ads7846(data));
219 	case ZSSP_IC_LZ9JG18:
220 		zssp_write_lz9jg18(data);
221 		return 0;
222 	default:
223 		aprint_error("zssp: zssp_ic_send: invalid IC %d\n", ic);
224 		return 0;
225 	}
226 }
227 
228 int
229 zssp_read_max1111(uint32_t cmd)
230 {
231 	struct zssp_softc *sc;
232 	int data[3];
233 	int voltage[3];	/* voltage[0]: dummy */
234 	int i;
235 	int s;
236 
237 	KASSERT(zssp_sc != NULL);
238 	sc = zssp_sc;
239 
240 	s = splhigh();
241 
242 	bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSCR0, 0);
243 	bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSCR0, SSCR0_MAX1111);
244 
245 	pxa2x0_gpio_set_bit(GPIO_TG_CS_C3000);
246 	pxa2x0_gpio_set_bit(GPIO_ADS7846_CS_C3000);
247 	pxa2x0_gpio_clear_bit(GPIO_MAX1111_CS_C3000);
248 
249 	delay(1);
250 
251 	memset(data, 0, sizeof(data));
252 	data[0] = cmd;
253 	for (i = 0; i < __arraycount(data); i++) {
254 		bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSDR, data[i]);
255 		while ((bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSSR)
256 		    & SSSR_TNF) != SSSR_TNF)
257 			continue;	/* poll */
258 		/* XXX is this delay necessary? */
259 		delay(1);
260 		while ((bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSSR)
261 		    & SSSR_RNE) != SSSR_RNE)
262 			continue;	/* poll */
263 		voltage[i] = bus_space_read_4(sc->sc_iot, sc->sc_ioh,
264 		    SSP_SSDR);
265 	}
266 
267 	pxa2x0_gpio_set_bit(GPIO_TG_CS_C3000);
268 	pxa2x0_gpio_set_bit(GPIO_ADS7846_CS_C3000);
269 	pxa2x0_gpio_set_bit(GPIO_MAX1111_CS_C3000);
270 
271 	bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSCR0, 0);
272 
273 	splx(s);
274 
275 	/* XXX no idea what this means, but it's what Linux would do. */
276 	if ((voltage[1] & 0xc0) != 0 || (voltage[2] & 0x3f) != 0)
277 		return -1;
278 	return ((voltage[1] << 2) & 0xfc) | ((voltage[2] >> 6) & 0x03);
279 }
280 
281 /* XXX - only does CS_ADS7846 */
282 uint32_t
283 zssp_read_ads7846(uint32_t cmd)
284 {
285 	struct zssp_softc *sc;
286 	unsigned int cr0;
287 	uint32_t val;
288 	int s;
289 
290 	if (zssp_sc == NULL) {
291 		printf("zssp_read_ads7846: not configured\n");
292 		return 0;
293 	}
294 	sc = zssp_sc;
295 
296 	s = splhigh();
297 
298 	if (ZAURUS_ISC1000 || ZAURUS_ISC3000) {
299 		cr0 = SSCR0_ADS7846_C3000;
300 	} else {
301 		cr0 = 0x00ab;
302 	}
303         bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSCR0, 0);
304 	bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSCR0, cr0);
305 
306 	pxa2x0_gpio_set_bit(GPIO_TG_CS_C3000);
307 	pxa2x0_gpio_set_bit(GPIO_MAX1111_CS_C3000);
308 	pxa2x0_gpio_clear_bit(GPIO_ADS7846_CS_C3000);
309 
310 	bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSDR, cmd);
311 
312 	while ((bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSSR)
313 	    & SSSR_TNF) != SSSR_TNF)
314 		continue;	/* poll */
315 
316 	delay(1);
317 
318 	while ((bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSSR)
319 	    & SSSR_RNE) != SSSR_RNE)
320 		continue;	/* poll */
321 
322 	val = bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSDR);
323 
324 	pxa2x0_gpio_set_bit(GPIO_ADS7846_CS_C3000);
325 
326 	splx(s);
327 
328 	return val;
329 }
330 
331 void
332 zssp_write_lz9jg18(uint32_t data)
333 {
334 	int sclk_pin, sclk_fn;
335 	int sfrm_pin, sfrm_fn;
336 	int txd_pin, txd_fn;
337 	int rxd_pin, rxd_fn;
338 	int i;
339 	int s;
340 
341 	/* XXX this creates a DAC command from a backlight duty value. */
342 	data = 0x40 | (data & 0x1f);
343 
344 	if (ZAURUS_ISC1000 || ZAURUS_ISC3000) {
345 		sclk_pin = 19;
346 		sfrm_pin = 14;
347 		txd_pin = 87;
348 		rxd_pin = 86;
349 	} else {
350 		sclk_pin = 23;
351 		sfrm_pin = 24;
352 		txd_pin = 25;
353 		rxd_pin = 26;
354 	}
355 
356 	s = splhigh();
357 
358 	sclk_fn = pxa2x0_gpio_get_function(sclk_pin);
359 	sfrm_fn = pxa2x0_gpio_get_function(sfrm_pin);
360 	txd_fn = pxa2x0_gpio_get_function(txd_pin);
361 	rxd_fn = pxa2x0_gpio_get_function(rxd_pin);
362 
363 	pxa2x0_gpio_set_function(sfrm_pin, GPIO_OUT | GPIO_SET);
364 	pxa2x0_gpio_set_function(sclk_pin, GPIO_OUT | GPIO_CLR);
365 	pxa2x0_gpio_set_function(txd_pin, GPIO_OUT | GPIO_CLR);
366 	pxa2x0_gpio_set_function(rxd_pin, GPIO_IN);
367 
368 	pxa2x0_gpio_set_bit(GPIO_MAX1111_CS_C3000);
369 	pxa2x0_gpio_set_bit(GPIO_ADS7846_CS_C3000);
370 	pxa2x0_gpio_clear_bit(GPIO_TG_CS_C3000);
371 
372 	delay(10);
373 
374 	for (i = 0; i < 8; i++) {
375 		if (data & 0x80)
376 			pxa2x0_gpio_set_bit(txd_pin);
377 		else
378 			pxa2x0_gpio_clear_bit(txd_pin);
379 		delay(10);
380 		pxa2x0_gpio_set_bit(sclk_pin);
381 		delay(10);
382 		pxa2x0_gpio_clear_bit(sclk_pin);
383 		delay(10);
384 		data <<= 1;
385 	}
386 
387 	pxa2x0_gpio_clear_bit(txd_pin);
388 	pxa2x0_gpio_set_bit(GPIO_TG_CS_C3000);
389 
390 	pxa2x0_gpio_set_function(sclk_pin, sclk_fn);
391 	pxa2x0_gpio_set_function(sfrm_pin, sfrm_fn);
392 	pxa2x0_gpio_set_function(txd_pin, txd_fn);
393 	pxa2x0_gpio_set_function(rxd_pin, rxd_fn);
394 
395 	splx(s);
396 }
397