1 /* $NetBSD: xen_intr.c,v 1.17 2019/06/07 12:43:52 cherry Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum, and by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: xen_intr.c,v 1.17 2019/06/07 12:43:52 cherry Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/kernel.h> 37 #include <sys/kmem.h> 38 39 #include <sys/cpu.h> 40 41 #include <xen/evtchn.h> 42 #include <xen/xenfunc.h> 43 44 #include <uvm/uvm.h> 45 46 #include <machine/cpu.h> 47 #include <machine/intr.h> 48 49 #include "acpica.h" 50 #include "ioapic.h" 51 #include "lapic.h" 52 #include "pci.h" 53 54 #if NACPICA > 0 55 #include <dev/acpi/acpivar.h> 56 #endif 57 58 #if NIOAPIC > 0 || NACPICA > 0 59 #include <machine/i82093var.h> 60 #endif 61 62 #if NLAPIC > 0 63 #include <machine/i82489var.h> 64 #endif 65 66 #if NPCI > 0 67 #include <dev/pci/ppbreg.h> 68 #endif 69 70 /* 71 * Restore a value to cpl (unmasking interrupts). If any unmasked 72 * interrupts are pending, call Xspllower() to process them. 73 */ 74 void xen_spllower(int nlevel); 75 76 void 77 xen_spllower(int nlevel) 78 { 79 struct cpu_info *ci = curcpu(); 80 uint32_t xmask; 81 u_long psl; 82 83 if (ci->ci_ilevel <= nlevel) 84 return; 85 86 __insn_barrier(); 87 88 xmask = XUNMASK(ci, nlevel); 89 psl = xen_read_psl(); 90 x86_disable_intr(); 91 if (ci->ci_xpending & xmask) { 92 KASSERT(psl == 0); 93 Xspllower(nlevel); 94 /* Xspllower does enable_intr() */ 95 } else { 96 ci->ci_ilevel = nlevel; 97 xen_write_psl(psl); 98 } 99 } 100 101 102 #if !defined(XENPVHVM) 103 void 104 x86_disable_intr(void) 105 { 106 curcpu()->ci_vcpu->evtchn_upcall_mask = 1; 107 x86_lfence(); 108 } 109 110 void 111 x86_enable_intr(void) 112 { 113 volatile struct vcpu_info *_vci = curcpu()->ci_vcpu; 114 __insn_barrier(); 115 _vci->evtchn_upcall_mask = 0; 116 x86_lfence(); /* unmask then check (avoid races) */ 117 if (__predict_false(_vci->evtchn_upcall_pending)) 118 hypervisor_force_callback(); 119 } 120 121 #endif /* !XENPVHVM */ 122 123 u_long 124 xen_read_psl(void) 125 { 126 127 return (curcpu()->ci_vcpu->evtchn_upcall_mask); 128 } 129 130 void 131 xen_write_psl(u_long psl) 132 { 133 struct cpu_info *ci = curcpu(); 134 135 ci->ci_vcpu->evtchn_upcall_mask = psl; 136 xen_rmb(); 137 if (ci->ci_vcpu->evtchn_upcall_pending && psl == 0) { 138 hypervisor_force_callback(); 139 } 140 } 141 142 void * 143 xen_intr_establish(int legacy_irq, struct pic *pic, int pin, 144 int type, int level, int (*handler)(void *), void *arg, 145 bool known_mpsafe) 146 { 147 148 return xen_intr_establish_xname(legacy_irq, pic, pin, type, level, 149 handler, arg, known_mpsafe, "XEN"); 150 } 151 152 void * 153 xen_intr_establish_xname(int legacy_irq, struct pic *pic, int pin, 154 int type, int level, int (*handler)(void *), void *arg, 155 bool known_mpsafe, const char *xname) 156 { 157 const char *intrstr; 158 char intrstr_buf[INTRIDBUF]; 159 160 if (pic->pic_type == PIC_XEN) { 161 struct intrhand *rih; 162 163 /* 164 * event_set_handler interprets `level != IPL_VM' to 165 * mean MP-safe, so we require the caller to match that 166 * for the moment. 167 */ 168 KASSERT(known_mpsafe == (level != IPL_VM)); 169 170 intrstr = intr_create_intrid(legacy_irq, pic, pin, intrstr_buf, 171 sizeof(intrstr_buf)); 172 173 event_set_handler(pin, handler, arg, level, intrstr, xname); 174 175 rih = kmem_zalloc(sizeof(*rih), cold ? KM_NOSLEEP : KM_SLEEP); 176 if (rih == NULL) { 177 printf("%s: can't allocate handler info\n", __func__); 178 return NULL; 179 } 180 181 /* 182 * XXX: 183 * This is just a copy for API conformance. 184 * The real ih is lost in the innards of 185 * event_set_handler(); where the details of 186 * biglock_wrapper etc are taken care of. 187 * All that goes away when we nuke event_set_handler() 188 * et. al. and unify with x86/intr.c 189 */ 190 rih->ih_pin = pin; /* port */ 191 rih->ih_fun = rih->ih_realfun = handler; 192 rih->ih_arg = rih->ih_realarg = arg; 193 rih->pic_type = pic->pic_type; 194 return rih; 195 } /* Else we assume pintr */ 196 197 #if (NPCI > 0 || NISA > 0) && defined(XENPV) /* XXX: support PVHVM pirq */ 198 struct pintrhand *pih; 199 int gsi; 200 int vector, evtchn; 201 202 KASSERTMSG(legacy_irq == -1 || (0 <= legacy_irq && legacy_irq < NUM_XEN_IRQS), 203 "bad legacy IRQ value: %d", legacy_irq); 204 KASSERTMSG(!(legacy_irq == -1 && pic == &i8259_pic), 205 "non-legacy IRQon i8259 "); 206 207 gsi = xen_pic_to_gsi(pic, pin); 208 209 intrstr = intr_create_intrid(gsi, pic, pin, intrstr_buf, 210 sizeof(intrstr_buf)); 211 212 vector = xen_vec_alloc(gsi); 213 214 if (irq2port[gsi] == 0) { 215 extern struct cpu_info phycpu_info_primary; /* XXX */ 216 struct cpu_info *ci = &phycpu_info_primary; 217 218 pic->pic_addroute(pic, ci, pin, vector, type); 219 220 evtchn = bind_pirq_to_evtch(gsi); 221 KASSERT(evtchn > 0); 222 KASSERT(evtchn < NR_EVENT_CHANNELS); 223 irq2port[gsi] = evtchn + 1; 224 xen_atomic_set_bit(&ci->ci_evtmask[0], evtchn); 225 } else { 226 /* 227 * Shared interrupt - we can't rebind. 228 * The port is shared instead. 229 */ 230 evtchn = irq2port[gsi] - 1; 231 } 232 233 pih = pirq_establish(gsi, evtchn, handler, arg, level, 234 intrstr, xname); 235 pih->pic_type = pic->pic_type; 236 return pih; 237 #endif /* NPCI > 0 || NISA > 0 */ 238 239 /* FALLTHROUGH */ 240 return NULL; 241 } 242 243 /* 244 * Deregister an interrupt handler. 245 */ 246 void 247 xen_intr_disestablish(struct intrhand *ih) 248 { 249 250 if (ih->pic_type == PIC_XEN) { 251 event_remove_handler(ih->ih_pin, ih->ih_realfun, 252 ih->ih_realarg); 253 kmem_free(ih, sizeof(*ih)); 254 return; 255 } 256 #if defined(DOM0OPS) 257 /* 258 * Cache state, to prevent a use after free situation with 259 * ih. 260 */ 261 262 struct pintrhand *pih = (struct pintrhand *)ih; 263 264 int pirq = pih->pirq; 265 int port = pih->evtch; 266 KASSERT(irq2port[pirq] != 0); 267 268 pirq_disestablish(pih); 269 270 if (evtsource[port] == NULL) { 271 /* 272 * Last handler was removed by 273 * event_remove_handler(). 274 * 275 * We can safely unbind the pirq now. 276 */ 277 278 port = unbind_pirq_from_evtch(pirq); 279 KASSERT(port == pih->evtch); 280 irq2port[pirq] = 0; 281 } 282 #endif 283 return; 284 } 285 286 /* MI interface for kern_cpu.c */ 287 void xen_cpu_intr_redistribute(void); 288 289 void 290 xen_cpu_intr_redistribute(void) 291 { 292 KASSERT(mutex_owned(&cpu_lock)); 293 KASSERT(mp_online); 294 295 return; 296 } 297 298 /* MD - called by x86/cpu.c */ 299 #if defined(INTRSTACKSIZE) 300 static inline bool 301 redzone_const_or_false(bool x) 302 { 303 #ifdef DIAGNOSTIC 304 return x; 305 #else 306 return false; 307 #endif /* !DIAGNOSTIC */ 308 } 309 310 static inline int 311 redzone_const_or_zero(int x) 312 { 313 return redzone_const_or_false(true) ? x : 0; 314 } 315 #endif 316 317 void xen_cpu_intr_init(struct cpu_info *); 318 void 319 xen_cpu_intr_init(struct cpu_info *ci) 320 { 321 int i; /* XXX: duplicate */ 322 323 ci->ci_xunmask[0] = 0xfffffffe; 324 for (i = 1; i < NIPL; i++) 325 ci->ci_xunmask[i] = ci->ci_xunmask[i - 1] & ~(1 << i); 326 327 #if defined(INTRSTACKSIZE) 328 vaddr_t istack; 329 330 /* 331 * If the red zone is activated, protect both the top and 332 * the bottom of the stack with an unmapped page. 333 */ 334 istack = uvm_km_alloc(kernel_map, 335 INTRSTACKSIZE + redzone_const_or_zero(2 * PAGE_SIZE), 0, 336 UVM_KMF_WIRED|UVM_KMF_ZERO); 337 if (redzone_const_or_false(true)) { 338 pmap_kremove(istack, PAGE_SIZE); 339 pmap_kremove(istack + INTRSTACKSIZE + PAGE_SIZE, PAGE_SIZE); 340 pmap_update(pmap_kernel()); 341 } 342 343 /* 344 * 33 used to be 1. Arbitrarily reserve 32 more register_t's 345 * of space for ddb(4) to examine some subroutine arguments 346 * and to hunt for the next stack frame. 347 */ 348 ci->ci_intrstack = (char *)istack + redzone_const_or_zero(PAGE_SIZE) + 349 INTRSTACKSIZE - 33 * sizeof(register_t); 350 #endif 351 352 ci->ci_idepth = -1; 353 } 354 355 /* 356 * Everything below from here is duplicated from x86/intr.c 357 * When intr.c and xen_intr.c are unified, these will need to be 358 * merged. 359 */ 360 361 u_int xen_cpu_intr_count(struct cpu_info *ci); 362 363 u_int 364 xen_cpu_intr_count(struct cpu_info *ci) 365 { 366 367 KASSERT(ci->ci_nintrhand >= 0); 368 369 return ci->ci_nintrhand; 370 } 371 372 static const char * 373 xen_intr_string(int port, char *buf, size_t len, struct pic *pic) 374 { 375 KASSERT(pic->pic_type == PIC_XEN); 376 377 KASSERT(port >= 0); 378 KASSERT(port < NR_EVENT_CHANNELS); 379 380 snprintf(buf, len, "%s channel %d", pic->pic_name, port); 381 382 return buf; 383 } 384 385 static const char * 386 legacy_intr_string(int ih, char *buf, size_t len, struct pic *pic) 387 { 388 int legacy_irq; 389 390 KASSERT(pic->pic_type == PIC_I8259); 391 #if NLAPIC > 0 392 KASSERT(APIC_IRQ_ISLEGACY(ih)); 393 394 legacy_irq = APIC_IRQ_LEGACY_IRQ(ih); 395 #else 396 legacy_irq = ih; 397 #endif 398 KASSERT(legacy_irq >= 0 && legacy_irq < 16); 399 400 snprintf(buf, len, "%s pin %d", pic->pic_name, legacy_irq); 401 402 return buf; 403 } 404 405 const char * xintr_string(intr_handle_t ih, char *buf, size_t len); 406 407 const char * 408 xintr_string(intr_handle_t ih, char *buf, size_t len) 409 { 410 #if NIOAPIC > 0 411 struct ioapic_softc *pic; 412 #endif 413 414 if (ih == 0) 415 panic("%s: bogus handle 0x%" PRIx64, __func__, ih); 416 417 #if NIOAPIC > 0 418 if (ih & APIC_INT_VIA_APIC) { 419 pic = ioapic_find(APIC_IRQ_APIC(ih)); 420 if (pic != NULL) { 421 snprintf(buf, len, "%s pin %d", 422 device_xname(pic->sc_dev), APIC_IRQ_PIN(ih)); 423 } else { 424 snprintf(buf, len, 425 "apic %d int %d (irq %d)", 426 APIC_IRQ_APIC(ih), 427 APIC_IRQ_PIN(ih), 428 APIC_IRQ_LEGACY_IRQ(ih)); 429 } 430 } else 431 snprintf(buf, len, "irq %d", APIC_IRQ_LEGACY_IRQ(ih)); 432 433 #elif NLAPIC > 0 434 snprintf(buf, len, "irq %d", APIC_IRQ_LEGACY_IRQ(ih)); 435 #else 436 snprintf(buf, len, "irq %d", (int) ih); 437 #endif 438 return buf; 439 440 } 441 442 /* 443 * Create an interrupt id such as "ioapic0 pin 9". This interrupt id is used 444 * by MI code and intrctl(8). 445 */ 446 const char * xen_intr_create_intrid(int legacy_irq, struct pic *pic, 447 int pin, char *buf, size_t len); 448 449 const char * 450 xen_intr_create_intrid(int legacy_irq, struct pic *pic, int pin, char *buf, size_t len) 451 { 452 int ih = 0; 453 454 #if NPCI > 0 455 #if defined(__HAVE_PCI_MSI_MSIX) 456 if ((pic->pic_type == PIC_MSI) || (pic->pic_type == PIC_MSIX)) { 457 uint64_t pih; 458 int dev, vec; 459 460 dev = msipic_get_devid(pic); 461 vec = pin; 462 pih = __SHIFTIN((uint64_t)dev, MSI_INT_DEV_MASK) 463 | __SHIFTIN((uint64_t)vec, MSI_INT_VEC_MASK) 464 | APIC_INT_VIA_MSI; 465 if (pic->pic_type == PIC_MSI) 466 MSI_INT_MAKE_MSI(pih); 467 else if (pic->pic_type == PIC_MSIX) 468 MSI_INT_MAKE_MSIX(pih); 469 470 return x86_pci_msi_string(NULL, pih, buf, len); 471 } 472 #endif /* __HAVE_PCI_MSI_MSIX */ 473 #endif 474 475 if (pic->pic_type == PIC_XEN) { 476 ih = pin; /* Port == pin */ 477 return xen_intr_string(pin, buf, len, pic); 478 } 479 480 /* 481 * If the device is pci, "legacy_irq" is alway -1. Least 8 bit of "ih" 482 * is only used in intr_string() to show the irq number. 483 * If the device is "legacy"(such as floppy), it should not use 484 * intr_string(). 485 */ 486 if (pic->pic_type == PIC_I8259) { 487 ih = legacy_irq; 488 return legacy_intr_string(ih, buf, len, pic); 489 } 490 491 #if NIOAPIC > 0 || NACPICA > 0 492 ih = ((pic->pic_apicid << APIC_INT_APIC_SHIFT) & APIC_INT_APIC_MASK) 493 | ((pin << APIC_INT_PIN_SHIFT) & APIC_INT_PIN_MASK); 494 if (pic->pic_type == PIC_IOAPIC) { 495 ih |= APIC_INT_VIA_APIC; 496 } 497 ih |= pin; 498 return intr_string(ih, buf, len); 499 #endif 500 501 return NULL; /* No pic found! */ 502 } 503 504 #if !defined(XENPVHVM) 505 __strong_alias(spllower, xen_spllower); 506 __strong_alias(x86_read_psl, xen_read_psl); 507 __strong_alias(x86_write_psl, xen_write_psl); 508 509 __strong_alias(intr_string, xintr_string); 510 __strong_alias(intr_create_intrid, xen_intr_create_intrid); 511 __strong_alias(intr_establish, xen_intr_establish); 512 __strong_alias(intr_establish_xname, xen_intr_establish_xname); 513 __strong_alias(intr_disestablish, xen_intr_disestablish); 514 __strong_alias(cpu_intr_redistribute, xen_cpu_intr_redistribute); 515 __strong_alias(cpu_intr_count, xen_cpu_intr_count); 516 __strong_alias(cpu_intr_init, xen_cpu_intr_init); 517 #endif /* !XENPVHVM */ 518