1 /* $NetBSD: hypervisor_machdep.c,v 1.4 2007/12/20 23:46:11 ad Exp $ */ 2 3 /* 4 * 5 * Copyright (c) 2004 Christian Limpach. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Christian Limpach. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /****************************************************************************** 35 * hypervisor.c 36 * 37 * Communication to/from hypervisor. 38 * 39 * Copyright (c) 2002-2004, K A Fraser 40 * 41 * Permission is hereby granted, free of charge, to any person obtaining a copy 42 * of this software and associated documentation files (the "Software"), to 43 * deal in the Software without restriction, including without limitation the 44 * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or 45 * sell copies of the Software, and to permit persons to whom the Software is 46 * furnished to do so, subject to the following conditions: 47 * 48 * The above copyright notice and this permission notice shall be included in 49 * all copies or substantial portions of the Software. 50 * 51 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 52 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 53 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 54 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 55 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 56 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 57 * DEALINGS IN THE SOFTWARE. 58 */ 59 60 61 #include <sys/cdefs.h> 62 __KERNEL_RCSID(0, "$NetBSD: hypervisor_machdep.c,v 1.4 2007/12/20 23:46:11 ad Exp $"); 63 64 #include <sys/param.h> 65 #include <sys/systm.h> 66 67 #include <xen/xen.h> 68 #include <xen/hypervisor.h> 69 #include <xen/evtchn.h> 70 71 #include "opt_xen.h" 72 73 // #define PORT_DEBUG 4 74 // #define EARLY_DEBUG_EVENT 75 76 int stipending(void); 77 int 78 stipending() 79 { 80 uint32_t l1; 81 unsigned long l2; 82 unsigned int l1i, l2i, port; 83 volatile shared_info_t *s = HYPERVISOR_shared_info; 84 struct cpu_info *ci; 85 int ret; 86 87 ret = 0; 88 ci = curcpu(); 89 90 #if 0 91 if (HYPERVISOR_shared_info->events) 92 printf("stipending events %08lx mask %08lx ilevel %d\n", 93 HYPERVISOR_shared_info->events, 94 HYPERVISOR_shared_info->events_mask, ci->ci_ilevel); 95 #endif 96 97 #ifdef EARLY_DEBUG_EVENT 98 if (xen_atomic_test_bit(&s->evtchn_pending[0], debug_port)) { 99 xen_debug_handler(NULL); 100 xen_atomic_clear_bit(&s->evtchn_pending[0], debug_port); 101 } 102 #endif 103 104 /* 105 * we're only called after STIC, so we know that we'll have to 106 * STI at the end 107 */ 108 while (s->vcpu_info[0].evtchn_upcall_pending) { 109 cli(); 110 s->vcpu_info[0].evtchn_upcall_pending = 0; 111 /* NB. No need for a barrier here -- XCHG is a barrier 112 * on x86. */ 113 #ifdef XEN3 114 l1 = xen_atomic_xchg(&s->vcpu_info[0].evtchn_pending_sel, 0); 115 #else 116 l1 = xen_atomic_xchg(&s->evtchn_pending_sel, 0); 117 #endif 118 while ((l1i = ffs(l1)) != 0) { 119 l1i--; 120 l1 &= ~(1 << l1i); 121 122 l2 = s->evtchn_pending[l1i] & ~s->evtchn_mask[l1i]; 123 /* 124 * mask and clear event. More efficient than calling 125 * hypervisor_mask/clear_event for each event. 126 */ 127 xen_atomic_setbits_l(&s->evtchn_mask[l1i], l2); 128 xen_atomic_clearbits_l(&s->evtchn_pending[l1i], l2); 129 while ((l2i = ffs(l2)) != 0) { 130 l2i--; 131 l2 &= ~(1 << l2i); 132 133 port = (l1i << 5) + l2i; 134 if (evtsource[port]) { 135 hypervisor_set_ipending( 136 evtsource[port]->ev_imask, 137 l1i, l2i); 138 evtsource[port]->ev_evcnt.ev_count++; 139 if (ret == 0 && ci->ci_ilevel < 140 evtsource[port]->ev_maxlevel) 141 ret = 1; 142 } 143 #ifdef DOM0OPS 144 else 145 xenevt_event(port); 146 #endif 147 } 148 } 149 sti(); 150 } 151 152 #if 0 153 if (ci->ci_ipending & 0x1) 154 printf("stipending events %08lx mask %08lx ilevel %d ipending %08x\n", 155 HYPERVISOR_shared_info->events, 156 HYPERVISOR_shared_info->events_mask, ci->ci_ilevel, 157 ci->ci_ipending); 158 #endif 159 160 return (ret); 161 } 162 163 void 164 do_hypervisor_callback(struct intrframe *regs) 165 { 166 uint32_t l1; 167 unsigned long l2; 168 unsigned int l1i, l2i, port; 169 volatile shared_info_t *s = HYPERVISOR_shared_info; 170 struct cpu_info *ci; 171 int level; 172 173 ci = curcpu(); 174 level = ci->ci_ilevel; 175 176 // DDD printf("do_hypervisor_callback\n"); 177 178 #ifdef EARLY_DEBUG_EVENT 179 if (xen_atomic_test_bit(&s->evtchn_pending[0], debug_port)) { 180 xen_debug_handler(NULL); 181 xen_atomic_clear_bit(&s->evtchn_pending[0], debug_port); 182 } 183 #endif 184 185 while (s->vcpu_info[0].evtchn_upcall_pending) { 186 s->vcpu_info[0].evtchn_upcall_pending = 0; 187 /* NB. No need for a barrier here -- XCHG is a barrier 188 * on x86. */ 189 #ifdef XEN3 190 l1 = xen_atomic_xchg(&s->vcpu_info[0].evtchn_pending_sel, 0); 191 #else 192 l1 = xen_atomic_xchg(&s->evtchn_pending_sel, 0); 193 #endif 194 while ((l1i = ffs(l1)) != 0) { 195 l1i--; 196 l1 &= ~(1 << l1i); 197 198 l2 = s->evtchn_pending[l1i] & ~s->evtchn_mask[l1i]; 199 /* 200 * mask and clear the pending events. 201 * Doing it here for all event that will be processed 202 * avoids a race with stipending (which can be called 203 * though evtchn_do_event->splx) that could cause an event to 204 * be both processed and marked pending. 205 */ 206 xen_atomic_setbits_l(&s->evtchn_mask[l1i], l2); 207 xen_atomic_clearbits_l(&s->evtchn_pending[l1i], l2); 208 209 while ((l2i = ffs(l2)) != 0) { 210 l2i--; 211 l2 &= ~(1 << l2i); 212 213 port = (l1i << 5) + l2i; 214 #ifdef PORT_DEBUG 215 if (port == PORT_DEBUG) 216 printf("do_hypervisor_callback event %d\n", port); 217 #endif 218 if (evtsource[port]) 219 call_evtchn_do_event(port, regs); 220 #ifdef DOM0OPS 221 else 222 xenevt_event(port); 223 #endif 224 } 225 } 226 } 227 228 #ifdef DIAGNOSTIC 229 if (level != ci->ci_ilevel) 230 printf("hypervisor done %08x level %d/%d ipending %08x\n", 231 #ifdef XEN3 232 (uint)HYPERVISOR_shared_info->vcpu_info[0].evtchn_pending_sel, 233 #else 234 (uint)HYPERVISOR_shared_info->evtchn_pending_sel, 235 #endif 236 level, ci->ci_ilevel, ci->ci_ipending); 237 #endif 238 } 239 240 void 241 hypervisor_unmask_event(unsigned int ev) 242 { 243 volatile shared_info_t *s = HYPERVISOR_shared_info; 244 #ifdef PORT_DEBUG 245 if (ev == PORT_DEBUG) 246 printf("hypervisor_unmask_event %d\n", ev); 247 #endif 248 249 xen_atomic_clear_bit(&s->evtchn_mask[0], ev); 250 /* 251 * The following is basically the equivalent of 252 * 'hw_resend_irq'. Just like a real IO-APIC we 'lose the 253 * interrupt edge' if the channel is masked. 254 */ 255 if (xen_atomic_test_bit(&s->evtchn_pending[0], ev) && 256 #ifdef XEN3 257 !xen_atomic_test_and_set_bit(&s->vcpu_info[0].evtchn_pending_sel, ev>>5)) { 258 #else 259 !xen_atomic_test_and_set_bit(&s->evtchn_pending_sel, ev>>5)) { 260 #endif 261 xen_atomic_set_bit(&s->vcpu_info[0].evtchn_upcall_pending, 0); 262 if (!s->vcpu_info[0].evtchn_upcall_mask) 263 hypervisor_force_callback(); 264 } 265 } 266 267 void 268 hypervisor_mask_event(unsigned int ev) 269 { 270 volatile shared_info_t *s = HYPERVISOR_shared_info; 271 #ifdef PORT_DEBUG 272 if (ev == PORT_DEBUG) 273 printf("hypervisor_mask_event %d\n", ev); 274 #endif 275 276 xen_atomic_set_bit(&s->evtchn_mask[0], ev); 277 } 278 279 void 280 hypervisor_clear_event(unsigned int ev) 281 { 282 volatile shared_info_t *s = HYPERVISOR_shared_info; 283 #ifdef PORT_DEBUG 284 if (ev == PORT_DEBUG) 285 printf("hypervisor_clear_event %d\n", ev); 286 #endif 287 288 xen_atomic_clear_bit(&s->evtchn_pending[0], ev); 289 } 290 291 void 292 hypervisor_enable_ipl(unsigned int ipl) 293 { 294 u_int32_t l1, l2; 295 int l1i, l2i; 296 struct cpu_info *ci = curcpu(); 297 298 /* 299 * enable all events for ipl. As we only set an event in ipl_evt_mask 300 * for its lowest IPL, and pending IPLs are processed high to low, 301 * we know that all callback for this event have been processed. 302 */ 303 304 l1 = ci->ci_isources[ipl]->ipl_evt_mask1; 305 ci->ci_isources[ipl]->ipl_evt_mask1 = 0; 306 while ((l1i = ffs(l1)) != 0) { 307 l1i--; 308 l1 &= ~(1 << l1i); 309 l2 = ci->ci_isources[ipl]->ipl_evt_mask2[l1i]; 310 ci->ci_isources[ipl]->ipl_evt_mask2[l1i] = 0; 311 while ((l2i = ffs(l2)) != 0) { 312 int evtch; 313 314 l2i--; 315 l2 &= ~(1 << l2i); 316 317 evtch = (l1i << 5) + l2i; 318 hypervisor_enable_event(evtch); 319 } 320 } 321 } 322 323 void 324 hypervisor_set_ipending(u_int32_t iplmask, int l1, int l2) 325 { 326 int ipl; 327 struct cpu_info *ci = curcpu(); 328 329 /* set pending bit for the appropriate IPLs */ 330 ci->ci_ipending |= iplmask; 331 332 /* 333 * And set event pending bit for the lowest IPL. As IPL are handled 334 * from high to low, this ensure that all callbacks will have been 335 * called when we ack the event 336 */ 337 ipl = ffs(iplmask); 338 KASSERT(ipl > 0); 339 ipl--; 340 ci->ci_isources[ipl]->ipl_evt_mask1 |= 1 << l1; 341 ci->ci_isources[ipl]->ipl_evt_mask2[l1] |= 1 << l2; 342 } 343