1 /* $NetBSD: cpu.c,v 1.122 2018/06/23 10:30:22 jdolecek Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 The NetBSD Foundation, Inc. 5 * Copyright (c) 2002, 2006, 2007 YAMAMOTO Takashi, 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by RedBack Networks Inc. 10 * 11 * Author: Bill Sommerfeld 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 23 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 24 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 25 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 * POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* 36 * Copyright (c) 1999 Stefan Grefen 37 * 38 * Redistribution and use in source and binary forms, with or without 39 * modification, are permitted provided that the following conditions 40 * are met: 41 * 1. Redistributions of source code must retain the above copyright 42 * notice, this list of conditions and the following disclaimer. 43 * 2. Redistributions in binary form must reproduce the above copyright 44 * notice, this list of conditions and the following disclaimer in the 45 * documentation and/or other materials provided with the distribution. 46 * 3. All advertising materials mentioning features or use of this software 47 * must display the following acknowledgement: 48 * This product includes software developed by the NetBSD 49 * Foundation, Inc. and its contributors. 50 * 4. Neither the name of The NetBSD Foundation nor the names of its 51 * contributors may be used to endorse or promote products derived 52 * from this software without specific prior written permission. 53 * 54 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY 55 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 56 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 57 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR AND CONTRIBUTORS BE LIABLE 58 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 59 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 60 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 61 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 62 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 63 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 64 * SUCH DAMAGE. 65 */ 66 67 #include <sys/cdefs.h> 68 __KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.122 2018/06/23 10:30:22 jdolecek Exp $"); 69 70 #include "opt_ddb.h" 71 #include "opt_multiprocessor.h" 72 #include "opt_mpbios.h" /* for MPDEBUG */ 73 #include "opt_mtrr.h" 74 #include "opt_xen.h" 75 76 #include "lapic.h" 77 #include "ioapic.h" 78 79 #include <sys/param.h> 80 #include <sys/proc.h> 81 #include <sys/systm.h> 82 #include <sys/device.h> 83 #include <sys/kmem.h> 84 #include <sys/cpu.h> 85 #include <sys/cpufreq.h> 86 #include <sys/atomic.h> 87 #include <sys/reboot.h> 88 #include <sys/idle.h> 89 90 #include <uvm/uvm.h> 91 92 #include <machine/cpu.h> 93 #include <machine/cpufunc.h> 94 #include <machine/cpuvar.h> 95 #include <machine/pmap.h> 96 #include <machine/vmparam.h> 97 #include <machine/mpbiosvar.h> 98 #include <machine/pcb.h> 99 #include <machine/specialreg.h> 100 #include <machine/segments.h> 101 #include <machine/gdt.h> 102 #include <machine/mtrr.h> 103 #include <machine/pio.h> 104 105 #include <x86/fpu.h> 106 107 #include <xen/xen.h> 108 #include <xen/xen-public/vcpu.h> 109 #include <xen/vcpuvar.h> 110 111 #if NLAPIC > 0 112 #include <machine/apicvar.h> 113 #include <machine/i82489reg.h> 114 #include <machine/i82489var.h> 115 #endif 116 117 #include <dev/ic/mc146818reg.h> 118 #include <dev/isa/isareg.h> 119 120 static int cpu_match(device_t, cfdata_t, void *); 121 static void cpu_attach(device_t, device_t, void *); 122 static void cpu_defer(device_t); 123 static int cpu_rescan(device_t, const char *, const int *); 124 static void cpu_childdetached(device_t, device_t); 125 static int vcpu_match(device_t, cfdata_t, void *); 126 static void vcpu_attach(device_t, device_t, void *); 127 static void cpu_attach_common(device_t, device_t, void *); 128 void cpu_offline_md(void); 129 130 struct cpu_softc { 131 device_t sc_dev; /* device tree glue */ 132 struct cpu_info *sc_info; /* pointer to CPU info */ 133 bool sc_wasonline; 134 }; 135 136 int mp_cpu_start(struct cpu_info *, vaddr_t); 137 void mp_cpu_start_cleanup(struct cpu_info *); 138 const struct cpu_functions mp_cpu_funcs = { mp_cpu_start, NULL, 139 mp_cpu_start_cleanup }; 140 141 CFATTACH_DECL2_NEW(cpu, sizeof(struct cpu_softc), 142 cpu_match, cpu_attach, NULL, NULL, cpu_rescan, cpu_childdetached); 143 144 CFATTACH_DECL_NEW(vcpu, sizeof(struct cpu_softc), 145 vcpu_match, vcpu_attach, NULL, NULL); 146 147 /* 148 * Statically-allocated CPU info for the primary CPU (or the only 149 * CPU, on uniprocessors). The CPU info list is initialized to 150 * point at it. 151 */ 152 struct cpu_info cpu_info_primary __aligned(CACHE_LINE_SIZE) = { 153 .ci_dev = 0, 154 .ci_self = &cpu_info_primary, 155 .ci_idepth = -1, 156 .ci_curlwp = &lwp0, 157 .ci_curldt = -1, 158 }; 159 struct cpu_info phycpu_info_primary __aligned(CACHE_LINE_SIZE) = { 160 .ci_dev = 0, 161 .ci_self = &phycpu_info_primary, 162 }; 163 164 struct cpu_info *cpu_info_list = &cpu_info_primary; 165 struct cpu_info *phycpu_info_list = &phycpu_info_primary; 166 167 uint32_t cpu_feature[7] __read_mostly; /* X86 CPUID feature bits 168 * [0] basic features %edx 169 * [1] basic features %ecx 170 * [2] extended features %edx 171 * [3] extended features %ecx 172 * [4] VIA padlock features 173 * [5] structured extended features cpuid.7:%ebx 174 * [6] structured extended features cpuid.7:%ecx 175 */ 176 177 bool x86_mp_online; 178 paddr_t mp_trampoline_paddr = MP_TRAMPOLINE; 179 180 #if defined(MULTIPROCESSOR) 181 void cpu_hatch(void *); 182 static void cpu_boot_secondary(struct cpu_info *ci); 183 static void cpu_start_secondary(struct cpu_info *ci); 184 #endif /* MULTIPROCESSOR */ 185 186 static int 187 cpu_match(device_t parent, cfdata_t match, void *aux) 188 { 189 190 return 1; 191 } 192 193 static void 194 cpu_attach(device_t parent, device_t self, void *aux) 195 { 196 struct cpu_softc *sc = device_private(self); 197 struct cpu_attach_args *caa = aux; 198 struct cpu_info *ci; 199 uintptr_t ptr; 200 static int nphycpu = 0; 201 202 sc->sc_dev = self; 203 204 /* 205 * If we're an Application Processor, allocate a cpu_info 206 * If we're the first attached CPU use the primary cpu_info, 207 * otherwise allocate a new one 208 */ 209 aprint_naive("\n"); 210 aprint_normal("\n"); 211 if (nphycpu > 0) { 212 struct cpu_info *tmp; 213 ptr = (uintptr_t)kmem_zalloc(sizeof(*ci) + CACHE_LINE_SIZE - 1, 214 KM_SLEEP); 215 ci = (struct cpu_info *)roundup2(ptr, CACHE_LINE_SIZE); 216 ci->ci_curldt = -1; 217 218 tmp = phycpu_info_list; 219 while (tmp->ci_next) 220 tmp = tmp->ci_next; 221 222 tmp->ci_next = ci; 223 } else { 224 ci = &phycpu_info_primary; 225 } 226 227 ci->ci_self = ci; 228 sc->sc_info = ci; 229 230 ci->ci_dev = self; 231 ci->ci_acpiid = caa->cpu_id; 232 ci->ci_cpuid = caa->cpu_number; 233 ci->ci_vcpu = NULL; 234 ci->ci_index = nphycpu++; 235 236 if (!pmf_device_register(self, NULL, NULL)) 237 aprint_error_dev(self, "couldn't establish power handler\n"); 238 239 (void)config_defer(self, cpu_defer); 240 } 241 242 static void 243 cpu_defer(device_t self) 244 { 245 cpu_rescan(self, NULL, NULL); 246 } 247 248 static int 249 cpu_rescan(device_t self, const char *ifattr, const int *locators) 250 { 251 struct cpu_softc *sc = device_private(self); 252 struct cpufeature_attach_args cfaa; 253 struct cpu_info *ci = sc->sc_info; 254 255 memset(&cfaa, 0, sizeof(cfaa)); 256 cfaa.ci = ci; 257 258 if (ifattr_match(ifattr, "cpufeaturebus")) { 259 260 if (ci->ci_frequency == NULL) { 261 cfaa.name = "frequency"; 262 ci->ci_frequency = config_found_ia(self, 263 "cpufeaturebus", &cfaa, NULL); 264 } 265 } 266 267 return 0; 268 } 269 270 static void 271 cpu_childdetached(device_t self, device_t child) 272 { 273 struct cpu_softc *sc = device_private(self); 274 struct cpu_info *ci = sc->sc_info; 275 276 if (ci->ci_frequency == child) 277 ci->ci_frequency = NULL; 278 } 279 280 static int 281 vcpu_match(device_t parent, cfdata_t match, void *aux) 282 { 283 struct vcpu_attach_args *vcaa = aux; 284 struct vcpu_runstate_info vcr; 285 int error; 286 287 if (strcmp(vcaa->vcaa_name, match->cf_name) == 0) { 288 error = HYPERVISOR_vcpu_op(VCPUOP_get_runstate_info, 289 vcaa->vcaa_caa.cpu_number, &vcr); 290 switch (error) { 291 case 0: 292 return 1; 293 case -ENOENT: 294 return 0; 295 default: 296 panic("Unknown hypervisor error %d returned on vcpu runstate probe\n", error); 297 } 298 } 299 300 return 0; 301 } 302 303 static void 304 vcpu_attach(device_t parent, device_t self, void *aux) 305 { 306 struct vcpu_attach_args *vcaa = aux; 307 308 KASSERT(vcaa->vcaa_caa.cpu_func == NULL); 309 vcaa->vcaa_caa.cpu_func = &mp_cpu_funcs; 310 cpu_attach_common(parent, self, &vcaa->vcaa_caa); 311 312 if (!pmf_device_register(self, NULL, NULL)) 313 aprint_error_dev(self, "couldn't establish power handler\n"); 314 } 315 316 static int 317 vcpu_is_up(struct cpu_info *ci) 318 { 319 KASSERT(ci != NULL); 320 return HYPERVISOR_vcpu_op(VCPUOP_is_up, ci->ci_cpuid, NULL); 321 } 322 323 static void 324 cpu_vm_init(struct cpu_info *ci) 325 { 326 int ncolors = 2, i; 327 328 for (i = CAI_ICACHE; i <= CAI_L2CACHE; i++) { 329 struct x86_cache_info *cai; 330 int tcolors; 331 332 cai = &ci->ci_cinfo[i]; 333 334 tcolors = atop(cai->cai_totalsize); 335 switch (cai->cai_associativity) { 336 case 0xff: 337 tcolors = 1; /* fully associative */ 338 break; 339 case 0: 340 case 1: 341 break; 342 default: 343 tcolors /= cai->cai_associativity; 344 } 345 ncolors = max(ncolors, tcolors); 346 } 347 348 /* 349 * Knowing the size of the largest cache on this CPU, potentially 350 * re-color our pages. 351 */ 352 aprint_debug_dev(ci->ci_dev, "%d page colors\n", ncolors); 353 uvm_page_recolor(ncolors); 354 pmap_tlb_cpu_init(ci); 355 #ifndef __HAVE_DIRECT_MAP 356 pmap_vpage_cpu_init(ci); 357 #endif 358 } 359 360 static void 361 cpu_attach_common(device_t parent, device_t self, void *aux) 362 { 363 struct cpu_softc *sc = device_private(self); 364 struct cpu_attach_args *caa = aux; 365 struct cpu_info *ci; 366 uintptr_t ptr; 367 int cpunum = caa->cpu_number; 368 static bool again = false; 369 370 sc->sc_dev = self; 371 372 /* 373 * If we're an Application Processor, allocate a cpu_info 374 * structure, otherwise use the primary's. 375 */ 376 if (caa->cpu_role == CPU_ROLE_AP) { 377 aprint_naive(": Application Processor\n"); 378 ptr = (uintptr_t)kmem_alloc(sizeof(*ci) + CACHE_LINE_SIZE - 1, 379 KM_SLEEP); 380 ci = (struct cpu_info *)roundup2(ptr, CACHE_LINE_SIZE); 381 memset(ci, 0, sizeof(*ci)); 382 cpu_init_tss(ci); 383 } else { 384 aprint_naive(": %s Processor\n", 385 caa->cpu_role == CPU_ROLE_SP ? "Single" : "Boot"); 386 ci = &cpu_info_primary; 387 } 388 389 ci->ci_self = ci; 390 sc->sc_info = ci; 391 ci->ci_dev = self; 392 ci->ci_cpuid = cpunum; 393 394 KASSERT(HYPERVISOR_shared_info != NULL); 395 KASSERT(cpunum < XEN_LEGACY_MAX_VCPUS); 396 ci->ci_vcpu = &HYPERVISOR_shared_info->vcpu_info[cpunum]; 397 398 KASSERT(ci->ci_func == 0); 399 ci->ci_func = caa->cpu_func; 400 aprint_normal("\n"); 401 402 /* Must be called before mi_cpu_attach(). */ 403 cpu_vm_init(ci); 404 405 if (caa->cpu_role == CPU_ROLE_AP) { 406 int error; 407 408 error = mi_cpu_attach(ci); 409 410 KASSERT(ci->ci_data.cpu_idlelwp != NULL); 411 if (error != 0) { 412 aprint_error_dev(self, 413 "mi_cpu_attach failed with %d\n", error); 414 return; 415 } 416 417 } else { 418 KASSERT(ci->ci_data.cpu_idlelwp != NULL); 419 } 420 421 KASSERT(ci->ci_cpuid == ci->ci_index); 422 #ifdef __x86_64__ 423 /* No user PGD mapped for this CPU yet */ 424 ci->ci_xen_current_user_pgd = 0; 425 #endif 426 #if defined(__x86_64__) || defined(PAE) 427 mutex_init(&ci->ci_kpm_mtx, MUTEX_DEFAULT, IPL_VM); 428 #endif 429 pmap_reference(pmap_kernel()); 430 ci->ci_pmap = pmap_kernel(); 431 ci->ci_tlbstate = TLBSTATE_STALE; 432 433 /* 434 * Boot processor may not be attached first, but the below 435 * must be done to allow booting other processors. 436 */ 437 if (!again) { 438 atomic_or_32(&ci->ci_flags, CPUF_PRESENT | CPUF_PRIMARY); 439 /* Basic init. */ 440 cpu_intr_init(ci); 441 cpu_get_tsc_freq(ci); 442 cpu_init(ci); 443 pmap_cpu_init_late(ci); 444 445 /* Every processor needs to init its own ipi h/w (similar to lapic) */ 446 xen_ipi_init(); 447 448 /* Make sure DELAY() is initialized. */ 449 DELAY(1); 450 again = true; 451 } 452 453 /* further PCB init done later. */ 454 455 switch (caa->cpu_role) { 456 case CPU_ROLE_SP: 457 atomic_or_32(&ci->ci_flags, CPUF_SP); 458 cpu_identify(ci); 459 x86_cpu_idle_init(); 460 break; 461 462 case CPU_ROLE_BP: 463 atomic_or_32(&ci->ci_flags, CPUF_BSP); 464 cpu_identify(ci); 465 x86_cpu_idle_init(); 466 break; 467 468 case CPU_ROLE_AP: 469 atomic_or_32(&ci->ci_flags, CPUF_AP); 470 471 /* 472 * report on an AP 473 */ 474 475 #if defined(MULTIPROCESSOR) 476 /* interrupt handler stack */ 477 cpu_intr_init(ci); 478 479 /* Setup per-cpu memory for gdt */ 480 gdt_alloc_cpu(ci); 481 482 pmap_cpu_init_late(ci); 483 cpu_start_secondary(ci); 484 485 if (ci->ci_flags & CPUF_PRESENT) { 486 struct cpu_info *tmp; 487 488 cpu_identify(ci); 489 tmp = cpu_info_list; 490 while (tmp->ci_next) 491 tmp = tmp->ci_next; 492 493 tmp->ci_next = ci; 494 } 495 #else 496 aprint_error_dev(ci->ci_dev, "not started\n"); 497 #endif 498 break; 499 500 default: 501 panic("unknown processor type??\n"); 502 } 503 504 #ifdef MPVERBOSE 505 if (mp_verbose) { 506 struct lwp *l = ci->ci_data.cpu_idlelwp; 507 struct pcb *pcb = lwp_getpcb(l); 508 509 aprint_verbose_dev(self, 510 "idle lwp at %p, idle sp at 0x%p\n", 511 l, 512 #ifdef i386 513 (void *)pcb->pcb_esp 514 #else 515 (void *)pcb->pcb_rsp 516 #endif 517 ); 518 519 } 520 #endif /* MPVERBOSE */ 521 } 522 523 /* 524 * Initialize the processor appropriately. 525 */ 526 527 void 528 cpu_init(struct cpu_info *ci) 529 { 530 uint32_t cr4 = 0; 531 532 /* 533 * If we have FXSAVE/FXRESTOR, use them. 534 */ 535 if (cpu_feature[0] & CPUID_FXSR) { 536 cr4 |= CR4_OSFXSR; 537 538 /* 539 * If we have SSE/SSE2, enable XMM exceptions. 540 */ 541 if (cpu_feature[0] & (CPUID_SSE|CPUID_SSE2)) 542 cr4 |= CR4_OSXMMEXCPT; 543 } 544 545 /* If xsave is supported, enable it */ 546 if (cpu_feature[1] & CPUID2_XSAVE && x86_fpu_save >= FPU_SAVE_XSAVE) 547 cr4 |= CR4_OSXSAVE; 548 549 if (cr4) { 550 cr4 |= rcr4(); 551 lcr4(cr4); 552 } 553 554 if (x86_fpu_save >= FPU_SAVE_FXSAVE) { 555 fpuinit_mxcsr_mask(); 556 } 557 558 /* 559 * Changing CR4 register may change cpuid values. For example, setting 560 * CR4_OSXSAVE sets CPUID2_OSXSAVE. The CPUID2_OSXSAVE is in 561 * ci_feat_val[1], so update it. 562 * XXX Other than ci_feat_val[1] might be changed. 563 */ 564 if (cpuid_level >= 1) { 565 u_int descs[4]; 566 567 x86_cpuid(1, descs); 568 ci->ci_feat_val[1] = descs[2]; 569 } 570 571 /* If xsave is enabled, enable all fpu features */ 572 if (cr4 & CR4_OSXSAVE) { 573 wrxcr(0, x86_xsave_features & XCR0_FPU); 574 } 575 576 atomic_or_32(&ci->ci_flags, CPUF_RUNNING); 577 } 578 579 580 #ifdef MULTIPROCESSOR 581 582 void 583 cpu_boot_secondary_processors(void) 584 { 585 struct cpu_info *ci; 586 u_long i; 587 for (i = 0; i < maxcpus; i++) { 588 ci = cpu_lookup(i); 589 if (ci == NULL) 590 continue; 591 if (ci->ci_data.cpu_idlelwp == NULL) 592 continue; 593 if ((ci->ci_flags & CPUF_PRESENT) == 0) 594 continue; 595 if (ci->ci_flags & (CPUF_BSP|CPUF_SP|CPUF_PRIMARY)) 596 continue; 597 cpu_boot_secondary(ci); 598 } 599 600 x86_mp_online = true; 601 } 602 603 static void 604 cpu_init_idle_lwp(struct cpu_info *ci) 605 { 606 struct lwp *l = ci->ci_data.cpu_idlelwp; 607 struct pcb *pcb = lwp_getpcb(l); 608 609 pcb->pcb_cr0 = rcr0(); 610 } 611 612 void 613 cpu_init_idle_lwps(void) 614 { 615 struct cpu_info *ci; 616 u_long i; 617 618 for (i = 0; i < maxcpus; i++) { 619 ci = cpu_lookup(i); 620 if (ci == NULL) 621 continue; 622 if (ci->ci_data.cpu_idlelwp == NULL) 623 continue; 624 if ((ci->ci_flags & CPUF_PRESENT) == 0) 625 continue; 626 cpu_init_idle_lwp(ci); 627 } 628 } 629 630 static void 631 cpu_start_secondary(struct cpu_info *ci) 632 { 633 int i; 634 635 aprint_debug_dev(ci->ci_dev, "starting\n"); 636 637 ci->ci_curlwp = ci->ci_data.cpu_idlelwp; 638 639 if (CPU_STARTUP(ci, (vaddr_t) cpu_hatch) != 0) { 640 return; 641 } 642 643 /* 644 * wait for it to become ready 645 */ 646 for (i = 100000; (!(ci->ci_flags & CPUF_PRESENT)) && i > 0; i--) { 647 delay(10); 648 } 649 if ((ci->ci_flags & CPUF_PRESENT) == 0) { 650 aprint_error_dev(ci->ci_dev, "failed to become ready\n"); 651 #if defined(MPDEBUG) && defined(DDB) 652 printf("dropping into debugger; continue from here to resume boot\n"); 653 Debugger(); 654 #endif 655 } 656 657 CPU_START_CLEANUP(ci); 658 } 659 660 void 661 cpu_boot_secondary(struct cpu_info *ci) 662 { 663 int i; 664 atomic_or_32(&ci->ci_flags, CPUF_GO); 665 for (i = 100000; (!(ci->ci_flags & CPUF_RUNNING)) && i > 0; i--) { 666 delay(10); 667 } 668 if ((ci->ci_flags & CPUF_RUNNING) == 0) { 669 aprint_error_dev(ci->ci_dev, "CPU failed to start\n"); 670 #if defined(MPDEBUG) && defined(DDB) 671 printf("dropping into debugger; continue from here to resume boot\n"); 672 Debugger(); 673 #endif 674 } 675 } 676 677 /* 678 * APs end up here immediately after initialisation and VCPUOP_up in 679 * mp_cpu_start(). 680 * At this point, we are running in the idle pcb/idle stack of the new 681 * CPU. This function jumps to the idle loop and starts looking for 682 * work. 683 */ 684 extern void x86_64_tls_switch(struct lwp *); 685 void 686 cpu_hatch(void *v) 687 { 688 struct cpu_info *ci = (struct cpu_info *)v; 689 struct pcb *pcb; 690 int s, i; 691 692 /* Setup TLS and kernel GS/FS */ 693 cpu_init_msrs(ci, true); 694 cpu_init_idt(); 695 gdt_init_cpu(ci); 696 697 cpu_probe(ci); 698 699 atomic_or_32(&ci->ci_flags, CPUF_PRESENT); 700 701 while ((ci->ci_flags & CPUF_GO) == 0) { 702 /* Don't use delay, boot CPU may be patching the text. */ 703 for (i = 10000; i != 0; i--) 704 x86_pause(); 705 } 706 707 /* Because the text may have been patched in x86_patch(). */ 708 x86_flush(); 709 tlbflushg(); 710 711 KASSERT((ci->ci_flags & CPUF_RUNNING) == 0); 712 713 pcb = lwp_getpcb(curlwp); 714 pcb->pcb_cr3 = pmap_pdirpa(pmap_kernel(), 0); 715 pcb = lwp_getpcb(ci->ci_data.cpu_idlelwp); 716 717 xen_ipi_init(); 718 719 xen_initclocks(); 720 721 #ifdef __x86_64__ 722 fpuinit(ci); 723 #endif 724 725 lldt(GSEL(GLDT_SEL, SEL_KPL)); 726 727 cpu_init(ci); 728 cpu_get_tsc_freq(ci); 729 730 s = splhigh(); 731 x86_enable_intr(); 732 splx(s); 733 734 aprint_debug_dev(ci->ci_dev, "running\n"); 735 736 cpu_switchto(NULL, ci->ci_data.cpu_idlelwp, true); 737 738 idle_loop(NULL); 739 KASSERT(false); 740 } 741 742 #if defined(DDB) 743 744 #include <ddb/db_output.h> 745 #include <machine/db_machdep.h> 746 747 /* 748 * Dump CPU information from ddb. 749 */ 750 void 751 cpu_debug_dump(void) 752 { 753 struct cpu_info *ci; 754 CPU_INFO_ITERATOR cii; 755 756 db_printf("addr dev id flags ipis curlwp fpcurlwp\n"); 757 for (CPU_INFO_FOREACH(cii, ci)) { 758 db_printf("%p %s %ld %x %x %10p %10p\n", 759 ci, 760 ci->ci_dev == NULL ? "BOOT" : device_xname(ci->ci_dev), 761 (long)ci->ci_cpuid, 762 ci->ci_flags, ci->ci_ipis, 763 ci->ci_curlwp, 764 ci->ci_fpcurlwp); 765 } 766 } 767 #endif /* DDB */ 768 769 #endif /* MULTIPROCESSOR */ 770 771 extern void hypervisor_callback(void); 772 extern void failsafe_callback(void); 773 #ifdef __x86_64__ 774 typedef void (vector)(void); 775 extern vector Xsyscall, Xsyscall32; 776 #endif 777 778 /* 779 * Setup the "trampoline". On Xen, we setup nearly all cpu context 780 * outside a trampoline, so we prototype and call targetip like so: 781 * void targetip(struct cpu_info *); 782 */ 783 784 static void 785 gdt_prepframes(paddr_t *frames, vaddr_t base, uint32_t entries) 786 { 787 int i; 788 for (i = 0; i < entries; i++) { 789 frames[i] = ((paddr_t)xpmap_ptetomach( 790 (pt_entry_t *)(base + (i << PAGE_SHIFT)))) >> PAGE_SHIFT; 791 792 /* Mark Read-only */ 793 pmap_pte_clearbits(kvtopte(base + (i << PAGE_SHIFT)), 794 PG_RW); 795 } 796 } 797 798 #ifdef __x86_64__ 799 extern char *ldtstore; 800 801 static void 802 xen_init_amd64_vcpuctxt(struct cpu_info *ci, struct vcpu_guest_context *initctx, 803 void targetrip(struct cpu_info *)) 804 { 805 /* page frames to point at GDT */ 806 extern int gdt_size; 807 paddr_t frames[16]; 808 psize_t gdt_ents; 809 810 struct lwp *l; 811 struct pcb *pcb; 812 813 volatile struct vcpu_info *vci; 814 815 KASSERT(ci != NULL); 816 KASSERT(ci != &cpu_info_primary); 817 KASSERT(initctx != NULL); 818 KASSERT(targetrip != NULL); 819 820 memset(initctx, 0, sizeof(*initctx)); 821 822 gdt_ents = roundup(gdt_size, PAGE_SIZE) >> PAGE_SHIFT; 823 KASSERT(gdt_ents <= 16); 824 825 gdt_prepframes(frames, (vaddr_t)ci->ci_gdt, gdt_ents); 826 827 /* Initialise the vcpu context: We use idle_loop()'s pcb context. */ 828 829 l = ci->ci_data.cpu_idlelwp; 830 831 KASSERT(l != NULL); 832 pcb = lwp_getpcb(l); 833 KASSERT(pcb != NULL); 834 835 /* resume with interrupts off */ 836 vci = ci->ci_vcpu; 837 vci->evtchn_upcall_mask = 1; 838 xen_mb(); 839 840 /* resume in kernel-mode */ 841 initctx->flags = VGCF_in_kernel | VGCF_online; 842 843 /* Stack and entry points: 844 * We arrange for the stack frame for cpu_hatch() to 845 * appear as a callee frame of lwp_trampoline(). Being a 846 * leaf frame prevents trampling on any of the MD stack setup 847 * that x86/vm_machdep.c:cpu_lwp_fork() does for idle_loop() 848 */ 849 850 initctx->user_regs.rdi = (uint64_t) ci; /* targetrip(ci); */ 851 initctx->user_regs.rip = (vaddr_t) targetrip; 852 853 initctx->user_regs.cs = GSEL(GCODE_SEL, SEL_KPL); 854 855 initctx->user_regs.rflags = pcb->pcb_flags; 856 initctx->user_regs.rsp = pcb->pcb_rsp; 857 858 /* Data segments */ 859 initctx->user_regs.ss = GSEL(GDATA_SEL, SEL_KPL); 860 initctx->user_regs.es = GSEL(GDATA_SEL, SEL_KPL); 861 initctx->user_regs.ds = GSEL(GDATA_SEL, SEL_KPL); 862 863 /* GDT */ 864 memcpy(initctx->gdt_frames, frames, sizeof(frames)); 865 initctx->gdt_ents = gdt_ents; 866 867 /* LDT */ 868 initctx->ldt_base = (unsigned long)ldtstore; 869 initctx->ldt_ents = LDT_SIZE >> 3; 870 871 /* Kernel context state */ 872 initctx->kernel_ss = GSEL(GDATA_SEL, SEL_KPL); 873 initctx->kernel_sp = pcb->pcb_rsp0; 874 initctx->ctrlreg[0] = pcb->pcb_cr0; 875 initctx->ctrlreg[1] = 0; /* "resuming" from kernel - no User cr3. */ 876 initctx->ctrlreg[2] = (vaddr_t)targetrip; 877 /* 878 * Use pmap_kernel() L4 PD directly, until we setup the 879 * per-cpu L4 PD in pmap_cpu_init_late() 880 */ 881 initctx->ctrlreg[3] = xen_pfn_to_cr3(x86_btop(xpmap_ptom(ci->ci_kpm_pdirpa))); 882 initctx->ctrlreg[4] = CR4_PAE | CR4_OSFXSR | CR4_OSXMMEXCPT; 883 884 /* Xen callbacks */ 885 initctx->event_callback_eip = (unsigned long)hypervisor_callback; 886 initctx->failsafe_callback_eip = (unsigned long)failsafe_callback; 887 initctx->syscall_callback_eip = (unsigned long)Xsyscall; 888 889 return; 890 } 891 #else /* i386 */ 892 extern union descriptor *ldtstore; 893 extern void Xsyscall(void); 894 895 static void 896 xen_init_i386_vcpuctxt(struct cpu_info *ci, struct vcpu_guest_context *initctx, 897 void targeteip(struct cpu_info *)) 898 { 899 /* page frames to point at GDT */ 900 extern int gdt_size; 901 paddr_t frames[16]; 902 psize_t gdt_ents; 903 904 struct lwp *l; 905 struct pcb *pcb; 906 907 volatile struct vcpu_info *vci; 908 909 KASSERT(ci != NULL); 910 KASSERT(ci != &cpu_info_primary); 911 KASSERT(initctx != NULL); 912 KASSERT(targeteip != NULL); 913 914 memset(initctx, 0, sizeof(*initctx)); 915 916 gdt_ents = roundup(gdt_size, PAGE_SIZE) >> PAGE_SHIFT; 917 KASSERT(gdt_ents <= 16); 918 919 gdt_prepframes(frames, (vaddr_t)ci->ci_gdt, gdt_ents); 920 921 /* 922 * Initialise the vcpu context: 923 * We use this cpu's idle_loop() pcb context. 924 */ 925 926 l = ci->ci_data.cpu_idlelwp; 927 928 KASSERT(l != NULL); 929 pcb = lwp_getpcb(l); 930 KASSERT(pcb != NULL); 931 932 /* resume with interrupts off */ 933 vci = ci->ci_vcpu; 934 vci->evtchn_upcall_mask = 1; 935 xen_mb(); 936 937 /* resume in kernel-mode */ 938 initctx->flags = VGCF_in_kernel | VGCF_online; 939 940 /* Stack frame setup for cpu_hatch(): 941 * We arrange for the stack frame for cpu_hatch() to 942 * appear as a callee frame of lwp_trampoline(). Being a 943 * leaf frame prevents trampling on any of the MD stack setup 944 * that x86/vm_machdep.c:cpu_lwp_fork() does for idle_loop() 945 */ 946 947 initctx->user_regs.esp = pcb->pcb_esp - 4; /* Leave word for 948 arg1 */ 949 { 950 /* targeteip(ci); */ 951 uint32_t *arg = (uint32_t *)initctx->user_regs.esp; 952 arg[1] = (uint32_t)ci; /* arg1 */ 953 } 954 955 initctx->user_regs.eip = (vaddr_t)targeteip; 956 initctx->user_regs.cs = GSEL(GCODE_SEL, SEL_KPL); 957 initctx->user_regs.eflags |= pcb->pcb_iopl; 958 959 /* Data segments */ 960 initctx->user_regs.ss = GSEL(GDATA_SEL, SEL_KPL); 961 initctx->user_regs.es = GSEL(GDATA_SEL, SEL_KPL); 962 initctx->user_regs.ds = GSEL(GDATA_SEL, SEL_KPL); 963 initctx->user_regs.fs = GSEL(GDATA_SEL, SEL_KPL); 964 965 /* GDT */ 966 memcpy(initctx->gdt_frames, frames, sizeof(frames)); 967 initctx->gdt_ents = gdt_ents; 968 969 /* LDT */ 970 initctx->ldt_base = (unsigned long)ldtstore; 971 initctx->ldt_ents = NLDT; 972 973 /* Kernel context state */ 974 initctx->kernel_ss = GSEL(GDATA_SEL, SEL_KPL); 975 initctx->kernel_sp = pcb->pcb_esp0; 976 initctx->ctrlreg[0] = pcb->pcb_cr0; 977 initctx->ctrlreg[1] = 0; /* "resuming" from kernel - no User cr3. */ 978 initctx->ctrlreg[2] = (vaddr_t)targeteip; 979 #ifdef PAE 980 initctx->ctrlreg[3] = xen_pfn_to_cr3(x86_btop(xpmap_ptom(ci->ci_pae_l3_pdirpa))); 981 #else 982 initctx->ctrlreg[3] = xen_pfn_to_cr3(x86_btop(xpmap_ptom(pcb->pcb_cr3))); 983 #endif 984 initctx->ctrlreg[4] = /* CR4_PAE | */CR4_OSFXSR | CR4_OSXMMEXCPT; 985 986 /* Xen callbacks */ 987 initctx->event_callback_eip = (unsigned long)hypervisor_callback; 988 initctx->event_callback_cs = GSEL(GCODE_SEL, SEL_KPL); 989 initctx->failsafe_callback_eip = (unsigned long)failsafe_callback; 990 initctx->failsafe_callback_cs = GSEL(GCODE_SEL, SEL_KPL); 991 992 return; 993 } 994 #endif /* __x86_64__ */ 995 996 int 997 mp_cpu_start(struct cpu_info *ci, vaddr_t target) 998 { 999 int hyperror; 1000 struct vcpu_guest_context vcpuctx; 1001 1002 KASSERT(ci != NULL); 1003 KASSERT(ci != &cpu_info_primary); 1004 KASSERT(ci->ci_flags & CPUF_AP); 1005 1006 #ifdef __x86_64__ 1007 xen_init_amd64_vcpuctxt(ci, &vcpuctx, (void (*)(struct cpu_info *))target); 1008 #else 1009 xen_init_i386_vcpuctxt(ci, &vcpuctx, (void (*)(struct cpu_info *))target); 1010 #endif 1011 1012 /* Initialise the given vcpu to execute cpu_hatch(ci); */ 1013 if ((hyperror = HYPERVISOR_vcpu_op(VCPUOP_initialise, ci->ci_cpuid, &vcpuctx))) { 1014 aprint_error(": context initialisation failed. errno = %d\n", hyperror); 1015 return hyperror; 1016 } 1017 1018 /* Start it up */ 1019 1020 /* First bring it down */ 1021 if ((hyperror = HYPERVISOR_vcpu_op(VCPUOP_down, ci->ci_cpuid, NULL))) { 1022 aprint_error(": VCPUOP_down hypervisor command failed. errno = %d\n", hyperror); 1023 return hyperror; 1024 } 1025 1026 if ((hyperror = HYPERVISOR_vcpu_op(VCPUOP_up, ci->ci_cpuid, NULL))) { 1027 aprint_error(": VCPUOP_up hypervisor command failed. errno = %d\n", hyperror); 1028 return hyperror; 1029 } 1030 1031 if (!vcpu_is_up(ci)) { 1032 aprint_error(": did not come up\n"); 1033 return -1; 1034 } 1035 1036 return 0; 1037 } 1038 1039 void 1040 mp_cpu_start_cleanup(struct cpu_info *ci) 1041 { 1042 if (vcpu_is_up(ci)) { 1043 aprint_debug_dev(ci->ci_dev, "is started.\n"); 1044 } else { 1045 aprint_error_dev(ci->ci_dev, "did not start up.\n"); 1046 } 1047 } 1048 1049 void 1050 cpu_init_msrs(struct cpu_info *ci, bool full) 1051 { 1052 #ifdef __x86_64__ 1053 if (full) { 1054 HYPERVISOR_set_segment_base(SEGBASE_FS, 0); 1055 HYPERVISOR_set_segment_base(SEGBASE_GS_KERNEL, (uint64_t)ci); 1056 HYPERVISOR_set_segment_base(SEGBASE_GS_USER, 0); 1057 } 1058 #endif 1059 1060 if (cpu_feature[2] & CPUID_NOX) 1061 wrmsr(MSR_EFER, rdmsr(MSR_EFER) | EFER_NXE); 1062 } 1063 1064 void 1065 cpu_offline_md(void) 1066 { 1067 int s; 1068 1069 s = splhigh(); 1070 fpusave_cpu(true); 1071 splx(s); 1072 } 1073 1074 void 1075 cpu_get_tsc_freq(struct cpu_info *ci) 1076 { 1077 uint32_t vcpu_tversion; 1078 const volatile vcpu_time_info_t *tinfo = &ci->ci_vcpu->time; 1079 1080 vcpu_tversion = tinfo->version; 1081 while (tinfo->version == vcpu_tversion); /* Wait for a time update. XXX: timeout ? */ 1082 1083 uint64_t freq = 1000000000ULL << 32; 1084 freq = freq / (uint64_t)tinfo->tsc_to_system_mul; 1085 if (tinfo->tsc_shift < 0) 1086 freq = freq << -tinfo->tsc_shift; 1087 else 1088 freq = freq >> tinfo->tsc_shift; 1089 ci->ci_data.cpu_cc_freq = freq; 1090 } 1091 1092 void 1093 x86_cpu_idle_xen(void) 1094 { 1095 struct cpu_info *ci = curcpu(); 1096 1097 KASSERT(ci->ci_ilevel == IPL_NONE); 1098 1099 x86_disable_intr(); 1100 if (!__predict_false(ci->ci_want_resched)) { 1101 idle_block(); 1102 } else { 1103 x86_enable_intr(); 1104 } 1105 } 1106 1107 /* 1108 * Loads pmap for the current CPU. 1109 */ 1110 void 1111 cpu_load_pmap(struct pmap *pmap, struct pmap *oldpmap) 1112 { 1113 KASSERT(pmap != pmap_kernel()); 1114 1115 #if defined(__x86_64__) || defined(PAE) 1116 struct cpu_info *ci = curcpu(); 1117 cpuid_t cid = cpu_index(ci); 1118 1119 mutex_enter(&ci->ci_kpm_mtx); 1120 /* make new pmap visible to xen_kpm_sync() */ 1121 kcpuset_atomic_set(pmap->pm_xen_ptp_cpus, cid); 1122 #endif 1123 1124 #ifdef i386 1125 #ifdef PAE 1126 { 1127 int i; 1128 paddr_t l3_pd = xpmap_ptom_masked(ci->ci_pae_l3_pdirpa); 1129 /* don't update the kernel L3 slot */ 1130 for (i = 0 ; i < PDP_SIZE - 1; i++) { 1131 xpq_queue_pte_update(l3_pd + i * sizeof(pd_entry_t), 1132 xpmap_ptom(pmap->pm_pdirpa[i]) | PG_V); 1133 } 1134 tlbflush(); 1135 } 1136 #else /* PAE */ 1137 lcr3(pmap_pdirpa(pmap, 0)); 1138 #endif /* PAE */ 1139 #endif /* i386 */ 1140 1141 #ifdef __x86_64__ 1142 { 1143 int i; 1144 pd_entry_t *new_pgd; 1145 paddr_t l4_pd_ma; 1146 1147 l4_pd_ma = xpmap_ptom_masked(ci->ci_kpm_pdirpa); 1148 1149 /* 1150 * Map user space address in kernel space and load 1151 * user cr3 1152 */ 1153 new_pgd = pmap->pm_pdir; 1154 KASSERT(pmap == ci->ci_pmap); 1155 1156 /* Copy user pmap L4 PDEs (in user addr. range) to per-cpu L4 */ 1157 for (i = 0; i < PDIR_SLOT_PTE; i++) { 1158 KASSERT(pmap != pmap_kernel() || new_pgd[i] == 0); 1159 if (ci->ci_kpm_pdir[i] != new_pgd[i]) { 1160 xpq_queue_pte_update( 1161 l4_pd_ma + i * sizeof(pd_entry_t), 1162 new_pgd[i]); 1163 } 1164 } 1165 1166 xen_set_user_pgd(pmap_pdirpa(pmap, 0)); 1167 ci->ci_xen_current_user_pgd = pmap_pdirpa(pmap, 0); 1168 1169 tlbflush(); 1170 } 1171 #endif /* __x86_64__ */ 1172 1173 #if defined(__x86_64__) || defined(PAE) 1174 /* old pmap no longer visible to xen_kpm_sync() */ 1175 if (oldpmap != pmap_kernel()) { 1176 kcpuset_atomic_clear(oldpmap->pm_xen_ptp_cpus, cid); 1177 } 1178 mutex_exit(&ci->ci_kpm_mtx); 1179 #endif 1180 } 1181 1182 /* 1183 * pmap_cpu_init_late: perform late per-CPU initialization. 1184 * 1185 * Short note about percpu PDIR pages. Both the PAE and __x86_64__ architectures 1186 * have per-cpu PDIR tables, for two different reasons: 1187 * - on PAE, this is to get around Xen's pagetable setup constraints (multiple 1188 * L3[3]s cannot point to the same L2 - Xen will refuse to pin a table set up 1189 * this way). 1190 * - on __x86_64__, this is for multiple CPUs to map in different user pmaps 1191 * (see cpu_load_pmap()). 1192 * 1193 * What this means for us is that the PDIR of the pmap_kernel() is considered 1194 * to be a canonical "SHADOW" PDIR with the following properties: 1195 * - its recursive mapping points to itself 1196 * - per-cpu recursive mappings point to themselves on __x86_64__ 1197 * - per-cpu L4 pages' kernel entries are expected to be in sync with 1198 * the shadow 1199 */ 1200 1201 void 1202 pmap_cpu_init_late(struct cpu_info *ci) 1203 { 1204 #if defined(PAE) || defined(__x86_64__) 1205 /* 1206 * The BP has already its own PD page allocated during early 1207 * MD startup. 1208 */ 1209 1210 #if defined(__x86_64__) 1211 /* Setup per-cpu normal_pdes */ 1212 int i; 1213 extern pd_entry_t * const normal_pdes[]; 1214 for (i = 0;i < PTP_LEVELS - 1;i++) { 1215 ci->ci_normal_pdes[i] = normal_pdes[i]; 1216 } 1217 #endif /* __x86_64__ */ 1218 1219 if (ci == &cpu_info_primary) 1220 return; 1221 1222 KASSERT(ci != NULL); 1223 1224 #if defined(PAE) 1225 cpu_alloc_l3_page(ci); 1226 KASSERT(ci->ci_pae_l3_pdirpa != 0); 1227 1228 /* Initialise L2 entries 0 - 2: Point them to pmap_kernel() */ 1229 int i; 1230 for (i = 0 ; i < PDP_SIZE - 1; i++) { 1231 ci->ci_pae_l3_pdir[i] = 1232 xpmap_ptom_masked(pmap_kernel()->pm_pdirpa[i]) | PG_V; 1233 } 1234 #endif /* PAE */ 1235 1236 ci->ci_kpm_pdir = (pd_entry_t *)uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 1237 UVM_KMF_WIRED | UVM_KMF_ZERO | UVM_KMF_NOWAIT); 1238 1239 if (ci->ci_kpm_pdir == NULL) { 1240 panic("%s: failed to allocate L4 per-cpu PD for CPU %d\n", 1241 __func__, cpu_index(ci)); 1242 } 1243 ci->ci_kpm_pdirpa = vtophys((vaddr_t)ci->ci_kpm_pdir); 1244 KASSERT(ci->ci_kpm_pdirpa != 0); 1245 1246 #if defined(__x86_64__) 1247 extern pt_entry_t xpmap_pg_nx; 1248 1249 /* Copy over the pmap_kernel() shadow L4 entries */ 1250 memcpy(ci->ci_kpm_pdir, pmap_kernel()->pm_pdir, PAGE_SIZE); 1251 1252 /* Recursive kernel mapping */ 1253 ci->ci_kpm_pdir[PDIR_SLOT_PTE] = xpmap_ptom_masked(ci->ci_kpm_pdirpa) 1254 | PG_V | xpmap_pg_nx; 1255 #elif defined(PAE) 1256 /* Copy over the pmap_kernel() shadow L2 entries */ 1257 memcpy(ci->ci_kpm_pdir, pmap_kernel()->pm_pdir + PDIR_SLOT_KERN, 1258 nkptp[PTP_LEVELS - 1] * sizeof(pd_entry_t)); 1259 #endif 1260 1261 /* Xen wants a RO pdir. */ 1262 pmap_protect(pmap_kernel(), (vaddr_t)ci->ci_kpm_pdir, 1263 (vaddr_t)ci->ci_kpm_pdir + PAGE_SIZE, VM_PROT_READ); 1264 pmap_update(pmap_kernel()); 1265 #if defined(PAE) 1266 /* 1267 * Initialize L3 entry 3. This mapping is shared across all pmaps and is 1268 * static, ie: loading a new pmap will not update this entry. 1269 */ 1270 ci->ci_pae_l3_pdir[3] = xpmap_ptom_masked(ci->ci_kpm_pdirpa) | PG_V; 1271 1272 /* Xen wants a RO L3. */ 1273 pmap_protect(pmap_kernel(), (vaddr_t)ci->ci_pae_l3_pdir, 1274 (vaddr_t)ci->ci_pae_l3_pdir + PAGE_SIZE, VM_PROT_READ); 1275 pmap_update(pmap_kernel()); 1276 1277 xpq_queue_pin_l3_table(xpmap_ptom_masked(ci->ci_pae_l3_pdirpa)); 1278 1279 #elif defined(__x86_64__) 1280 xpq_queue_pin_l4_table(xpmap_ptom_masked(ci->ci_kpm_pdirpa)); 1281 #endif /* PAE , __x86_64__ */ 1282 #endif /* defined(PAE) || defined(__x86_64__) */ 1283 } 1284 1285 /* 1286 * Notify all other cpus to halt. 1287 */ 1288 1289 void 1290 cpu_broadcast_halt(void) 1291 { 1292 xen_broadcast_ipi(XEN_IPI_HALT); 1293 } 1294 1295 /* 1296 * Send a dummy ipi to a cpu. 1297 */ 1298 1299 void 1300 cpu_kick(struct cpu_info *ci) 1301 { 1302 (void)xen_send_ipi(ci, XEN_IPI_KICK); 1303 } 1304