1 /* $NetBSD: cpu.c,v 1.105 2016/11/25 12:20:03 maxv Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 The NetBSD Foundation, Inc. 5 * Copyright (c) 2002, 2006, 2007 YAMAMOTO Takashi, 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by RedBack Networks Inc. 10 * 11 * Author: Bill Sommerfeld 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 23 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 24 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 25 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 * POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* 36 * Copyright (c) 1999 Stefan Grefen 37 * 38 * Redistribution and use in source and binary forms, with or without 39 * modification, are permitted provided that the following conditions 40 * are met: 41 * 1. Redistributions of source code must retain the above copyright 42 * notice, this list of conditions and the following disclaimer. 43 * 2. Redistributions in binary form must reproduce the above copyright 44 * notice, this list of conditions and the following disclaimer in the 45 * documentation and/or other materials provided with the distribution. 46 * 3. All advertising materials mentioning features or use of this software 47 * must display the following acknowledgement: 48 * This product includes software developed by the NetBSD 49 * Foundation, Inc. and its contributors. 50 * 4. Neither the name of The NetBSD Foundation nor the names of its 51 * contributors may be used to endorse or promote products derived 52 * from this software without specific prior written permission. 53 * 54 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY 55 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 56 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 57 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR AND CONTRIBUTORS BE LIABLE 58 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 59 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 60 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 61 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 62 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 63 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 64 * SUCH DAMAGE. 65 */ 66 67 #include <sys/cdefs.h> 68 __KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.105 2016/11/25 12:20:03 maxv Exp $"); 69 70 #include "opt_ddb.h" 71 #include "opt_multiprocessor.h" 72 #include "opt_mpbios.h" /* for MPDEBUG */ 73 #include "opt_mtrr.h" 74 #include "opt_xen.h" 75 76 #include "lapic.h" 77 #include "ioapic.h" 78 79 #include <sys/param.h> 80 #include <sys/proc.h> 81 #include <sys/systm.h> 82 #include <sys/device.h> 83 #include <sys/kmem.h> 84 #include <sys/cpu.h> 85 #include <sys/cpufreq.h> 86 #include <sys/atomic.h> 87 #include <sys/reboot.h> 88 #include <sys/idle.h> 89 90 #include <uvm/uvm.h> 91 92 #include <machine/cpufunc.h> 93 #include <machine/cpuvar.h> 94 #include <machine/pmap.h> 95 #include <machine/vmparam.h> 96 #include <machine/mpbiosvar.h> 97 #include <machine/pcb.h> 98 #include <machine/specialreg.h> 99 #include <machine/segments.h> 100 #include <machine/gdt.h> 101 #include <machine/mtrr.h> 102 #include <machine/pio.h> 103 104 #include <x86/fpu.h> 105 106 #include <xen/xen.h> 107 #include <xen/xen-public/vcpu.h> 108 #include <xen/vcpuvar.h> 109 110 #if NLAPIC > 0 111 #include <machine/apicvar.h> 112 #include <machine/i82489reg.h> 113 #include <machine/i82489var.h> 114 #endif 115 116 #include <dev/ic/mc146818reg.h> 117 #include <dev/isa/isareg.h> 118 119 static int cpu_match(device_t, cfdata_t, void *); 120 static void cpu_attach(device_t, device_t, void *); 121 static void cpu_defer(device_t); 122 static int cpu_rescan(device_t, const char *, const int *); 123 static void cpu_childdetached(device_t, device_t); 124 static int vcpu_match(device_t, cfdata_t, void *); 125 static void vcpu_attach(device_t, device_t, void *); 126 static void cpu_attach_common(device_t, device_t, void *); 127 void cpu_offline_md(void); 128 129 struct cpu_softc { 130 device_t sc_dev; /* device tree glue */ 131 struct cpu_info *sc_info; /* pointer to CPU info */ 132 bool sc_wasonline; 133 }; 134 135 int mp_cpu_start(struct cpu_info *, vaddr_t); 136 void mp_cpu_start_cleanup(struct cpu_info *); 137 const struct cpu_functions mp_cpu_funcs = { mp_cpu_start, NULL, 138 mp_cpu_start_cleanup }; 139 140 CFATTACH_DECL2_NEW(cpu, sizeof(struct cpu_softc), 141 cpu_match, cpu_attach, NULL, NULL, cpu_rescan, cpu_childdetached); 142 143 CFATTACH_DECL_NEW(vcpu, sizeof(struct cpu_softc), 144 vcpu_match, vcpu_attach, NULL, NULL); 145 146 /* 147 * Statically-allocated CPU info for the primary CPU (or the only 148 * CPU, on uniprocessors). The CPU info list is initialized to 149 * point at it. 150 */ 151 #ifdef TRAPLOG 152 #include <machine/tlog.h> 153 struct tlog tlog_primary; 154 #endif 155 struct cpu_info cpu_info_primary __aligned(CACHE_LINE_SIZE) = { 156 .ci_dev = 0, 157 .ci_self = &cpu_info_primary, 158 .ci_idepth = -1, 159 .ci_curlwp = &lwp0, 160 .ci_curldt = -1, 161 #ifdef TRAPLOG 162 .ci_tlog = &tlog_primary, 163 #endif 164 165 }; 166 struct cpu_info phycpu_info_primary __aligned(CACHE_LINE_SIZE) = { 167 .ci_dev = 0, 168 .ci_self = &phycpu_info_primary, 169 }; 170 171 struct cpu_info *cpu_info_list = &cpu_info_primary; 172 struct cpu_info *phycpu_info_list = &phycpu_info_primary; 173 174 uint32_t cpu_feature[7]; /* X86 CPUID feature bits 175 * [0] basic features %edx 176 * [1] basic features %ecx 177 * [2] extended features %edx 178 * [3] extended features %ecx 179 * [4] VIA padlock features 180 * [5] structured extended features cpuid.7:%ebx 181 * [6] structured extended features cpuid.7:%ecx 182 */ 183 184 bool x86_mp_online; 185 paddr_t mp_trampoline_paddr = MP_TRAMPOLINE; 186 187 #if defined(MULTIPROCESSOR) 188 void cpu_hatch(void *); 189 static void cpu_boot_secondary(struct cpu_info *ci); 190 static void cpu_start_secondary(struct cpu_info *ci); 191 #endif /* MULTIPROCESSOR */ 192 193 static int 194 cpu_match(device_t parent, cfdata_t match, void *aux) 195 { 196 197 return 1; 198 } 199 200 static void 201 cpu_attach(device_t parent, device_t self, void *aux) 202 { 203 struct cpu_softc *sc = device_private(self); 204 struct cpu_attach_args *caa = aux; 205 struct cpu_info *ci; 206 uintptr_t ptr; 207 static int nphycpu = 0; 208 209 sc->sc_dev = self; 210 211 /* 212 * If we're an Application Processor, allocate a cpu_info 213 * If we're the first attached CPU use the primary cpu_info, 214 * otherwise allocate a new one 215 */ 216 aprint_naive("\n"); 217 aprint_normal("\n"); 218 if (nphycpu > 0) { 219 struct cpu_info *tmp; 220 ptr = (uintptr_t)kmem_zalloc(sizeof(*ci) + CACHE_LINE_SIZE - 1, 221 KM_SLEEP); 222 ci = (struct cpu_info *)roundup2(ptr, CACHE_LINE_SIZE); 223 ci->ci_curldt = -1; 224 225 tmp = phycpu_info_list; 226 while (tmp->ci_next) 227 tmp = tmp->ci_next; 228 229 tmp->ci_next = ci; 230 } else { 231 ci = &phycpu_info_primary; 232 } 233 234 ci->ci_self = ci; 235 sc->sc_info = ci; 236 237 ci->ci_dev = self; 238 ci->ci_acpiid = caa->cpu_id; 239 ci->ci_cpuid = caa->cpu_number; 240 ci->ci_vcpu = NULL; 241 ci->ci_index = nphycpu++; 242 243 if (!pmf_device_register(self, NULL, NULL)) 244 aprint_error_dev(self, "couldn't establish power handler\n"); 245 246 (void)config_defer(self, cpu_defer); 247 } 248 249 static void 250 cpu_defer(device_t self) 251 { 252 cpu_rescan(self, NULL, NULL); 253 } 254 255 static int 256 cpu_rescan(device_t self, const char *ifattr, const int *locators) 257 { 258 struct cpu_softc *sc = device_private(self); 259 struct cpufeature_attach_args cfaa; 260 struct cpu_info *ci = sc->sc_info; 261 262 memset(&cfaa, 0, sizeof(cfaa)); 263 cfaa.ci = ci; 264 265 if (ifattr_match(ifattr, "cpufeaturebus")) { 266 267 if (ci->ci_frequency == NULL) { 268 cfaa.name = "frequency"; 269 ci->ci_frequency = config_found_ia(self, 270 "cpufeaturebus", &cfaa, NULL); 271 } 272 } 273 274 return 0; 275 } 276 277 static void 278 cpu_childdetached(device_t self, device_t child) 279 { 280 struct cpu_softc *sc = device_private(self); 281 struct cpu_info *ci = sc->sc_info; 282 283 if (ci->ci_frequency == child) 284 ci->ci_frequency = NULL; 285 } 286 287 static int 288 vcpu_match(device_t parent, cfdata_t match, void *aux) 289 { 290 struct vcpu_attach_args *vcaa = aux; 291 struct vcpu_runstate_info vcr; 292 int error; 293 294 if (strcmp(vcaa->vcaa_name, match->cf_name) == 0) { 295 error = HYPERVISOR_vcpu_op(VCPUOP_get_runstate_info, 296 vcaa->vcaa_caa.cpu_number, &vcr); 297 switch (error) { 298 case 0: 299 return 1; 300 case -ENOENT: 301 return 0; 302 default: 303 panic("Unknown hypervisor error %d returned on vcpu runstate probe\n", error); 304 } 305 } 306 307 return 0; 308 } 309 310 static void 311 vcpu_attach(device_t parent, device_t self, void *aux) 312 { 313 struct vcpu_attach_args *vcaa = aux; 314 315 KASSERT(vcaa->vcaa_caa.cpu_func == NULL); 316 vcaa->vcaa_caa.cpu_func = &mp_cpu_funcs; 317 cpu_attach_common(parent, self, &vcaa->vcaa_caa); 318 319 if (!pmf_device_register(self, NULL, NULL)) 320 aprint_error_dev(self, "couldn't establish power handler\n"); 321 } 322 323 static int 324 vcpu_is_up(struct cpu_info *ci) 325 { 326 KASSERT(ci != NULL); 327 return HYPERVISOR_vcpu_op(VCPUOP_is_up, ci->ci_cpuid, NULL); 328 } 329 330 static void 331 cpu_vm_init(struct cpu_info *ci) 332 { 333 int ncolors = 2, i; 334 335 for (i = CAI_ICACHE; i <= CAI_L2CACHE; i++) { 336 struct x86_cache_info *cai; 337 int tcolors; 338 339 cai = &ci->ci_cinfo[i]; 340 341 tcolors = atop(cai->cai_totalsize); 342 switch (cai->cai_associativity) { 343 case 0xff: 344 tcolors = 1; /* fully associative */ 345 break; 346 case 0: 347 case 1: 348 break; 349 default: 350 tcolors /= cai->cai_associativity; 351 } 352 ncolors = max(ncolors, tcolors); 353 } 354 355 /* 356 * Knowing the size of the largest cache on this CPU, potentially 357 * re-color our pages. 358 */ 359 aprint_debug_dev(ci->ci_dev, "%d page colors\n", ncolors); 360 uvm_page_recolor(ncolors); 361 pmap_tlb_cpu_init(ci); 362 } 363 364 static void 365 cpu_attach_common(device_t parent, device_t self, void *aux) 366 { 367 struct cpu_softc *sc = device_private(self); 368 struct cpu_attach_args *caa = aux; 369 struct cpu_info *ci; 370 uintptr_t ptr; 371 int cpunum = caa->cpu_number; 372 static bool again = false; 373 374 sc->sc_dev = self; 375 376 /* 377 * If we're an Application Processor, allocate a cpu_info 378 * structure, otherwise use the primary's. 379 */ 380 if (caa->cpu_role == CPU_ROLE_AP) { 381 aprint_naive(": Application Processor\n"); 382 ptr = (uintptr_t)kmem_alloc(sizeof(*ci) + CACHE_LINE_SIZE - 1, 383 KM_SLEEP); 384 ci = (struct cpu_info *)roundup2(ptr, CACHE_LINE_SIZE); 385 memset(ci, 0, sizeof(*ci)); 386 #ifdef TRAPLOG 387 ci->ci_tlog_base = kmem_zalloc(sizeof(struct tlog), KM_SLEEP); 388 #endif 389 } else { 390 aprint_naive(": %s Processor\n", 391 caa->cpu_role == CPU_ROLE_SP ? "Single" : "Boot"); 392 ci = &cpu_info_primary; 393 } 394 395 ci->ci_self = ci; 396 sc->sc_info = ci; 397 ci->ci_dev = self; 398 ci->ci_cpuid = cpunum; 399 400 KASSERT(HYPERVISOR_shared_info != NULL); 401 KASSERT(cpunum < XEN_LEGACY_MAX_VCPUS); 402 ci->ci_vcpu = &HYPERVISOR_shared_info->vcpu_info[cpunum]; 403 404 KASSERT(ci->ci_func == 0); 405 ci->ci_func = caa->cpu_func; 406 aprint_normal("\n"); 407 408 /* Must be called before mi_cpu_attach(). */ 409 cpu_vm_init(ci); 410 411 if (caa->cpu_role == CPU_ROLE_AP) { 412 int error; 413 414 error = mi_cpu_attach(ci); 415 416 KASSERT(ci->ci_data.cpu_idlelwp != NULL); 417 if (error != 0) { 418 aprint_error_dev(self, 419 "mi_cpu_attach failed with %d\n", error); 420 return; 421 } 422 423 } else { 424 KASSERT(ci->ci_data.cpu_idlelwp != NULL); 425 } 426 427 KASSERT(ci->ci_cpuid == ci->ci_index); 428 #ifdef __x86_64__ 429 /* No user PGD mapped for this CPU yet */ 430 ci->ci_xen_current_user_pgd = 0; 431 #endif 432 #if defined(__x86_64__) || defined(PAE) 433 mutex_init(&ci->ci_kpm_mtx, MUTEX_DEFAULT, IPL_VM); 434 #endif 435 pmap_reference(pmap_kernel()); 436 ci->ci_pmap = pmap_kernel(); 437 ci->ci_tlbstate = TLBSTATE_STALE; 438 439 /* 440 * Boot processor may not be attached first, but the below 441 * must be done to allow booting other processors. 442 */ 443 if (!again) { 444 atomic_or_32(&ci->ci_flags, CPUF_PRESENT | CPUF_PRIMARY); 445 /* Basic init. */ 446 cpu_intr_init(ci); 447 cpu_get_tsc_freq(ci); 448 cpu_init(ci); 449 pmap_cpu_init_late(ci); 450 451 /* Every processor needs to init its own ipi h/w (similar to lapic) */ 452 xen_ipi_init(); 453 454 /* Make sure DELAY() is initialized. */ 455 DELAY(1); 456 again = true; 457 } 458 459 /* further PCB init done later. */ 460 461 switch (caa->cpu_role) { 462 case CPU_ROLE_SP: 463 atomic_or_32(&ci->ci_flags, CPUF_SP); 464 cpu_identify(ci); 465 x86_cpu_idle_init(); 466 break; 467 468 case CPU_ROLE_BP: 469 atomic_or_32(&ci->ci_flags, CPUF_BSP); 470 cpu_identify(ci); 471 x86_cpu_idle_init(); 472 break; 473 474 case CPU_ROLE_AP: 475 atomic_or_32(&ci->ci_flags, CPUF_AP); 476 477 /* 478 * report on an AP 479 */ 480 481 #if defined(MULTIPROCESSOR) 482 /* interrupt handler stack */ 483 cpu_intr_init(ci); 484 485 /* Setup per-cpu memory for gdt */ 486 gdt_alloc_cpu(ci); 487 488 pmap_cpu_init_late(ci); 489 cpu_start_secondary(ci); 490 491 if (ci->ci_flags & CPUF_PRESENT) { 492 struct cpu_info *tmp; 493 494 cpu_identify(ci); 495 tmp = cpu_info_list; 496 while (tmp->ci_next) 497 tmp = tmp->ci_next; 498 499 tmp->ci_next = ci; 500 } 501 #else 502 aprint_error_dev(ci->ci_dev, "not started\n"); 503 #endif 504 break; 505 506 default: 507 panic("unknown processor type??\n"); 508 } 509 510 #ifdef MPVERBOSE 511 if (mp_verbose) { 512 struct lwp *l = ci->ci_data.cpu_idlelwp; 513 struct pcb *pcb = lwp_getpcb(l); 514 515 aprint_verbose_dev(self, 516 "idle lwp at %p, idle sp at 0x%p\n", 517 l, 518 #ifdef i386 519 (void *)pcb->pcb_esp 520 #else 521 (void *)pcb->pcb_rsp 522 #endif 523 ); 524 525 } 526 #endif /* MPVERBOSE */ 527 } 528 529 /* 530 * Initialize the processor appropriately. 531 */ 532 533 void 534 cpu_init(struct cpu_info *ci) 535 { 536 537 /* 538 * If we have FXSAVE/FXRESTOR, use them. 539 */ 540 if (cpu_feature[0] & CPUID_FXSR) { 541 lcr4(rcr4() | CR4_OSFXSR); 542 543 /* 544 * If we have SSE/SSE2, enable XMM exceptions. 545 */ 546 if (cpu_feature[0] & (CPUID_SSE|CPUID_SSE2)) 547 lcr4(rcr4() | CR4_OSXMMEXCPT); 548 } 549 550 atomic_or_32(&ci->ci_flags, CPUF_RUNNING); 551 } 552 553 554 #ifdef MULTIPROCESSOR 555 556 void 557 cpu_boot_secondary_processors(void) 558 { 559 struct cpu_info *ci; 560 u_long i; 561 for (i = 0; i < maxcpus; i++) { 562 ci = cpu_lookup(i); 563 if (ci == NULL) 564 continue; 565 if (ci->ci_data.cpu_idlelwp == NULL) 566 continue; 567 if ((ci->ci_flags & CPUF_PRESENT) == 0) 568 continue; 569 if (ci->ci_flags & (CPUF_BSP|CPUF_SP|CPUF_PRIMARY)) 570 continue; 571 cpu_boot_secondary(ci); 572 } 573 574 x86_mp_online = true; 575 } 576 577 static void 578 cpu_init_idle_lwp(struct cpu_info *ci) 579 { 580 struct lwp *l = ci->ci_data.cpu_idlelwp; 581 struct pcb *pcb = lwp_getpcb(l); 582 583 pcb->pcb_cr0 = rcr0(); 584 } 585 586 void 587 cpu_init_idle_lwps(void) 588 { 589 struct cpu_info *ci; 590 u_long i; 591 592 for (i = 0; i < maxcpus; i++) { 593 ci = cpu_lookup(i); 594 if (ci == NULL) 595 continue; 596 if (ci->ci_data.cpu_idlelwp == NULL) 597 continue; 598 if ((ci->ci_flags & CPUF_PRESENT) == 0) 599 continue; 600 cpu_init_idle_lwp(ci); 601 } 602 } 603 604 static void 605 cpu_start_secondary(struct cpu_info *ci) 606 { 607 int i; 608 609 aprint_debug_dev(ci->ci_dev, "starting\n"); 610 611 ci->ci_curlwp = ci->ci_data.cpu_idlelwp; 612 613 if (CPU_STARTUP(ci, (vaddr_t) cpu_hatch) != 0) { 614 return; 615 } 616 617 /* 618 * wait for it to become ready 619 */ 620 for (i = 100000; (!(ci->ci_flags & CPUF_PRESENT)) && i > 0; i--) { 621 delay(10); 622 } 623 if ((ci->ci_flags & CPUF_PRESENT) == 0) { 624 aprint_error_dev(ci->ci_dev, "failed to become ready\n"); 625 #if defined(MPDEBUG) && defined(DDB) 626 printf("dropping into debugger; continue from here to resume boot\n"); 627 Debugger(); 628 #endif 629 } 630 631 CPU_START_CLEANUP(ci); 632 } 633 634 void 635 cpu_boot_secondary(struct cpu_info *ci) 636 { 637 int i; 638 atomic_or_32(&ci->ci_flags, CPUF_GO); 639 for (i = 100000; (!(ci->ci_flags & CPUF_RUNNING)) && i > 0; i--) { 640 delay(10); 641 } 642 if ((ci->ci_flags & CPUF_RUNNING) == 0) { 643 aprint_error_dev(ci->ci_dev, "CPU failed to start\n"); 644 #if defined(MPDEBUG) && defined(DDB) 645 printf("dropping into debugger; continue from here to resume boot\n"); 646 Debugger(); 647 #endif 648 } 649 } 650 651 /* 652 * APs end up here immediately after initialisation and VCPUOP_up in 653 * mp_cpu_start(). 654 * At this point, we are running in the idle pcb/idle stack of the new 655 * CPU. This function jumps to the idle loop and starts looking for 656 * work. 657 */ 658 extern void x86_64_tls_switch(struct lwp *); 659 void 660 cpu_hatch(void *v) 661 { 662 struct cpu_info *ci = (struct cpu_info *)v; 663 struct pcb *pcb; 664 int s, i; 665 666 /* Setup TLS and kernel GS/FS */ 667 cpu_init_msrs(ci, true); 668 cpu_init_idt(); 669 gdt_init_cpu(ci); 670 671 cpu_probe(ci); 672 673 atomic_or_32(&ci->ci_flags, CPUF_PRESENT); 674 675 while ((ci->ci_flags & CPUF_GO) == 0) { 676 /* Don't use delay, boot CPU may be patching the text. */ 677 for (i = 10000; i != 0; i--) 678 x86_pause(); 679 } 680 681 /* Because the text may have been patched in x86_patch(). */ 682 x86_flush(); 683 tlbflushg(); 684 685 KASSERT((ci->ci_flags & CPUF_RUNNING) == 0); 686 687 pcb = lwp_getpcb(curlwp); 688 pcb->pcb_cr3 = pmap_pdirpa(pmap_kernel(), 0); 689 pcb = lwp_getpcb(ci->ci_data.cpu_idlelwp); 690 691 xen_ipi_init(); 692 693 xen_initclocks(); 694 695 #ifdef __x86_64__ 696 fpuinit(ci); 697 #endif 698 699 lldt(GSEL(GLDT_SEL, SEL_KPL)); 700 701 cpu_init(ci); 702 cpu_get_tsc_freq(ci); 703 704 s = splhigh(); 705 x86_enable_intr(); 706 splx(s); 707 708 aprint_debug_dev(ci->ci_dev, "running\n"); 709 710 cpu_switchto(NULL, ci->ci_data.cpu_idlelwp, true); 711 712 idle_loop(NULL); 713 KASSERT(false); 714 } 715 716 #if defined(DDB) 717 718 #include <ddb/db_output.h> 719 #include <machine/db_machdep.h> 720 721 /* 722 * Dump CPU information from ddb. 723 */ 724 void 725 cpu_debug_dump(void) 726 { 727 struct cpu_info *ci; 728 CPU_INFO_ITERATOR cii; 729 730 db_printf("addr dev id flags ipis curlwp fpcurlwp\n"); 731 for (CPU_INFO_FOREACH(cii, ci)) { 732 db_printf("%p %s %ld %x %x %10p %10p\n", 733 ci, 734 ci->ci_dev == NULL ? "BOOT" : device_xname(ci->ci_dev), 735 (long)ci->ci_cpuid, 736 ci->ci_flags, ci->ci_ipis, 737 ci->ci_curlwp, 738 ci->ci_fpcurlwp); 739 } 740 } 741 #endif /* DDB */ 742 743 #endif /* MULTIPROCESSOR */ 744 745 extern void hypervisor_callback(void); 746 extern void failsafe_callback(void); 747 #ifdef __x86_64__ 748 typedef void (vector)(void); 749 extern vector Xsyscall, Xsyscall32; 750 #endif 751 752 /* 753 * Setup the "trampoline". On Xen, we setup nearly all cpu context 754 * outside a trampoline, so we prototype and call targetip like so: 755 * void targetip(struct cpu_info *); 756 */ 757 758 static void 759 gdt_prepframes(paddr_t *frames, vaddr_t base, uint32_t entries) 760 { 761 int i; 762 for (i = 0; i < roundup(entries, PAGE_SIZE) >> PAGE_SHIFT; i++) { 763 frames[i] = ((paddr_t)xpmap_ptetomach( 764 (pt_entry_t *)(base + (i << PAGE_SHIFT)))) >> PAGE_SHIFT; 765 766 /* Mark Read-only */ 767 pmap_pte_clearbits(kvtopte(base + (i << PAGE_SHIFT)), 768 PG_RW); 769 } 770 } 771 772 #ifdef __x86_64__ 773 extern char *ldtstore; 774 775 static void 776 xen_init_amd64_vcpuctxt(struct cpu_info *ci, struct vcpu_guest_context *initctx, 777 void targetrip(struct cpu_info *)) 778 { 779 /* page frames to point at GDT */ 780 extern int gdt_size; 781 paddr_t frames[16]; 782 psize_t gdt_ents; 783 784 struct lwp *l; 785 struct pcb *pcb; 786 787 volatile struct vcpu_info *vci; 788 789 KASSERT(ci != NULL); 790 KASSERT(ci != &cpu_info_primary); 791 KASSERT(initctx != NULL); 792 KASSERT(targetrip != NULL); 793 794 memset(initctx, 0, sizeof(*initctx)); 795 796 gdt_ents = roundup(gdt_size, PAGE_SIZE) >> PAGE_SHIFT; 797 KASSERT(gdt_ents <= 16); 798 799 gdt_prepframes(frames, (vaddr_t)ci->ci_gdt, gdt_ents); 800 801 /* Initialise the vcpu context: We use idle_loop()'s pcb context. */ 802 803 l = ci->ci_data.cpu_idlelwp; 804 805 KASSERT(l != NULL); 806 pcb = lwp_getpcb(l); 807 KASSERT(pcb != NULL); 808 809 /* resume with interrupts off */ 810 vci = ci->ci_vcpu; 811 vci->evtchn_upcall_mask = 1; 812 xen_mb(); 813 814 /* resume in kernel-mode */ 815 initctx->flags = VGCF_in_kernel | VGCF_online; 816 817 /* Stack and entry points: 818 * We arrange for the stack frame for cpu_hatch() to 819 * appear as a callee frame of lwp_trampoline(). Being a 820 * leaf frame prevents trampling on any of the MD stack setup 821 * that x86/vm_machdep.c:cpu_lwp_fork() does for idle_loop() 822 */ 823 824 initctx->user_regs.rdi = (uint64_t) ci; /* targetrip(ci); */ 825 initctx->user_regs.rip = (vaddr_t) targetrip; 826 827 initctx->user_regs.cs = GSEL(GCODE_SEL, SEL_KPL); 828 829 initctx->user_regs.rflags = pcb->pcb_flags; 830 initctx->user_regs.rsp = pcb->pcb_rsp; 831 832 /* Data segments */ 833 initctx->user_regs.ss = GSEL(GDATA_SEL, SEL_KPL); 834 initctx->user_regs.es = GSEL(GDATA_SEL, SEL_KPL); 835 initctx->user_regs.ds = GSEL(GDATA_SEL, SEL_KPL); 836 837 /* GDT */ 838 memcpy(initctx->gdt_frames, frames, sizeof(frames)); 839 initctx->gdt_ents = gdt_ents; 840 841 /* LDT */ 842 initctx->ldt_base = (unsigned long)ldtstore; 843 initctx->ldt_ents = LDT_SIZE >> 3; 844 845 /* Kernel context state */ 846 initctx->kernel_ss = GSEL(GDATA_SEL, SEL_KPL); 847 initctx->kernel_sp = pcb->pcb_rsp0; 848 initctx->ctrlreg[0] = pcb->pcb_cr0; 849 initctx->ctrlreg[1] = 0; /* "resuming" from kernel - no User cr3. */ 850 initctx->ctrlreg[2] = (vaddr_t)targetrip; 851 /* 852 * Use pmap_kernel() L4 PD directly, until we setup the 853 * per-cpu L4 PD in pmap_cpu_init_late() 854 */ 855 initctx->ctrlreg[3] = xen_pfn_to_cr3(x86_btop(xpmap_ptom(ci->ci_kpm_pdirpa))); 856 initctx->ctrlreg[4] = CR4_PAE | CR4_OSFXSR | CR4_OSXMMEXCPT; 857 858 /* Xen callbacks */ 859 initctx->event_callback_eip = (unsigned long)hypervisor_callback; 860 initctx->failsafe_callback_eip = (unsigned long)failsafe_callback; 861 initctx->syscall_callback_eip = (unsigned long)Xsyscall; 862 863 return; 864 } 865 #else /* i386 */ 866 extern union descriptor *ldt; 867 extern void Xsyscall(void); 868 869 static void 870 xen_init_i386_vcpuctxt(struct cpu_info *ci, struct vcpu_guest_context *initctx, 871 void targeteip(struct cpu_info *)) 872 { 873 /* page frames to point at GDT */ 874 extern int gdt_size; 875 paddr_t frames[16]; 876 psize_t gdt_ents; 877 878 struct lwp *l; 879 struct pcb *pcb; 880 881 volatile struct vcpu_info *vci; 882 883 KASSERT(ci != NULL); 884 KASSERT(ci != &cpu_info_primary); 885 KASSERT(initctx != NULL); 886 KASSERT(targeteip != NULL); 887 888 memset(initctx, 0, sizeof(*initctx)); 889 890 gdt_ents = roundup(gdt_size, PAGE_SIZE) >> PAGE_SHIFT; 891 KASSERT(gdt_ents <= 16); 892 893 gdt_prepframes(frames, (vaddr_t)ci->ci_gdt, gdt_ents); 894 895 /* 896 * Initialise the vcpu context: 897 * We use this cpu's idle_loop() pcb context. 898 */ 899 900 l = ci->ci_data.cpu_idlelwp; 901 902 KASSERT(l != NULL); 903 pcb = lwp_getpcb(l); 904 KASSERT(pcb != NULL); 905 906 /* resume with interrupts off */ 907 vci = ci->ci_vcpu; 908 vci->evtchn_upcall_mask = 1; 909 xen_mb(); 910 911 /* resume in kernel-mode */ 912 initctx->flags = VGCF_in_kernel | VGCF_online; 913 914 /* Stack frame setup for cpu_hatch(): 915 * We arrange for the stack frame for cpu_hatch() to 916 * appear as a callee frame of lwp_trampoline(). Being a 917 * leaf frame prevents trampling on any of the MD stack setup 918 * that x86/vm_machdep.c:cpu_lwp_fork() does for idle_loop() 919 */ 920 921 initctx->user_regs.esp = pcb->pcb_esp - 4; /* Leave word for 922 arg1 */ 923 { 924 /* targeteip(ci); */ 925 uint32_t *arg = (uint32_t *)initctx->user_regs.esp; 926 arg[1] = (uint32_t)ci; /* arg1 */ 927 } 928 929 initctx->user_regs.eip = (vaddr_t)targeteip; 930 initctx->user_regs.cs = GSEL(GCODE_SEL, SEL_KPL); 931 initctx->user_regs.eflags |= pcb->pcb_iopl; 932 933 /* Data segments */ 934 initctx->user_regs.ss = GSEL(GDATA_SEL, SEL_KPL); 935 initctx->user_regs.es = GSEL(GDATA_SEL, SEL_KPL); 936 initctx->user_regs.ds = GSEL(GDATA_SEL, SEL_KPL); 937 initctx->user_regs.fs = GSEL(GDATA_SEL, SEL_KPL); 938 939 /* GDT */ 940 memcpy(initctx->gdt_frames, frames, sizeof(frames)); 941 initctx->gdt_ents = gdt_ents; 942 943 /* LDT */ 944 initctx->ldt_base = (unsigned long)ldt; 945 initctx->ldt_ents = NLDT; 946 947 /* Kernel context state */ 948 initctx->kernel_ss = GSEL(GDATA_SEL, SEL_KPL); 949 initctx->kernel_sp = pcb->pcb_esp0; 950 initctx->ctrlreg[0] = pcb->pcb_cr0; 951 initctx->ctrlreg[1] = 0; /* "resuming" from kernel - no User cr3. */ 952 initctx->ctrlreg[2] = (vaddr_t)targeteip; 953 #ifdef PAE 954 initctx->ctrlreg[3] = xen_pfn_to_cr3(x86_btop(xpmap_ptom(ci->ci_pae_l3_pdirpa))); 955 #else 956 initctx->ctrlreg[3] = xen_pfn_to_cr3(x86_btop(xpmap_ptom(pcb->pcb_cr3))); 957 #endif 958 initctx->ctrlreg[4] = /* CR4_PAE | */CR4_OSFXSR | CR4_OSXMMEXCPT; 959 960 /* Xen callbacks */ 961 initctx->event_callback_eip = (unsigned long)hypervisor_callback; 962 initctx->event_callback_cs = GSEL(GCODE_SEL, SEL_KPL); 963 initctx->failsafe_callback_eip = (unsigned long)failsafe_callback; 964 initctx->failsafe_callback_cs = GSEL(GCODE_SEL, SEL_KPL); 965 966 return; 967 } 968 #endif /* __x86_64__ */ 969 970 int 971 mp_cpu_start(struct cpu_info *ci, vaddr_t target) 972 { 973 int hyperror; 974 struct vcpu_guest_context vcpuctx; 975 976 KASSERT(ci != NULL); 977 KASSERT(ci != &cpu_info_primary); 978 KASSERT(ci->ci_flags & CPUF_AP); 979 980 #ifdef __x86_64__ 981 xen_init_amd64_vcpuctxt(ci, &vcpuctx, (void (*)(struct cpu_info *))target); 982 #else 983 xen_init_i386_vcpuctxt(ci, &vcpuctx, (void (*)(struct cpu_info *))target); 984 #endif 985 986 /* Initialise the given vcpu to execute cpu_hatch(ci); */ 987 if ((hyperror = HYPERVISOR_vcpu_op(VCPUOP_initialise, ci->ci_cpuid, &vcpuctx))) { 988 aprint_error(": context initialisation failed. errno = %d\n", hyperror); 989 return hyperror; 990 } 991 992 /* Start it up */ 993 994 /* First bring it down */ 995 if ((hyperror = HYPERVISOR_vcpu_op(VCPUOP_down, ci->ci_cpuid, NULL))) { 996 aprint_error(": VCPUOP_down hypervisor command failed. errno = %d\n", hyperror); 997 return hyperror; 998 } 999 1000 if ((hyperror = HYPERVISOR_vcpu_op(VCPUOP_up, ci->ci_cpuid, NULL))) { 1001 aprint_error(": VCPUOP_up hypervisor command failed. errno = %d\n", hyperror); 1002 return hyperror; 1003 } 1004 1005 if (!vcpu_is_up(ci)) { 1006 aprint_error(": did not come up\n"); 1007 return -1; 1008 } 1009 1010 return 0; 1011 } 1012 1013 void 1014 mp_cpu_start_cleanup(struct cpu_info *ci) 1015 { 1016 if (vcpu_is_up(ci)) { 1017 aprint_debug_dev(ci->ci_dev, "is started.\n"); 1018 } else { 1019 aprint_error_dev(ci->ci_dev, "did not start up.\n"); 1020 } 1021 } 1022 1023 void 1024 cpu_init_msrs(struct cpu_info *ci, bool full) 1025 { 1026 #ifdef __x86_64__ 1027 if (full) { 1028 HYPERVISOR_set_segment_base(SEGBASE_FS, 0); 1029 HYPERVISOR_set_segment_base(SEGBASE_GS_KERNEL, (uint64_t)ci); 1030 HYPERVISOR_set_segment_base(SEGBASE_GS_USER, 0); 1031 } 1032 #endif 1033 1034 if (cpu_feature[2] & CPUID_NOX) 1035 wrmsr(MSR_EFER, rdmsr(MSR_EFER) | EFER_NXE); 1036 } 1037 1038 void 1039 cpu_offline_md(void) 1040 { 1041 int s; 1042 1043 s = splhigh(); 1044 fpusave_cpu(true); 1045 splx(s); 1046 } 1047 1048 void 1049 cpu_get_tsc_freq(struct cpu_info *ci) 1050 { 1051 uint32_t vcpu_tversion; 1052 const volatile vcpu_time_info_t *tinfo = &ci->ci_vcpu->time; 1053 1054 vcpu_tversion = tinfo->version; 1055 while (tinfo->version == vcpu_tversion); /* Wait for a time update. XXX: timeout ? */ 1056 1057 uint64_t freq = 1000000000ULL << 32; 1058 freq = freq / (uint64_t)tinfo->tsc_to_system_mul; 1059 if (tinfo->tsc_shift < 0) 1060 freq = freq << -tinfo->tsc_shift; 1061 else 1062 freq = freq >> tinfo->tsc_shift; 1063 ci->ci_data.cpu_cc_freq = freq; 1064 } 1065 1066 void 1067 x86_cpu_idle_xen(void) 1068 { 1069 struct cpu_info *ci = curcpu(); 1070 1071 KASSERT(ci->ci_ilevel == IPL_NONE); 1072 1073 x86_disable_intr(); 1074 if (!__predict_false(ci->ci_want_resched)) { 1075 idle_block(); 1076 } else { 1077 x86_enable_intr(); 1078 } 1079 } 1080 1081 /* 1082 * Loads pmap for the current CPU. 1083 */ 1084 void 1085 cpu_load_pmap(struct pmap *pmap, struct pmap *oldpmap) 1086 { 1087 KASSERT(pmap != pmap_kernel()); 1088 1089 #if defined(__x86_64__) || defined(PAE) 1090 struct cpu_info *ci = curcpu(); 1091 cpuid_t cid = cpu_index(ci); 1092 1093 mutex_enter(&ci->ci_kpm_mtx); 1094 /* make new pmap visible to xen_kpm_sync() */ 1095 kcpuset_atomic_set(pmap->pm_xen_ptp_cpus, cid); 1096 #endif 1097 1098 #ifdef i386 1099 #ifdef PAE 1100 { 1101 int i; 1102 paddr_t l3_pd = xpmap_ptom_masked(ci->ci_pae_l3_pdirpa); 1103 /* don't update the kernel L3 slot */ 1104 for (i = 0 ; i < PDP_SIZE - 1; i++) { 1105 xpq_queue_pte_update(l3_pd + i * sizeof(pd_entry_t), 1106 xpmap_ptom(pmap->pm_pdirpa[i]) | PG_V); 1107 } 1108 tlbflush(); 1109 } 1110 #else /* PAE */ 1111 lcr3(pmap_pdirpa(pmap, 0)); 1112 #endif /* PAE */ 1113 #endif /* i386 */ 1114 1115 #ifdef __x86_64__ 1116 { 1117 int i; 1118 pd_entry_t *new_pgd; 1119 paddr_t l4_pd_ma; 1120 1121 l4_pd_ma = xpmap_ptom_masked(ci->ci_kpm_pdirpa); 1122 1123 /* 1124 * Map user space address in kernel space and load 1125 * user cr3 1126 */ 1127 new_pgd = pmap->pm_pdir; 1128 KASSERT(pmap == ci->ci_pmap); 1129 1130 /* Copy user pmap L4 PDEs (in user addr. range) to per-cpu L4 */ 1131 for (i = 0; i < PDIR_SLOT_PTE; i++) { 1132 KASSERT(pmap != pmap_kernel() || new_pgd[i] == 0); 1133 if (ci->ci_kpm_pdir[i] != new_pgd[i]) { 1134 xpq_queue_pte_update( 1135 l4_pd_ma + i * sizeof(pd_entry_t), 1136 new_pgd[i]); 1137 } 1138 } 1139 1140 xen_set_user_pgd(pmap_pdirpa(pmap, 0)); 1141 ci->ci_xen_current_user_pgd = pmap_pdirpa(pmap, 0); 1142 1143 tlbflush(); 1144 } 1145 #endif /* __x86_64__ */ 1146 1147 #if defined(__x86_64__) || defined(PAE) 1148 /* old pmap no longer visible to xen_kpm_sync() */ 1149 if (oldpmap != pmap_kernel()) { 1150 kcpuset_atomic_clear(oldpmap->pm_xen_ptp_cpus, cid); 1151 } 1152 mutex_exit(&ci->ci_kpm_mtx); 1153 #endif 1154 } 1155 1156 /* 1157 * pmap_cpu_init_late: perform late per-CPU initialization. 1158 * 1159 * Short note about percpu PDIR pages. Both the PAE and __x86_64__ architectures 1160 * have per-cpu PDIR tables, for two different reasons: 1161 * - on PAE, this is to get around Xen's pagetable setup constraints (multiple 1162 * L3[3]s cannot point to the same L2 - Xen will refuse to pin a table set up 1163 * this way). 1164 * - on __x86_64__, this is for multiple CPUs to map in different user pmaps 1165 * (see cpu_load_pmap()). 1166 * 1167 * What this means for us is that the PDIR of the pmap_kernel() is considered 1168 * to be a canonical "SHADOW" PDIR with the following properties: 1169 * - its recursive mapping points to itself 1170 * - per-cpu recursive mappings point to themselves on __x86_64__ 1171 * - per-cpu L4 pages' kernel entries are expected to be in sync with 1172 * the shadow 1173 */ 1174 1175 void 1176 pmap_cpu_init_late(struct cpu_info *ci) 1177 { 1178 #if defined(PAE) || defined(__x86_64__) 1179 /* 1180 * The BP has already its own PD page allocated during early 1181 * MD startup. 1182 */ 1183 1184 #if defined(__x86_64__) 1185 /* Setup per-cpu normal_pdes */ 1186 int i; 1187 extern pd_entry_t * const normal_pdes[]; 1188 for (i = 0;i < PTP_LEVELS - 1;i++) { 1189 ci->ci_normal_pdes[i] = normal_pdes[i]; 1190 } 1191 #endif /* __x86_64__ */ 1192 1193 if (ci == &cpu_info_primary) 1194 return; 1195 1196 KASSERT(ci != NULL); 1197 1198 #if defined(PAE) 1199 cpu_alloc_l3_page(ci); 1200 KASSERT(ci->ci_pae_l3_pdirpa != 0); 1201 1202 /* Initialise L2 entries 0 - 2: Point them to pmap_kernel() */ 1203 int i; 1204 for (i = 0 ; i < PDP_SIZE - 1; i++) { 1205 ci->ci_pae_l3_pdir[i] = 1206 xpmap_ptom_masked(pmap_kernel()->pm_pdirpa[i]) | PG_V; 1207 } 1208 #endif /* PAE */ 1209 1210 ci->ci_kpm_pdir = (pd_entry_t *)uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 1211 UVM_KMF_WIRED | UVM_KMF_ZERO | UVM_KMF_NOWAIT); 1212 1213 if (ci->ci_kpm_pdir == NULL) { 1214 panic("%s: failed to allocate L4 per-cpu PD for CPU %d\n", 1215 __func__, cpu_index(ci)); 1216 } 1217 ci->ci_kpm_pdirpa = vtophys((vaddr_t)ci->ci_kpm_pdir); 1218 KASSERT(ci->ci_kpm_pdirpa != 0); 1219 1220 #if defined(__x86_64__) 1221 /* 1222 * Copy over the pmap_kernel() shadow L4 entries 1223 */ 1224 1225 memcpy(ci->ci_kpm_pdir, pmap_kernel()->pm_pdir, PAGE_SIZE); 1226 1227 /* Recursive kernel mapping */ 1228 ci->ci_kpm_pdir[PDIR_SLOT_PTE] = xpmap_ptom_masked(ci->ci_kpm_pdirpa) 1229 | PG_k | PG_V; 1230 #elif defined(PAE) 1231 /* Copy over the pmap_kernel() shadow L2 entries that map the kernel */ 1232 memcpy(ci->ci_kpm_pdir, pmap_kernel()->pm_pdir + PDIR_SLOT_KERN, 1233 nkptp[PTP_LEVELS - 1] * sizeof(pd_entry_t)); 1234 #endif /* __x86_64__ else PAE */ 1235 1236 /* Xen wants a RO pdir. */ 1237 pmap_protect(pmap_kernel(), (vaddr_t)ci->ci_kpm_pdir, 1238 (vaddr_t)ci->ci_kpm_pdir + PAGE_SIZE, VM_PROT_READ); 1239 pmap_update(pmap_kernel()); 1240 #if defined(PAE) 1241 /* 1242 * Initialize L3 entry 3. This mapping is shared across all pmaps and is 1243 * static, ie: loading a new pmap will not update this entry. 1244 */ 1245 ci->ci_pae_l3_pdir[3] = xpmap_ptom_masked(ci->ci_kpm_pdirpa) | PG_k | PG_V; 1246 1247 /* Xen wants a RO L3. */ 1248 pmap_protect(pmap_kernel(), (vaddr_t)ci->ci_pae_l3_pdir, 1249 (vaddr_t)ci->ci_pae_l3_pdir + PAGE_SIZE, VM_PROT_READ); 1250 pmap_update(pmap_kernel()); 1251 1252 xpq_queue_pin_l3_table(xpmap_ptom_masked(ci->ci_pae_l3_pdirpa)); 1253 1254 #elif defined(__x86_64__) 1255 xpq_queue_pin_l4_table(xpmap_ptom_masked(ci->ci_kpm_pdirpa)); 1256 #endif /* PAE , __x86_64__ */ 1257 #endif /* defined(PAE) || defined(__x86_64__) */ 1258 } 1259 1260 /* 1261 * Notify all other cpus to halt. 1262 */ 1263 1264 void 1265 cpu_broadcast_halt(void) 1266 { 1267 xen_broadcast_ipi(XEN_IPI_HALT); 1268 } 1269 1270 /* 1271 * Send a dummy ipi to a cpu. 1272 */ 1273 1274 void 1275 cpu_kick(struct cpu_info *ci) 1276 { 1277 (void)xen_send_ipi(ci, XEN_IPI_KICK); 1278 } 1279