1 /* $NetBSD: patch.c,v 1.18 2009/04/24 17:45:40 ad Exp $ */ 2 3 /*- 4 * Copyright (c) 2007, 2008, 2009 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Andrew Doran. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Patch kernel code at boot time, depending on available CPU features. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: patch.c,v 1.18 2009/04/24 17:45:40 ad Exp $"); 38 39 #include "opt_lockdebug.h" 40 41 #include <sys/types.h> 42 #include <sys/systm.h> 43 44 #include <machine/cpu.h> 45 #include <machine/cpufunc.h> 46 #include <machine/specialreg.h> 47 48 #include <x86/cpuvar.h> 49 #include <x86/cputypes.h> 50 51 void spllower(int); 52 void spllower_end(void); 53 void cx8_spllower(int); 54 void cx8_spllower_end(void); 55 void cx8_spllower_patch(void); 56 57 void mutex_spin_exit_end(void); 58 void i686_mutex_spin_exit(int); 59 void i686_mutex_spin_exit_end(void); 60 void i686_mutex_spin_exit_patch(void); 61 62 void membar_consumer(void); 63 void membar_consumer_end(void); 64 void membar_sync(void); 65 void membar_sync_end(void); 66 void sse2_lfence(void); 67 void sse2_lfence_end(void); 68 void sse2_mfence(void); 69 void sse2_mfence_end(void); 70 71 void _atomic_cas_64(void); 72 void _atomic_cas_64_end(void); 73 void _atomic_cas_cx8(void); 74 void _atomic_cas_cx8_end(void); 75 76 extern void *x86_lockpatch[]; 77 extern void *x86_retpatch[]; 78 extern void *atomic_lockpatch[]; 79 80 #define X86_NOP 0x90 81 #define X86_REP 0xf3 82 #define X86_RET 0xc3 83 #define X86_CS 0x2e 84 #define X86_DS 0x3e 85 #define X86_GROUP_0F 0x0f 86 87 static void 88 adjust_jumpoff(uint8_t *ptr, void *from_s, void *to_s) 89 { 90 91 /* Branch hints */ 92 if (ptr[0] == X86_CS || ptr[0] == X86_DS) 93 ptr++; 94 /* Conditional jumps */ 95 if (ptr[0] == X86_GROUP_0F) 96 ptr++; 97 /* 4-byte relative jump or call */ 98 *(uint32_t *)(ptr + 1 - (uintptr_t)from_s + (uintptr_t)to_s) += 99 ((uint32_t)(uintptr_t)from_s - (uint32_t)(uintptr_t)to_s); 100 } 101 102 static void __unused 103 patchfunc(void *from_s, void *from_e, void *to_s, void *to_e, 104 void *pcrel) 105 { 106 107 if ((uintptr_t)from_e - (uintptr_t)from_s != 108 (uintptr_t)to_e - (uintptr_t)to_s) 109 panic("patchfunc: sizes do not match (from=%p)", from_s); 110 111 memcpy(to_s, from_s, (uintptr_t)to_e - (uintptr_t)to_s); 112 if (pcrel != NULL) 113 adjust_jumpoff(pcrel, from_s, to_s); 114 115 #ifdef GPROF 116 #ifdef i386 117 #define MCOUNT_CALL_OFFSET 3 118 #endif 119 #ifdef __x86_64__ 120 #define MCOUNT_CALL_OFFSET 5 121 #endif 122 /* Patch mcount call offset */ 123 adjust_jumpoff((uint8_t *)from_s + MCOUNT_CALL_OFFSET, from_s, to_s); 124 #endif 125 } 126 127 static inline void __unused 128 patchbytes(void *addr, const int byte1, const int byte2, const int byte3) 129 { 130 131 ((uint8_t *)addr)[0] = (uint8_t)byte1; 132 if (byte2 != -1) 133 ((uint8_t *)addr)[1] = (uint8_t)byte2; 134 if (byte3 != -1) 135 ((uint8_t *)addr)[2] = (uint8_t)byte3; 136 } 137 138 void 139 x86_patch(bool early) 140 { 141 static bool first, second; 142 u_long psl; 143 u_long cr0; 144 int i; 145 146 if (early) { 147 if (first) 148 return; 149 first = true; 150 } else { 151 if (second) 152 return; 153 second = true; 154 } 155 156 /* Disable interrupts. */ 157 psl = x86_read_psl(); 158 x86_disable_intr(); 159 160 /* Disable write protection in supervisor mode. */ 161 cr0 = rcr0(); 162 lcr0(cr0 & ~CR0_WP); 163 164 #if !defined(GPROF) 165 if (!early && ncpu == 1) { 166 #ifndef LOCKDEBUG 167 /* Uniprocessor: kill LOCK prefixes. */ 168 for (i = 0; x86_lockpatch[i] != 0; i++) 169 patchbytes(x86_lockpatch[i], X86_NOP, -1, -1); 170 for (i = 0; atomic_lockpatch[i] != 0; i++) 171 patchbytes(atomic_lockpatch[i], X86_NOP, -1, -1); 172 #endif /* !LOCKDEBUG */ 173 } 174 if (!early && (cpu_feature & CPUID_SSE2) != 0) { 175 /* Faster memory barriers. */ 176 patchfunc( 177 sse2_lfence, sse2_lfence_end, 178 membar_consumer, membar_consumer_end, 179 NULL 180 ); 181 patchfunc( 182 sse2_mfence, sse2_mfence_end, 183 membar_sync, membar_sync_end, 184 NULL 185 ); 186 } 187 #endif /* GPROF */ 188 189 #ifdef i386 190 /* 191 * Patch early and late. Second time around the 'lock' prefix 192 * may be gone. 193 */ 194 if ((cpu_feature & CPUID_CX8) != 0) { 195 patchfunc( 196 _atomic_cas_cx8, _atomic_cas_cx8_end, 197 _atomic_cas_64, _atomic_cas_64_end, 198 NULL 199 ); 200 } 201 #endif /* i386 */ 202 203 if (!early && (cpu_feature & CPUID_CX8) != 0) { 204 /* Faster splx(), mutex_spin_exit(). */ 205 patchfunc( 206 cx8_spllower, cx8_spllower_end, 207 spllower, spllower_end, 208 cx8_spllower_patch 209 ); 210 #if defined(i386) && !defined(LOCKDEBUG) 211 patchfunc( 212 i686_mutex_spin_exit, i686_mutex_spin_exit_end, 213 mutex_spin_exit, mutex_spin_exit_end, 214 i686_mutex_spin_exit_patch 215 ); 216 #endif /* !LOCKDEBUG */ 217 } 218 219 /* 220 * On some Opteron revisions, locked operations erroneously 221 * allow memory references to be `bled' outside of critical 222 * sections. Apply workaround. 223 */ 224 if (cpu_vendor == CPUVENDOR_AMD && 225 (CPUID2FAMILY(cpu_info_primary.ci_signature) == 0xe || 226 (CPUID2FAMILY(cpu_info_primary.ci_signature) == 0xf && 227 CPUID2EXTMODEL(cpu_info_primary.ci_signature) < 0x4))) { 228 for (i = 0; x86_retpatch[i] != 0; i++) { 229 /* ret,nop,nop,ret -> lfence,ret */ 230 patchbytes(x86_retpatch[i], 0x0f, 0xae, 0xe8); 231 } 232 } 233 234 /* Write back and invalidate cache, flush pipelines. */ 235 wbinvd(); 236 x86_flush(); 237 x86_write_psl(psl); 238 239 /* Re-enable write protection. */ 240 lcr0(cr0); 241 } 242