1 /* $NetBSD: identcpu.c,v 1.111 2020/06/29 23:51:35 riastradh Exp $ */ 2 3 /*- 4 * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Frank van der Linden, and by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: identcpu.c,v 1.111 2020/06/29 23:51:35 riastradh Exp $"); 34 35 #include "opt_xen.h" 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/device.h> 40 #include <sys/cpu.h> 41 42 #include <crypto/aes/arch/x86/aes_ni.h> 43 #include <crypto/aes/arch/x86/aes_sse2.h> 44 #include <crypto/aes/arch/x86/aes_ssse3.h> 45 #include <crypto/aes/arch/x86/aes_via.h> 46 47 #include <uvm/uvm_extern.h> 48 49 #include <machine/specialreg.h> 50 #include <machine/pio.h> 51 #include <machine/cpu.h> 52 53 #include <x86/cputypes.h> 54 #include <x86/cacheinfo.h> 55 #include <x86/cpuvar.h> 56 #include <x86/fpu.h> 57 58 #include <x86/x86/vmtreg.h> /* for vmt_hvcall() */ 59 #include <x86/x86/vmtvar.h> /* for vmt_hvcall() */ 60 61 #ifndef XENPV 62 #include "hyperv.h" 63 #if NHYPERV > 0 64 #include <x86/x86/hypervvar.h> 65 #endif 66 #endif 67 68 static const struct x86_cache_info intel_cpuid_cache_info[] = INTEL_CACHE_INFO; 69 70 static const struct x86_cache_info amd_cpuid_l2l3cache_assoc_info[] = 71 AMD_L2L3CACHE_INFO; 72 73 int cpu_vendor; 74 char cpu_brand_string[49]; 75 76 int x86_fpu_save __read_mostly; 77 unsigned int x86_fpu_save_size __read_mostly = sizeof(struct save87); 78 uint64_t x86_xsave_features __read_mostly = 0; 79 size_t x86_xsave_offsets[XSAVE_MAX_COMPONENT+1] __read_mostly; 80 size_t x86_xsave_sizes[XSAVE_MAX_COMPONENT+1] __read_mostly; 81 82 /* 83 * Note: these are just the ones that may not have a cpuid instruction. 84 * We deal with the rest in a different way. 85 */ 86 const int i386_nocpuid_cpus[] = { 87 CPUVENDOR_INTEL, CPUCLASS_386, /* CPU_386SX */ 88 CPUVENDOR_INTEL, CPUCLASS_386, /* CPU_386 */ 89 CPUVENDOR_INTEL, CPUCLASS_486, /* CPU_486SX */ 90 CPUVENDOR_INTEL, CPUCLASS_486, /* CPU_486 */ 91 CPUVENDOR_CYRIX, CPUCLASS_486, /* CPU_486DLC */ 92 CPUVENDOR_CYRIX, CPUCLASS_486, /* CPU_6x86 */ 93 CPUVENDOR_NEXGEN, CPUCLASS_386, /* CPU_NX586 */ 94 }; 95 96 static const char cpu_vendor_names[][10] = { 97 "Unknown", "Intel", "NS/Cyrix", "NexGen", "AMD", "IDT/VIA", "Transmeta", 98 "Vortex86" 99 }; 100 101 static const struct x86_cache_info * 102 cache_info_lookup(const struct x86_cache_info *cai, uint8_t desc) 103 { 104 int i; 105 106 for (i = 0; cai[i].cai_desc != 0; i++) { 107 if (cai[i].cai_desc == desc) 108 return (&cai[i]); 109 } 110 111 return (NULL); 112 } 113 114 /* 115 * Get cache info from one of the following: 116 * Intel Deterministic Cache Parameter Leaf (0x04) 117 * AMD Cache Topology Information Leaf (0x8000001d) 118 */ 119 static void 120 cpu_dcp_cacheinfo(struct cpu_info *ci, uint32_t leaf) 121 { 122 u_int descs[4]; 123 int type, level, ways, partitions, linesize, sets, totalsize; 124 int caitype = -1; 125 int i; 126 127 for (i = 0; ; i++) { 128 x86_cpuid2(leaf, i, descs); 129 type = __SHIFTOUT(descs[0], CPUID_DCP_CACHETYPE); 130 if (type == CPUID_DCP_CACHETYPE_N) 131 break; 132 level = __SHIFTOUT(descs[0], CPUID_DCP_CACHELEVEL); 133 switch (level) { 134 case 1: 135 if (type == CPUID_DCP_CACHETYPE_I) 136 caitype = CAI_ICACHE; 137 else if (type == CPUID_DCP_CACHETYPE_D) 138 caitype = CAI_DCACHE; 139 else 140 caitype = -1; 141 break; 142 case 2: 143 if (type == CPUID_DCP_CACHETYPE_U) 144 caitype = CAI_L2CACHE; 145 else 146 caitype = -1; 147 break; 148 case 3: 149 if (type == CPUID_DCP_CACHETYPE_U) 150 caitype = CAI_L3CACHE; 151 else 152 caitype = -1; 153 break; 154 default: 155 caitype = -1; 156 break; 157 } 158 if (caitype == -1) 159 continue; 160 161 ways = __SHIFTOUT(descs[1], CPUID_DCP_WAYS) + 1; 162 partitions =__SHIFTOUT(descs[1], CPUID_DCP_PARTITIONS) 163 + 1; 164 linesize = __SHIFTOUT(descs[1], CPUID_DCP_LINESIZE) 165 + 1; 166 sets = descs[2] + 1; 167 totalsize = ways * partitions * linesize * sets; 168 ci->ci_cinfo[caitype].cai_totalsize = totalsize; 169 ci->ci_cinfo[caitype].cai_associativity = ways; 170 ci->ci_cinfo[caitype].cai_linesize = linesize; 171 } 172 } 173 174 static void 175 cpu_probe_intel_cache(struct cpu_info *ci) 176 { 177 const struct x86_cache_info *cai; 178 u_int descs[4]; 179 int iterations, i, j; 180 uint8_t desc; 181 182 if (cpuid_level >= 2) { 183 /* Parse the cache info from `cpuid leaf 2', if we have it. */ 184 x86_cpuid(2, descs); 185 iterations = descs[0] & 0xff; 186 while (iterations-- > 0) { 187 for (i = 0; i < 4; i++) { 188 if (descs[i] & 0x80000000) 189 continue; 190 for (j = 0; j < 4; j++) { 191 if (i == 0 && j == 0) 192 continue; 193 desc = (descs[i] >> (j * 8)) & 0xff; 194 if (desc == 0) 195 continue; 196 cai = cache_info_lookup( 197 intel_cpuid_cache_info, desc); 198 if (cai != NULL) { 199 ci->ci_cinfo[cai->cai_index] = 200 *cai; 201 } 202 } 203 } 204 } 205 } 206 207 if (cpuid_level < 4) 208 return; 209 210 /* Parse the cache info from `cpuid leaf 4', if we have it. */ 211 cpu_dcp_cacheinfo(ci, 4); 212 } 213 214 static void 215 cpu_probe_intel_errata(struct cpu_info *ci) 216 { 217 u_int family, model, stepping; 218 219 family = CPUID_TO_FAMILY(ci->ci_signature); 220 model = CPUID_TO_MODEL(ci->ci_signature); 221 stepping = CPUID_TO_STEPPING(ci->ci_signature); 222 223 if (family == 0x6 && model == 0x5C && stepping == 0x9) { /* Apollo Lake */ 224 wrmsr(MSR_MISC_ENABLE, 225 rdmsr(MSR_MISC_ENABLE) & ~IA32_MISC_MWAIT_EN); 226 227 cpu_feature[1] &= ~CPUID2_MONITOR; 228 ci->ci_feat_val[1] &= ~CPUID2_MONITOR; 229 } 230 } 231 232 static void 233 cpu_probe_intel(struct cpu_info *ci) 234 { 235 236 if (cpu_vendor != CPUVENDOR_INTEL) 237 return; 238 239 cpu_probe_intel_cache(ci); 240 cpu_probe_intel_errata(ci); 241 } 242 243 static void 244 cpu_probe_amd_cache(struct cpu_info *ci) 245 { 246 const struct x86_cache_info *cp; 247 struct x86_cache_info *cai; 248 int family, model; 249 u_int descs[4]; 250 u_int lfunc; 251 252 family = CPUID_TO_FAMILY(ci->ci_signature); 253 model = CPUID_TO_MODEL(ci->ci_signature); 254 255 /* K5 model 0 has none of this info. */ 256 if (family == 5 && model == 0) 257 return; 258 259 /* Determine the largest extended function value. */ 260 x86_cpuid(0x80000000, descs); 261 lfunc = descs[0]; 262 263 if (lfunc < 0x80000005) 264 return; 265 266 /* Determine L1 cache/TLB info. */ 267 x86_cpuid(0x80000005, descs); 268 269 /* K6-III and higher have large page TLBs. */ 270 if ((family == 5 && model >= 9) || family >= 6) { 271 cai = &ci->ci_cinfo[CAI_ITLB2]; 272 cai->cai_totalsize = AMD_L1_EAX_ITLB_ENTRIES(descs[0]); 273 cai->cai_associativity = AMD_L1_EAX_ITLB_ASSOC(descs[0]); 274 cai->cai_linesize = (4 * 1024 * 1024); 275 276 cai = &ci->ci_cinfo[CAI_DTLB2]; 277 cai->cai_totalsize = AMD_L1_EAX_DTLB_ENTRIES(descs[0]); 278 cai->cai_associativity = AMD_L1_EAX_DTLB_ASSOC(descs[0]); 279 cai->cai_linesize = (4 * 1024 * 1024); 280 } 281 282 cai = &ci->ci_cinfo[CAI_ITLB]; 283 cai->cai_totalsize = AMD_L1_EBX_ITLB_ENTRIES(descs[1]); 284 cai->cai_associativity = AMD_L1_EBX_ITLB_ASSOC(descs[1]); 285 cai->cai_linesize = (4 * 1024); 286 287 cai = &ci->ci_cinfo[CAI_DTLB]; 288 cai->cai_totalsize = AMD_L1_EBX_DTLB_ENTRIES(descs[1]); 289 cai->cai_associativity = AMD_L1_EBX_DTLB_ASSOC(descs[1]); 290 cai->cai_linesize = (4 * 1024); 291 292 cai = &ci->ci_cinfo[CAI_DCACHE]; 293 cai->cai_totalsize = AMD_L1_ECX_DC_SIZE(descs[2]); 294 cai->cai_associativity = AMD_L1_ECX_DC_ASSOC(descs[2]); 295 cai->cai_linesize = AMD_L1_ECX_DC_LS(descs[2]); 296 297 cai = &ci->ci_cinfo[CAI_ICACHE]; 298 cai->cai_totalsize = AMD_L1_EDX_IC_SIZE(descs[3]); 299 cai->cai_associativity = AMD_L1_EDX_IC_ASSOC(descs[3]); 300 cai->cai_linesize = AMD_L1_EDX_IC_LS(descs[3]); 301 302 if (lfunc < 0x80000006) 303 return; 304 305 /* Determine L2 cache/TLB info. */ 306 x86_cpuid(0x80000006, descs); 307 308 cai = &ci->ci_cinfo[CAI_L2CACHE]; 309 cai->cai_totalsize = AMD_L2_ECX_C_SIZE(descs[2]); 310 cai->cai_associativity = AMD_L2_ECX_C_ASSOC(descs[2]); 311 cai->cai_linesize = AMD_L2_ECX_C_LS(descs[2]); 312 313 cp = cache_info_lookup(amd_cpuid_l2l3cache_assoc_info, 314 cai->cai_associativity); 315 if (cp != NULL) 316 cai->cai_associativity = cp->cai_associativity; 317 else 318 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 319 320 if (family < 0xf) 321 return; 322 323 /* Determine L3 cache info on AMD Family 10h and newer processors */ 324 cai = &ci->ci_cinfo[CAI_L3CACHE]; 325 cai->cai_totalsize = AMD_L3_EDX_C_SIZE(descs[3]); 326 cai->cai_associativity = AMD_L3_EDX_C_ASSOC(descs[3]); 327 cai->cai_linesize = AMD_L3_EDX_C_LS(descs[3]); 328 329 cp = cache_info_lookup(amd_cpuid_l2l3cache_assoc_info, 330 cai->cai_associativity); 331 if (cp != NULL) 332 cai->cai_associativity = cp->cai_associativity; 333 else 334 cai->cai_associativity = 0; /* XXX Unknown reserved */ 335 336 if (lfunc < 0x80000019) 337 return; 338 339 /* Determine 1GB TLB info. */ 340 x86_cpuid(0x80000019, descs); 341 342 cai = &ci->ci_cinfo[CAI_L1_1GBDTLB]; 343 cai->cai_totalsize = AMD_L1_1GB_EAX_DTLB_ENTRIES(descs[1]); 344 cai->cai_associativity = AMD_L1_1GB_EAX_DTLB_ASSOC(descs[1]); 345 cai->cai_linesize = (1 * 1024); 346 347 cai = &ci->ci_cinfo[CAI_L1_1GBITLB]; 348 cai->cai_totalsize = AMD_L1_1GB_EAX_IUTLB_ENTRIES(descs[0]); 349 cai->cai_associativity = AMD_L1_1GB_EAX_IUTLB_ASSOC(descs[0]); 350 cai->cai_linesize = (1 * 1024); 351 352 cai = &ci->ci_cinfo[CAI_L2_1GBDTLB]; 353 cai->cai_totalsize = AMD_L2_1GB_EBX_DUTLB_ENTRIES(descs[1]); 354 cai->cai_associativity = AMD_L2_1GB_EBX_DUTLB_ASSOC(descs[1]); 355 cai->cai_linesize = (1 * 1024); 356 357 cai = &ci->ci_cinfo[CAI_L2_1GBITLB]; 358 cai->cai_totalsize = AMD_L2_1GB_EBX_IUTLB_ENTRIES(descs[0]); 359 cai->cai_associativity = AMD_L2_1GB_EBX_IUTLB_ASSOC(descs[0]); 360 cai->cai_linesize = (1 * 1024); 361 362 if (lfunc < 0x8000001d) 363 return; 364 365 if (ci->ci_feat_val[3] & CPUID_TOPOEXT) 366 cpu_dcp_cacheinfo(ci, 0x8000001d); 367 } 368 369 static void 370 cpu_probe_amd_errata(struct cpu_info *ci) 371 { 372 u_int model; 373 uint64_t val; 374 int flag; 375 376 model = CPUID_TO_MODEL(ci->ci_signature); 377 378 switch (CPUID_TO_FAMILY(ci->ci_signature)) { 379 case 0x05: /* K5 */ 380 if (model == 0) { 381 /* 382 * According to the AMD Processor Recognition App Note, 383 * the AMD-K5 Model 0 uses the wrong bit to indicate 384 * support for global PTEs, instead using bit 9 (APIC) 385 * rather than bit 13 (i.e. "0x200" vs. 0x2000"). 386 */ 387 flag = ci->ci_feat_val[0]; 388 if ((flag & CPUID_APIC) != 0) 389 flag = (flag & ~CPUID_APIC) | CPUID_PGE; 390 ci->ci_feat_val[0] = flag; 391 } 392 break; 393 394 case 0x10: /* Family 10h */ 395 /* 396 * On Family 10h, certain BIOSes do not enable WC+ support. 397 * This causes WC+ to become CD, and degrades guest 398 * performance at the NPT level. 399 * 400 * Explicitly enable WC+ if we're not a guest. 401 */ 402 if (!ISSET(ci->ci_feat_val[1], CPUID2_RAZ)) { 403 val = rdmsr(MSR_BU_CFG2); 404 val &= ~BU_CFG2_CWPLUS_DIS; 405 wrmsr(MSR_BU_CFG2, val); 406 } 407 break; 408 409 case 0x17: 410 /* 411 * "Revision Guide for AMD Family 17h Models 00h-0Fh 412 * Processors" revision 1.12: 413 * 414 * 1057 MWAIT or MWAITX Instructions May Fail to Correctly 415 * Exit From the Monitor Event Pending State 416 * 417 * 1109 MWAIT Instruction May Hang a Thread 418 */ 419 if (model == 0x01) { 420 cpu_feature[1] &= ~CPUID2_MONITOR; 421 ci->ci_feat_val[1] &= ~CPUID2_MONITOR; 422 } 423 break; 424 } 425 } 426 427 static void 428 cpu_probe_amd(struct cpu_info *ci) 429 { 430 431 if (cpu_vendor != CPUVENDOR_AMD) 432 return; 433 434 cpu_probe_amd_cache(ci); 435 cpu_probe_amd_errata(ci); 436 } 437 438 static inline uint8_t 439 cyrix_read_reg(uint8_t reg) 440 { 441 442 outb(0x22, reg); 443 return inb(0x23); 444 } 445 446 static inline void 447 cyrix_write_reg(uint8_t reg, uint8_t data) 448 { 449 450 outb(0x22, reg); 451 outb(0x23, data); 452 } 453 454 static void 455 cpu_probe_cyrix_cmn(struct cpu_info *ci) 456 { 457 /* 458 * i8254 latch check routine: 459 * National Geode (formerly Cyrix MediaGX) has a serious bug in 460 * its built-in i8254-compatible clock module (cs5510 cs5520). 461 * Set the variable 'clock_broken_latch' to indicate it. 462 * 463 * This bug is not present in the cs5530, and the flag 464 * is disabled again in sys/arch/i386/pci/pcib.c if this later 465 * model device is detected. Ideally, this work-around should not 466 * even be in here, it should be in there. XXX 467 */ 468 uint8_t c3; 469 #ifndef XENPV 470 extern int clock_broken_latch; 471 472 switch (ci->ci_signature) { 473 case 0x440: /* Cyrix MediaGX */ 474 case 0x540: /* GXm */ 475 clock_broken_latch = 1; 476 break; 477 } 478 #endif 479 480 /* set up various cyrix registers */ 481 /* 482 * Enable suspend on halt (powersave mode). 483 * When powersave mode is enabled, the TSC stops counting 484 * while the CPU is halted in idle() waiting for an interrupt. 485 * This means we can't use the TSC for interval time in 486 * microtime(9), and thus it is disabled here. 487 * 488 * It still makes a perfectly good cycle counter 489 * for program profiling, so long as you remember you're 490 * counting cycles, and not time. Further, if you don't 491 * mind not using powersave mode, the TSC works just fine, 492 * so this should really be optional. XXX 493 */ 494 cyrix_write_reg(0xc2, cyrix_read_reg(0xc2) | 0x08); 495 496 /* 497 * Do not disable the TSC on the Geode GX, it's reported to 498 * work fine. 499 */ 500 if (ci->ci_signature != 0x552) 501 ci->ci_feat_val[0] &= ~CPUID_TSC; 502 503 /* enable access to ccr4/ccr5 */ 504 c3 = cyrix_read_reg(0xC3); 505 cyrix_write_reg(0xC3, c3 | 0x10); 506 /* cyrix's workaround for the "coma bug" */ 507 cyrix_write_reg(0x31, cyrix_read_reg(0x31) | 0xf8); 508 cyrix_write_reg(0x32, cyrix_read_reg(0x32) | 0x7f); 509 cyrix_write_reg(0x33, cyrix_read_reg(0x33) & ~0xff); 510 cyrix_write_reg(0x3c, cyrix_read_reg(0x3c) | 0x87); 511 /* disable access to ccr4/ccr5 */ 512 cyrix_write_reg(0xC3, c3); 513 } 514 515 static void 516 cpu_probe_cyrix(struct cpu_info *ci) 517 { 518 519 if (cpu_vendor != CPUVENDOR_CYRIX || 520 CPUID_TO_FAMILY(ci->ci_signature) < 4 || 521 CPUID_TO_FAMILY(ci->ci_signature) > 6) 522 return; 523 524 cpu_probe_cyrix_cmn(ci); 525 } 526 527 static void 528 cpu_probe_winchip(struct cpu_info *ci) 529 { 530 531 if (cpu_vendor != CPUVENDOR_IDT || 532 CPUID_TO_FAMILY(ci->ci_signature) != 5) 533 return; 534 535 /* WinChip C6 */ 536 if (CPUID_TO_MODEL(ci->ci_signature) == 4) 537 ci->ci_feat_val[0] &= ~CPUID_TSC; 538 } 539 540 static void 541 cpu_probe_c3(struct cpu_info *ci) 542 { 543 u_int family, model, stepping, descs[4], lfunc, msr; 544 struct x86_cache_info *cai; 545 546 if (cpu_vendor != CPUVENDOR_IDT || 547 CPUID_TO_FAMILY(ci->ci_signature) < 6) 548 return; 549 550 family = CPUID_TO_FAMILY(ci->ci_signature); 551 model = CPUID_TO_MODEL(ci->ci_signature); 552 stepping = CPUID_TO_STEPPING(ci->ci_signature); 553 554 /* Determine the largest extended function value. */ 555 x86_cpuid(0x80000000, descs); 556 lfunc = descs[0]; 557 558 if (family == 6) { 559 /* 560 * VIA Eden ESP. 561 * 562 * Quoting from page 3-4 of: "VIA Eden ESP Processor Datasheet" 563 * http://www.via.com.tw/download/mainboards/6/14/Eden20v115.pdf 564 * 565 * 1. The CMPXCHG8B instruction is provided and always enabled, 566 * however, it appears disabled in the corresponding CPUID 567 * function bit 0 to avoid a bug in an early version of 568 * Windows NT. However, this default can be changed via a 569 * bit in the FCR MSR. 570 */ 571 ci->ci_feat_val[0] |= CPUID_CX8; 572 wrmsr(MSR_VIA_FCR, rdmsr(MSR_VIA_FCR) | VIA_ACE_ECX8); 573 } 574 575 if (family > 6 || model > 0x9 || (model == 0x9 && stepping >= 3)) { 576 /* VIA Nehemiah or Esther. */ 577 x86_cpuid(0xc0000000, descs); 578 lfunc = descs[0]; 579 if (lfunc >= 0xc0000001) { /* has ACE, RNG */ 580 int rng_enable = 0, ace_enable = 0; 581 x86_cpuid(0xc0000001, descs); 582 lfunc = descs[3]; 583 ci->ci_feat_val[4] = lfunc; 584 /* Check for and enable RNG */ 585 if (lfunc & CPUID_VIA_HAS_RNG) { 586 if (!(lfunc & CPUID_VIA_DO_RNG)) { 587 rng_enable++; 588 ci->ci_feat_val[4] |= CPUID_VIA_DO_RNG; 589 } 590 } 591 /* Check for and enable ACE (AES-CBC) */ 592 if (lfunc & CPUID_VIA_HAS_ACE) { 593 if (!(lfunc & CPUID_VIA_DO_ACE)) { 594 ace_enable++; 595 ci->ci_feat_val[4] |= CPUID_VIA_DO_ACE; 596 } 597 } 598 /* Check for and enable SHA */ 599 if (lfunc & CPUID_VIA_HAS_PHE) { 600 if (!(lfunc & CPUID_VIA_DO_PHE)) { 601 ace_enable++; 602 ci->ci_feat_val[4] |= CPUID_VIA_DO_PHE; 603 } 604 } 605 /* Check for and enable ACE2 (AES-CTR) */ 606 if (lfunc & CPUID_VIA_HAS_ACE2) { 607 if (!(lfunc & CPUID_VIA_DO_ACE2)) { 608 ace_enable++; 609 ci->ci_feat_val[4] |= CPUID_VIA_DO_ACE2; 610 } 611 } 612 /* Check for and enable PMM (modmult engine) */ 613 if (lfunc & CPUID_VIA_HAS_PMM) { 614 if (!(lfunc & CPUID_VIA_DO_PMM)) { 615 ace_enable++; 616 ci->ci_feat_val[4] |= CPUID_VIA_DO_PMM; 617 } 618 } 619 620 /* 621 * Actually do the enables. It's a little gross, 622 * but per the PadLock programming guide, "Enabling 623 * PadLock", condition 3, we must enable SSE too or 624 * else the first use of RNG or ACE instructions 625 * will generate a trap. 626 * 627 * We must do this early because of kernel RNG 628 * initialization but it is safe without the full 629 * FPU-detect as all these CPUs have SSE. 630 */ 631 lcr4(rcr4() | CR4_OSFXSR); 632 633 if (rng_enable) { 634 msr = rdmsr(MSR_VIA_RNG); 635 msr |= MSR_VIA_RNG_ENABLE; 636 /* C7 stepping 8 and subsequent CPUs have dual RNG */ 637 if (model > 0xA || (model == 0xA && stepping > 0x7)) { 638 msr |= MSR_VIA_RNG_2NOISE; 639 } 640 wrmsr(MSR_VIA_RNG, msr); 641 } 642 643 if (ace_enable) { 644 msr = rdmsr(MSR_VIA_ACE); 645 wrmsr(MSR_VIA_ACE, msr | VIA_ACE_ENABLE); 646 } 647 } 648 } 649 650 /* Explicitly disable unsafe ALTINST mode. */ 651 if (ci->ci_feat_val[4] & CPUID_VIA_DO_ACE) { 652 msr = rdmsr(MSR_VIA_ACE); 653 wrmsr(MSR_VIA_ACE, msr & ~VIA_ACE_ALTINST); 654 } 655 656 /* 657 * Determine L1 cache/TLB info. 658 */ 659 if (lfunc < 0x80000005) { 660 /* No L1 cache info available. */ 661 return; 662 } 663 664 x86_cpuid(0x80000005, descs); 665 666 cai = &ci->ci_cinfo[CAI_ITLB]; 667 cai->cai_totalsize = VIA_L1_EBX_ITLB_ENTRIES(descs[1]); 668 cai->cai_associativity = VIA_L1_EBX_ITLB_ASSOC(descs[1]); 669 cai->cai_linesize = (4 * 1024); 670 671 cai = &ci->ci_cinfo[CAI_DTLB]; 672 cai->cai_totalsize = VIA_L1_EBX_DTLB_ENTRIES(descs[1]); 673 cai->cai_associativity = VIA_L1_EBX_DTLB_ASSOC(descs[1]); 674 cai->cai_linesize = (4 * 1024); 675 676 cai = &ci->ci_cinfo[CAI_DCACHE]; 677 cai->cai_totalsize = VIA_L1_ECX_DC_SIZE(descs[2]); 678 cai->cai_associativity = VIA_L1_ECX_DC_ASSOC(descs[2]); 679 cai->cai_linesize = VIA_L1_EDX_IC_LS(descs[2]); 680 if (family == 6 && model == 9 && stepping == 8) { 681 /* Erratum: stepping 8 reports 4 when it should be 2 */ 682 cai->cai_associativity = 2; 683 } 684 685 cai = &ci->ci_cinfo[CAI_ICACHE]; 686 cai->cai_totalsize = VIA_L1_EDX_IC_SIZE(descs[3]); 687 cai->cai_associativity = VIA_L1_EDX_IC_ASSOC(descs[3]); 688 cai->cai_linesize = VIA_L1_EDX_IC_LS(descs[3]); 689 if (family == 6 && model == 9 && stepping == 8) { 690 /* Erratum: stepping 8 reports 4 when it should be 2 */ 691 cai->cai_associativity = 2; 692 } 693 694 /* 695 * Determine L2 cache/TLB info. 696 */ 697 if (lfunc < 0x80000006) { 698 /* No L2 cache info available. */ 699 return; 700 } 701 702 x86_cpuid(0x80000006, descs); 703 704 cai = &ci->ci_cinfo[CAI_L2CACHE]; 705 if (family > 6 || model >= 9) { 706 cai->cai_totalsize = VIA_L2N_ECX_C_SIZE(descs[2]); 707 cai->cai_associativity = VIA_L2N_ECX_C_ASSOC(descs[2]); 708 cai->cai_linesize = VIA_L2N_ECX_C_LS(descs[2]); 709 } else { 710 cai->cai_totalsize = VIA_L2_ECX_C_SIZE(descs[2]); 711 cai->cai_associativity = VIA_L2_ECX_C_ASSOC(descs[2]); 712 cai->cai_linesize = VIA_L2_ECX_C_LS(descs[2]); 713 } 714 } 715 716 static void 717 cpu_probe_geode(struct cpu_info *ci) 718 { 719 720 if (memcmp("Geode by NSC", ci->ci_vendor, 12) != 0 || 721 CPUID_TO_FAMILY(ci->ci_signature) != 5) 722 return; 723 724 cpu_probe_cyrix_cmn(ci); 725 cpu_probe_amd_cache(ci); 726 } 727 728 static void 729 cpu_probe_vortex86(struct cpu_info *ci) 730 { 731 #define PCI_MODE1_ADDRESS_REG 0x0cf8 732 #define PCI_MODE1_DATA_REG 0x0cfc 733 #define PCI_MODE1_ENABLE 0x80000000UL 734 735 uint32_t reg, idx; 736 737 if (cpu_vendor != CPUVENDOR_VORTEX86) 738 return; 739 /* 740 * CPU model available from "Customer ID register" in 741 * North Bridge Function 0 PCI space 742 * we can't use pci_conf_read() because the PCI subsystem is not 743 * not initialised early enough 744 */ 745 746 outl(PCI_MODE1_ADDRESS_REG, PCI_MODE1_ENABLE | 0x90); 747 reg = inl(PCI_MODE1_DATA_REG); 748 749 if ((reg & 0xf0ffffff) != 0x30504d44) { 750 idx = 0; 751 } else { 752 idx = (reg >> 24) & 0xf; 753 } 754 755 static const char *cpu_vortex86_flavor[] = { 756 "??", "SX", "DX", "MX", "DX2", "MX+", "DX3", "EX", "EX2", 757 }; 758 idx = idx < __arraycount(cpu_vortex86_flavor) ? idx : 0; 759 snprintf(cpu_brand_string, sizeof(cpu_brand_string), "Vortex86%s", 760 cpu_vortex86_flavor[idx]); 761 762 #undef PCI_MODE1_ENABLE 763 #undef PCI_MODE1_ADDRESS_REG 764 #undef PCI_MODE1_DATA_REG 765 } 766 767 static void 768 cpu_probe_fpu_old(struct cpu_info *ci) 769 { 770 #if defined(__i386__) && !defined(XENPV) 771 772 clts(); 773 fninit(); 774 775 /* Check for 'FDIV' bug on the original Pentium */ 776 if (npx586bug1(4195835, 3145727) != 0) 777 /* NB 120+MHz cpus are not affected */ 778 i386_fpu_fdivbug = 1; 779 780 stts(); 781 #endif 782 } 783 784 static void 785 cpu_probe_fpu(struct cpu_info *ci) 786 { 787 u_int descs[4]; 788 int i; 789 790 x86_fpu_save = FPU_SAVE_FSAVE; 791 792 #ifdef i386 793 /* If we have FXSAVE/FXRESTOR, use them. */ 794 if ((ci->ci_feat_val[0] & CPUID_FXSR) == 0) { 795 i386_use_fxsave = 0; 796 cpu_probe_fpu_old(ci); 797 return; 798 } 799 800 i386_use_fxsave = 1; 801 /* 802 * If we have SSE/SSE2, enable XMM exceptions, and 803 * notify userland. 804 */ 805 if (ci->ci_feat_val[0] & CPUID_SSE) 806 i386_has_sse = 1; 807 if (ci->ci_feat_val[0] & CPUID_SSE2) 808 i386_has_sse2 = 1; 809 #else 810 /* 811 * For amd64 i386_use_fxsave, i386_has_sse and i386_has_sse2 are 812 * #defined to 1, because fxsave/sse/sse2 are always present. 813 */ 814 #endif 815 816 x86_fpu_save = FPU_SAVE_FXSAVE; 817 x86_fpu_save_size = sizeof(struct fxsave); 818 819 /* See if XSAVE is supported */ 820 if ((ci->ci_feat_val[1] & CPUID2_XSAVE) == 0) 821 return; 822 823 #ifdef XENPV 824 /* 825 * Xen kernel can disable XSAVE via "no-xsave" option, in that case 826 * the XSAVE/XRSTOR instructions become privileged and trigger 827 * supervisor trap. OSXSAVE flag seems to be reliably set according 828 * to whether XSAVE is actually available. 829 */ 830 if ((ci->ci_feat_val[1] & CPUID2_OSXSAVE) == 0) 831 return; 832 #endif 833 834 x86_fpu_save = FPU_SAVE_XSAVE; 835 836 x86_cpuid2(0xd, 1, descs); 837 if (descs[0] & CPUID_PES1_XSAVEOPT) 838 x86_fpu_save = FPU_SAVE_XSAVEOPT; 839 840 /* Get features and maximum size of the save area */ 841 x86_cpuid(0xd, descs); 842 if (descs[2] > sizeof(struct fxsave)) 843 x86_fpu_save_size = descs[2]; 844 845 x86_xsave_features = (uint64_t)descs[3] << 32 | descs[0]; 846 847 /* Get component offsets and sizes for the save area */ 848 for (i = XSAVE_YMM_Hi128; i < __arraycount(x86_xsave_offsets); i++) { 849 if (x86_xsave_features & __BIT(i)) { 850 x86_cpuid2(0xd, i, descs); 851 x86_xsave_offsets[i] = descs[1]; 852 x86_xsave_sizes[i] = descs[0]; 853 } 854 } 855 } 856 857 void 858 cpu_probe(struct cpu_info *ci) 859 { 860 u_int descs[4]; 861 int i; 862 uint32_t miscbytes; 863 uint32_t brand[12]; 864 865 if (ci == &cpu_info_primary) { 866 cpu_vendor = i386_nocpuid_cpus[cputype << 1]; 867 cpu_class = i386_nocpuid_cpus[(cputype << 1) + 1]; 868 } 869 870 if (cpuid_level < 0) { 871 /* cpuid instruction not supported */ 872 cpu_probe_fpu_old(ci); 873 return; 874 } 875 876 for (i = 0; i < __arraycount(ci->ci_feat_val); i++) { 877 ci->ci_feat_val[i] = 0; 878 } 879 880 x86_cpuid(0, descs); 881 cpuid_level = descs[0]; 882 ci->ci_max_cpuid = descs[0]; 883 884 ci->ci_vendor[0] = descs[1]; 885 ci->ci_vendor[2] = descs[2]; 886 ci->ci_vendor[1] = descs[3]; 887 ci->ci_vendor[3] = 0; 888 889 if (ci == &cpu_info_primary) { 890 if (memcmp(ci->ci_vendor, "GenuineIntel", 12) == 0) 891 cpu_vendor = CPUVENDOR_INTEL; 892 else if (memcmp(ci->ci_vendor, "AuthenticAMD", 12) == 0) 893 cpu_vendor = CPUVENDOR_AMD; 894 else if (memcmp(ci->ci_vendor, "CyrixInstead", 12) == 0) 895 cpu_vendor = CPUVENDOR_CYRIX; 896 else if (memcmp(ci->ci_vendor, "Geode by NSC", 12) == 0) 897 cpu_vendor = CPUVENDOR_CYRIX; 898 else if (memcmp(ci->ci_vendor, "CentaurHauls", 12) == 0) 899 cpu_vendor = CPUVENDOR_IDT; 900 else if (memcmp(ci->ci_vendor, "GenuineTMx86", 12) == 0) 901 cpu_vendor = CPUVENDOR_TRANSMETA; 902 else if (memcmp(ci->ci_vendor, "Vortex86 SoC", 12) == 0) 903 cpu_vendor = CPUVENDOR_VORTEX86; 904 else 905 cpu_vendor = CPUVENDOR_UNKNOWN; 906 } 907 908 if (cpuid_level >= 1) { 909 x86_cpuid(1, descs); 910 ci->ci_signature = descs[0]; 911 miscbytes = descs[1]; 912 ci->ci_feat_val[1] = descs[2]; 913 ci->ci_feat_val[0] = descs[3]; 914 915 if (ci == &cpu_info_primary) { 916 /* Determine family + class. */ 917 cpu_class = CPUID_TO_FAMILY(ci->ci_signature) 918 + (CPUCLASS_386 - 3); 919 if (cpu_class > CPUCLASS_686) 920 cpu_class = CPUCLASS_686; 921 } 922 923 /* CLFLUSH line size is next 8 bits */ 924 if (ci->ci_feat_val[0] & CPUID_CFLUSH) 925 ci->ci_cflush_lsize 926 = __SHIFTOUT(miscbytes, CPUID_CLFLUSH_SIZE) << 3; 927 ci->ci_initapicid = __SHIFTOUT(miscbytes, CPUID_LOCAL_APIC_ID); 928 } 929 930 /* 931 * Get the basic information from the extended cpuid leafs. 932 * These were first implemented by amd, but most of the values 933 * match with those generated by modern intel cpus. 934 */ 935 x86_cpuid(0x80000000, descs); 936 if (descs[0] >= 0x80000000) 937 ci->ci_max_ext_cpuid = descs[0]; 938 else 939 ci->ci_max_ext_cpuid = 0; 940 941 if (ci->ci_max_ext_cpuid >= 0x80000001) { 942 /* Determine the extended feature flags. */ 943 x86_cpuid(0x80000001, descs); 944 ci->ci_feat_val[3] = descs[2]; /* %ecx */ 945 ci->ci_feat_val[2] = descs[3]; /* %edx */ 946 } 947 948 if (ci->ci_max_ext_cpuid >= 0x80000004) { 949 x86_cpuid(0x80000002, brand); 950 x86_cpuid(0x80000003, brand + 4); 951 x86_cpuid(0x80000004, brand + 8); 952 /* Skip leading spaces on brand */ 953 for (i = 0; i < 48; i++) { 954 if (((char *) brand)[i] != ' ') 955 break; 956 } 957 memcpy(cpu_brand_string, ((char *) brand) + i, 48 - i); 958 } 959 960 /* 961 * Get the structured extended features. 962 */ 963 if (cpuid_level >= 7) { 964 x86_cpuid(7, descs); 965 ci->ci_feat_val[5] = descs[1]; /* %ebx */ 966 ci->ci_feat_val[6] = descs[2]; /* %ecx */ 967 ci->ci_feat_val[7] = descs[3]; /* %edx */ 968 } 969 970 cpu_probe_intel(ci); 971 cpu_probe_amd(ci); 972 cpu_probe_cyrix(ci); 973 cpu_probe_winchip(ci); 974 cpu_probe_c3(ci); 975 cpu_probe_geode(ci); 976 cpu_probe_vortex86(ci); 977 978 if (ci == &cpu_info_primary) { 979 cpu_probe_fpu(ci); 980 } 981 982 #ifndef XENPV 983 x86_cpu_topology(ci); 984 #endif 985 986 if (cpu_vendor != CPUVENDOR_AMD && (ci->ci_feat_val[0] & CPUID_TM) && 987 (rdmsr(MSR_MISC_ENABLE) & (1 << 3)) == 0) { 988 /* Enable thermal monitor 1. */ 989 wrmsr(MSR_MISC_ENABLE, rdmsr(MSR_MISC_ENABLE) | (1<<3)); 990 } 991 992 ci->ci_feat_val[0] &= ~CPUID_FEAT_BLACKLIST; 993 if (ci == &cpu_info_primary) { 994 /* If first. Boot Processor is the cpu_feature reference. */ 995 for (i = 0; i < __arraycount(cpu_feature); i++) { 996 cpu_feature[i] = ci->ci_feat_val[i]; 997 } 998 identify_hypervisor(); 999 #ifndef XENPV 1000 /* Early patch of text segment. */ 1001 x86_patch(true); 1002 #endif 1003 #ifdef __x86_64__ /* not yet implemented on i386 */ 1004 if (cpu_feature[1] & CPUID2_AES) 1005 aes_md_init(&aes_ni_impl); 1006 else 1007 #endif 1008 if (cpu_feature[4] & CPUID_VIA_HAS_ACE) 1009 aes_md_init(&aes_via_impl); 1010 else if (i386_has_sse && i386_has_sse2 && 1011 (cpu_feature[1] & CPUID2_SSE3) && 1012 (cpu_feature[1] & CPUID2_SSSE3)) 1013 aes_md_init(&aes_ssse3_impl); 1014 else if (i386_has_sse && i386_has_sse2) 1015 aes_md_init(&aes_sse2_impl); 1016 } else { 1017 /* 1018 * If not first. Warn about cpu_feature mismatch for 1019 * secondary CPUs. 1020 */ 1021 for (i = 0; i < __arraycount(cpu_feature); i++) { 1022 if (cpu_feature[i] != ci->ci_feat_val[i]) 1023 aprint_error_dev(ci->ci_dev, 1024 "feature mismatch: cpu_feature[%d] is " 1025 "%#x, but CPU reported %#x\n", 1026 i, cpu_feature[i], ci->ci_feat_val[i]); 1027 } 1028 } 1029 } 1030 1031 /* Write what we know about the cpu to the console... */ 1032 void 1033 cpu_identify(struct cpu_info *ci) 1034 { 1035 1036 cpu_setmodel("%s %d86-class", 1037 cpu_vendor_names[cpu_vendor], cpu_class + 3); 1038 if (cpu_brand_string[0] != '\0') { 1039 aprint_normal_dev(ci->ci_dev, "%s", cpu_brand_string); 1040 } else { 1041 aprint_normal_dev(ci->ci_dev, "%s", cpu_getmodel()); 1042 if (ci->ci_data.cpu_cc_freq != 0) 1043 aprint_normal(", %dMHz", 1044 (int)(ci->ci_data.cpu_cc_freq / 1000000)); 1045 } 1046 if (ci->ci_signature != 0) 1047 aprint_normal(", id 0x%x", ci->ci_signature); 1048 aprint_normal("\n"); 1049 aprint_normal_dev(ci->ci_dev, "node %u, package %u, core %u, smt %u\n", 1050 ci->ci_numa_id, ci->ci_package_id, ci->ci_core_id, ci->ci_smt_id); 1051 if (cpu_brand_string[0] == '\0') { 1052 strlcpy(cpu_brand_string, cpu_getmodel(), 1053 sizeof(cpu_brand_string)); 1054 } 1055 if (cpu_class == CPUCLASS_386) { 1056 panic("NetBSD requires an 80486DX or later processor"); 1057 } 1058 if (cputype == CPU_486DLC) { 1059 aprint_error("WARNING: BUGGY CYRIX CACHE\n"); 1060 } 1061 1062 #if !defined(XENPV) || defined(DOM0OPS) /* on Xen PV rdmsr is for Dom0 only */ 1063 if (cpu_vendor == CPUVENDOR_AMD /* check enablement of an */ 1064 && device_unit(ci->ci_dev) == 0 /* AMD feature only once */ 1065 && ((cpu_feature[3] & CPUID_SVM) == CPUID_SVM)) { 1066 uint64_t val; 1067 1068 val = rdmsr(MSR_VMCR); 1069 if (((val & VMCR_SVMED) == VMCR_SVMED) 1070 && ((val & VMCR_LOCK) == VMCR_LOCK)) { 1071 aprint_normal_dev(ci->ci_dev, 1072 "SVM disabled by the BIOS\n"); 1073 } 1074 } 1075 #endif 1076 1077 #ifdef i386 1078 if (i386_fpu_fdivbug == 1) 1079 aprint_normal_dev(ci->ci_dev, 1080 "WARNING: Pentium FDIV bug detected!\n"); 1081 1082 if (cpu_vendor == CPUVENDOR_TRANSMETA) { 1083 u_int descs[4]; 1084 x86_cpuid(0x80860000, descs); 1085 if (descs[0] >= 0x80860007) 1086 /* Create longrun sysctls */ 1087 tmx86_init_longrun(); 1088 } 1089 #endif /* i386 */ 1090 1091 } 1092 1093 /* 1094 * Hypervisor 1095 */ 1096 vm_guest_t vm_guest = VM_GUEST_NO; 1097 1098 static const char * const vm_bios_vendors[] = { 1099 "QEMU", /* QEMU */ 1100 "Plex86", /* Plex86 */ 1101 "Bochs", /* Bochs */ 1102 "Xen", /* Xen */ 1103 "BHYVE", /* bhyve */ 1104 "Seabios", /* KVM */ 1105 }; 1106 1107 static const char * const vm_system_products[] = { 1108 "VMware Virtual Platform", /* VMWare VM */ 1109 "Virtual Machine", /* Microsoft VirtualPC */ 1110 "VirtualBox", /* Sun xVM VirtualBox */ 1111 "Parallels Virtual Platform", /* Parallels VM */ 1112 "KVM", /* KVM */ 1113 }; 1114 1115 void 1116 identify_hypervisor(void) 1117 { 1118 u_int regs[6]; 1119 char hv_vendor[12]; 1120 const char *p; 1121 int i; 1122 1123 if (vm_guest != VM_GUEST_NO) 1124 return; 1125 1126 /* 1127 * [RFC] CPUID usage for interaction between Hypervisors and Linux. 1128 * http://lkml.org/lkml/2008/10/1/246 1129 * 1130 * KB1009458: Mechanisms to determine if software is running in 1131 * a VMware virtual machine 1132 * http://kb.vmware.com/kb/1009458 1133 */ 1134 if (ISSET(cpu_feature[1], CPUID2_RAZ)) { 1135 vm_guest = VM_GUEST_VM; 1136 x86_cpuid(0x40000000, regs); 1137 if (regs[0] >= 0x40000000) { 1138 memcpy(&hv_vendor[0], ®s[1], sizeof(*regs)); 1139 memcpy(&hv_vendor[4], ®s[2], sizeof(*regs)); 1140 memcpy(&hv_vendor[8], ®s[3], sizeof(*regs)); 1141 if (memcmp(hv_vendor, "VMwareVMware", 12) == 0) 1142 vm_guest = VM_GUEST_VMWARE; 1143 else if (memcmp(hv_vendor, "Microsoft Hv", 12) == 0) { 1144 vm_guest = VM_GUEST_HV; 1145 #if NHYPERV > 0 1146 hyperv_early_init(); 1147 #endif 1148 } else if (memcmp(hv_vendor, "KVMKVMKVM\0\0\0", 12) == 0) 1149 vm_guest = VM_GUEST_KVM; 1150 else if (memcmp(hv_vendor, "XenVMMXenVMM", 12) == 0) 1151 vm_guest = VM_GUEST_XENHVM; 1152 /* FreeBSD bhyve: "bhyve bhyve " */ 1153 /* OpenBSD vmm: "OpenBSDVMM58" */ 1154 /* NetBSD nvmm: "___ NVMM ___" */ 1155 } 1156 return; 1157 } 1158 1159 /* 1160 * Examine SMBIOS strings for older hypervisors. 1161 */ 1162 p = pmf_get_platform("system-serial"); 1163 if (p != NULL) { 1164 if (strncmp(p, "VMware-", 7) == 0 || strncmp(p, "VMW", 3) == 0) { 1165 vmt_hvcall(VM_CMD_GET_VERSION, regs); 1166 if (regs[1] == VM_MAGIC) { 1167 vm_guest = VM_GUEST_VMWARE; 1168 return; 1169 } 1170 } 1171 } 1172 p = pmf_get_platform("bios-vendor"); 1173 if (p != NULL) { 1174 for (i = 0; i < __arraycount(vm_bios_vendors); i++) { 1175 if (strcmp(p, vm_bios_vendors[i]) == 0) { 1176 vm_guest = VM_GUEST_VM; 1177 return; 1178 } 1179 } 1180 } 1181 p = pmf_get_platform("system-product"); 1182 if (p != NULL) { 1183 for (i = 0; i < __arraycount(vm_system_products); i++) { 1184 if (strcmp(p, vm_system_products[i]) == 0) { 1185 vm_guest = VM_GUEST_VM; 1186 return; 1187 } 1188 } 1189 } 1190 } 1191