1 /* $NetBSD: identcpu.c,v 1.130 2024/07/01 19:40:03 andvar Exp $ */ 2 3 /*- 4 * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Frank van der Linden, and by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: identcpu.c,v 1.130 2024/07/01 19:40:03 andvar Exp $"); 34 35 #include "opt_xen.h" 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/device.h> 40 #include <sys/cpu.h> 41 42 #include <crypto/aes/aes_impl.h> 43 #include <crypto/aes/arch/x86/aes_ni.h> 44 #include <crypto/aes/arch/x86/aes_sse2.h> 45 #include <crypto/aes/arch/x86/aes_ssse3.h> 46 #include <crypto/aes/arch/x86/aes_via.h> 47 #include <crypto/chacha/chacha_impl.h> 48 #include <crypto/chacha/arch/x86/chacha_sse2.h> 49 50 #include <uvm/uvm_extern.h> 51 52 #include <machine/specialreg.h> 53 #include <machine/pio.h> 54 #include <machine/cpu.h> 55 56 #include <x86/cputypes.h> 57 #include <x86/cacheinfo.h> 58 #include <x86/cpuvar.h> 59 #include <x86/fpu.h> 60 61 #include <dev/vmt/vmtreg.h> /* for vmt_hvcall() */ 62 #include <dev/vmt/vmtvar.h> /* for vmt_hvcall() */ 63 64 #ifndef XENPV 65 #include "hyperv.h" 66 #if NHYPERV > 0 67 #include <x86/x86/hypervvar.h> 68 #endif 69 #endif 70 71 static const struct x86_cache_info intel_cpuid_cache_info[] = INTEL_CACHE_INFO; 72 73 static const struct x86_cache_info amd_cpuid_l2l3cache_assoc_info[] = 74 AMD_L2L3CACHE_INFO; 75 76 int cpu_vendor; 77 char cpu_brand_string[49]; 78 79 int x86_fpu_save __read_mostly; 80 unsigned int x86_fpu_save_size __read_mostly = sizeof(struct save87); 81 uint64_t x86_xsave_features __read_mostly = 0; 82 size_t x86_xsave_offsets[XSAVE_MAX_COMPONENT+1] __read_mostly; 83 size_t x86_xsave_sizes[XSAVE_MAX_COMPONENT+1] __read_mostly; 84 85 /* 86 * Note: these are just the ones that may not have a cpuid instruction. 87 * We deal with the rest in a different way. 88 */ 89 const int i386_nocpuid_cpus[] = { 90 CPUVENDOR_INTEL, CPUCLASS_386, /* CPU_386SX */ 91 CPUVENDOR_INTEL, CPUCLASS_386, /* CPU_386 */ 92 CPUVENDOR_INTEL, CPUCLASS_486, /* CPU_486SX */ 93 CPUVENDOR_INTEL, CPUCLASS_486, /* CPU_486 */ 94 CPUVENDOR_CYRIX, CPUCLASS_486, /* CPU_486DLC */ 95 CPUVENDOR_CYRIX, CPUCLASS_486, /* CPU_6x86 */ 96 CPUVENDOR_NEXGEN, CPUCLASS_386, /* CPU_NX586 */ 97 }; 98 99 static const char cpu_vendor_names[][10] = { 100 "Unknown", "Intel", "NS/Cyrix", "NexGen", "AMD", "IDT/VIA", "Transmeta", 101 "Vortex86" 102 }; 103 104 static void 105 cpu_probe_intel_cache(struct cpu_info *ci) 106 { 107 const struct x86_cache_info *cai; 108 u_int descs[4]; 109 int iterations, i, j; 110 uint8_t desc; 111 112 if (cpuid_level >= 2) { 113 /* Parse the cache info from `cpuid leaf 2', if we have it. */ 114 x86_cpuid(2, descs); 115 iterations = descs[0] & 0xff; 116 while (iterations-- > 0) { 117 for (i = 0; i < 4; i++) { 118 if (descs[i] & 0x80000000) 119 continue; 120 for (j = 0; j < 4; j++) { 121 if (i == 0 && j == 0) 122 continue; 123 desc = (descs[i] >> (j * 8)) & 0xff; 124 if (desc == 0) 125 continue; 126 cai = cpu_cacheinfo_lookup( 127 intel_cpuid_cache_info, desc); 128 if (cai != NULL) { 129 ci->ci_cinfo[cai->cai_index] = 130 *cai; 131 } 132 } 133 } 134 } 135 } 136 137 if (cpuid_level < 4) 138 return; 139 140 /* Parse the cache info from `cpuid leaf 4', if we have it. */ 141 cpu_dcp_cacheinfo(ci, 4); 142 } 143 144 static void 145 cpu_probe_intel_errata(struct cpu_info *ci) 146 { 147 u_int family, model, stepping; 148 149 family = CPUID_TO_FAMILY(ci->ci_signature); 150 model = CPUID_TO_MODEL(ci->ci_signature); 151 stepping = CPUID_TO_STEPPING(ci->ci_signature); 152 153 if (family == 0x6 && model == 0x5C && stepping == 0x9) { /* Apollo Lake */ 154 wrmsr(MSR_MISC_ENABLE, 155 rdmsr(MSR_MISC_ENABLE) & ~IA32_MISC_MWAIT_EN); 156 157 cpu_feature[1] &= ~CPUID2_MONITOR; 158 ci->ci_feat_val[1] &= ~CPUID2_MONITOR; 159 } 160 } 161 162 static void 163 cpu_probe_intel(struct cpu_info *ci) 164 { 165 166 if (cpu_vendor != CPUVENDOR_INTEL) 167 return; 168 169 cpu_probe_intel_cache(ci); 170 cpu_probe_intel_errata(ci); 171 } 172 173 static void 174 cpu_probe_amd_cache(struct cpu_info *ci) 175 { 176 const struct x86_cache_info *cp; 177 struct x86_cache_info *cai; 178 int family, model; 179 u_int descs[4]; 180 u_int lfunc; 181 182 family = CPUID_TO_FAMILY(ci->ci_signature); 183 model = CPUID_TO_MODEL(ci->ci_signature); 184 185 /* K5 model 0 has none of this info. */ 186 if (family == 5 && model == 0) 187 return; 188 189 /* Determine the largest extended function value. */ 190 x86_cpuid(0x80000000, descs); 191 lfunc = descs[0]; 192 193 if (lfunc < 0x80000005) 194 return; 195 196 /* Determine L1 cache/TLB info. */ 197 x86_cpuid(0x80000005, descs); 198 199 /* K6-III and higher have large page TLBs. */ 200 if ((family == 5 && model >= 9) || family >= 6) { 201 cai = &ci->ci_cinfo[CAI_ITLB2]; 202 cai->cai_totalsize = AMD_L1_EAX_ITLB_ENTRIES(descs[0]); 203 cai->cai_associativity = AMD_L1_EAX_ITLB_ASSOC(descs[0]); 204 cai->cai_linesize = (4 * 1024 * 1024); 205 206 cai = &ci->ci_cinfo[CAI_DTLB2]; 207 cai->cai_totalsize = AMD_L1_EAX_DTLB_ENTRIES(descs[0]); 208 cai->cai_associativity = AMD_L1_EAX_DTLB_ASSOC(descs[0]); 209 cai->cai_linesize = (4 * 1024 * 1024); 210 } 211 212 cai = &ci->ci_cinfo[CAI_ITLB]; 213 cai->cai_totalsize = AMD_L1_EBX_ITLB_ENTRIES(descs[1]); 214 cai->cai_associativity = AMD_L1_EBX_ITLB_ASSOC(descs[1]); 215 cai->cai_linesize = (4 * 1024); 216 217 cai = &ci->ci_cinfo[CAI_DTLB]; 218 cai->cai_totalsize = AMD_L1_EBX_DTLB_ENTRIES(descs[1]); 219 cai->cai_associativity = AMD_L1_EBX_DTLB_ASSOC(descs[1]); 220 cai->cai_linesize = (4 * 1024); 221 222 cai = &ci->ci_cinfo[CAI_DCACHE]; 223 cai->cai_totalsize = AMD_L1_ECX_DC_SIZE(descs[2]); 224 cai->cai_associativity = AMD_L1_ECX_DC_ASSOC(descs[2]); 225 cai->cai_linesize = AMD_L1_ECX_DC_LS(descs[2]); 226 227 cai = &ci->ci_cinfo[CAI_ICACHE]; 228 cai->cai_totalsize = AMD_L1_EDX_IC_SIZE(descs[3]); 229 cai->cai_associativity = AMD_L1_EDX_IC_ASSOC(descs[3]); 230 cai->cai_linesize = AMD_L1_EDX_IC_LS(descs[3]); 231 232 if (lfunc < 0x80000006) 233 return; 234 235 /* Determine L2 cache/TLB info. */ 236 x86_cpuid(0x80000006, descs); 237 238 cai = &ci->ci_cinfo[CAI_L2CACHE]; 239 cai->cai_totalsize = AMD_L2_ECX_C_SIZE(descs[2]); 240 cai->cai_associativity = AMD_L2_ECX_C_ASSOC(descs[2]); 241 cai->cai_linesize = AMD_L2_ECX_C_LS(descs[2]); 242 243 cp = cpu_cacheinfo_lookup(amd_cpuid_l2l3cache_assoc_info, 244 cai->cai_associativity); 245 if (cp != NULL) 246 cai->cai_associativity = cp->cai_associativity; 247 else 248 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 249 250 if (family < 0xf) 251 return; 252 253 /* Determine L3 cache info on AMD Family 10h and newer processors */ 254 cai = &ci->ci_cinfo[CAI_L3CACHE]; 255 cai->cai_totalsize = AMD_L3_EDX_C_SIZE(descs[3]); 256 cai->cai_associativity = AMD_L3_EDX_C_ASSOC(descs[3]); 257 cai->cai_linesize = AMD_L3_EDX_C_LS(descs[3]); 258 259 cp = cpu_cacheinfo_lookup(amd_cpuid_l2l3cache_assoc_info, 260 cai->cai_associativity); 261 if (cp != NULL) 262 cai->cai_associativity = cp->cai_associativity; 263 else 264 cai->cai_associativity = 0; /* XXX Unknown reserved */ 265 266 if (lfunc < 0x80000019) 267 return; 268 269 /* Determine 1GB TLB info. */ 270 x86_cpuid(0x80000019, descs); 271 272 cai = &ci->ci_cinfo[CAI_L1_1GBDTLB]; 273 cai->cai_totalsize = AMD_L1_1GB_EAX_DTLB_ENTRIES(descs[1]); 274 cai->cai_associativity = AMD_L1_1GB_EAX_DTLB_ASSOC(descs[1]); 275 cai->cai_linesize = (1 * 1024); 276 277 cai = &ci->ci_cinfo[CAI_L1_1GBITLB]; 278 cai->cai_totalsize = AMD_L1_1GB_EAX_IUTLB_ENTRIES(descs[0]); 279 cai->cai_associativity = AMD_L1_1GB_EAX_IUTLB_ASSOC(descs[0]); 280 cai->cai_linesize = (1 * 1024); 281 282 cai = &ci->ci_cinfo[CAI_L2_1GBDTLB]; 283 cai->cai_totalsize = AMD_L2_1GB_EBX_DUTLB_ENTRIES(descs[1]); 284 cai->cai_associativity = AMD_L2_1GB_EBX_DUTLB_ASSOC(descs[1]); 285 cai->cai_linesize = (1 * 1024); 286 287 cai = &ci->ci_cinfo[CAI_L2_1GBITLB]; 288 cai->cai_totalsize = AMD_L2_1GB_EBX_IUTLB_ENTRIES(descs[0]); 289 cai->cai_associativity = AMD_L2_1GB_EBX_IUTLB_ASSOC(descs[0]); 290 cai->cai_linesize = (1 * 1024); 291 292 if (lfunc < 0x8000001d) 293 return; 294 295 if (ci->ci_feat_val[3] & CPUID_TOPOEXT) 296 cpu_dcp_cacheinfo(ci, 0x8000001d); 297 } 298 299 static void 300 cpu_probe_amd_errata(struct cpu_info *ci) 301 { 302 u_int model; 303 uint64_t val; 304 int flag; 305 306 model = CPUID_TO_MODEL(ci->ci_signature); 307 308 switch (CPUID_TO_FAMILY(ci->ci_signature)) { 309 case 0x05: /* K5 */ 310 if (model == 0) { 311 /* 312 * According to the AMD Processor Recognition App Note, 313 * the AMD-K5 Model 0 uses the wrong bit to indicate 314 * support for global PTEs, instead using bit 9 (APIC) 315 * rather than bit 13 (i.e. "0x200" vs. 0x2000"). 316 */ 317 flag = ci->ci_feat_val[0]; 318 if ((flag & CPUID_APIC) != 0) 319 flag = (flag & ~CPUID_APIC) | CPUID_PGE; 320 ci->ci_feat_val[0] = flag; 321 } 322 break; 323 324 case 0x10: /* Family 10h */ 325 /* 326 * On Family 10h, certain BIOSes do not enable WC+ support. 327 * This causes WC+ to become CD, and degrades guest 328 * performance at the NPT level. 329 * 330 * Explicitly enable WC+ if we're not a guest. 331 */ 332 if (!ISSET(ci->ci_feat_val[1], CPUID2_RAZ)) { 333 val = rdmsr(MSR_BU_CFG2); 334 val &= ~BU_CFG2_CWPLUS_DIS; 335 wrmsr(MSR_BU_CFG2, val); 336 } 337 break; 338 339 case 0x17: 340 /* 341 * "Revision Guide for AMD Family 17h Models 00h-0Fh 342 * Processors" revision 1.12: 343 * 344 * 1057 MWAIT or MWAITX Instructions May Fail to Correctly 345 * Exit From the Monitor Event Pending State 346 * 347 * 1109 MWAIT Instruction May Hang a Thread 348 */ 349 if (model == 0x01) { 350 cpu_feature[1] &= ~CPUID2_MONITOR; 351 ci->ci_feat_val[1] &= ~CPUID2_MONITOR; 352 } 353 break; 354 } 355 } 356 357 static void 358 cpu_probe_amd(struct cpu_info *ci) 359 { 360 361 if (cpu_vendor != CPUVENDOR_AMD) 362 return; 363 364 cpu_probe_amd_cache(ci); 365 cpu_probe_amd_errata(ci); 366 } 367 368 static inline uint8_t 369 cyrix_read_reg(uint8_t reg) 370 { 371 372 outb(0x22, reg); 373 return inb(0x23); 374 } 375 376 static inline void 377 cyrix_write_reg(uint8_t reg, uint8_t data) 378 { 379 380 outb(0x22, reg); 381 outb(0x23, data); 382 } 383 384 static void 385 cpu_probe_cyrix_cmn(struct cpu_info *ci) 386 { 387 /* 388 * i8254 latch check routine: 389 * National Geode (formerly Cyrix MediaGX) has a serious bug in 390 * its built-in i8254-compatible clock module (cs5510 cs5520). 391 * Set the variable 'clock_broken_latch' to indicate it. 392 * 393 * This bug is not present in the cs5530, and the flag 394 * is disabled again in sys/arch/i386/pci/pcib.c if this later 395 * model device is detected. Ideally, this work-around should not 396 * even be in here, it should be in there. XXX 397 */ 398 uint8_t c3; 399 #ifndef XENPV 400 extern int clock_broken_latch; 401 402 switch (ci->ci_signature) { 403 case 0x440: /* Cyrix MediaGX */ 404 case 0x540: /* GXm */ 405 clock_broken_latch = 1; 406 break; 407 } 408 #endif 409 410 /* set up various cyrix registers */ 411 /* 412 * Enable suspend on halt (powersave mode). 413 * When powersave mode is enabled, the TSC stops counting 414 * while the CPU is halted in idle() waiting for an interrupt. 415 * This means we can't use the TSC for interval time in 416 * microtime(9), and thus it is disabled here. 417 * 418 * It still makes a perfectly good cycle counter 419 * for program profiling, so long as you remember you're 420 * counting cycles, and not time. Further, if you don't 421 * mind not using powersave mode, the TSC works just fine, 422 * so this should really be optional. XXX 423 */ 424 cyrix_write_reg(0xc2, cyrix_read_reg(0xc2) | 0x08); 425 426 /* 427 * Do not disable the TSC on the Geode GX, it's reported to 428 * work fine. 429 */ 430 if (ci->ci_signature != 0x552) 431 ci->ci_feat_val[0] &= ~CPUID_TSC; 432 433 /* enable access to ccr4/ccr5 */ 434 c3 = cyrix_read_reg(0xC3); 435 cyrix_write_reg(0xC3, c3 | 0x10); 436 /* cyrix's workaround for the "coma bug" */ 437 cyrix_write_reg(0x31, cyrix_read_reg(0x31) | 0xf8); 438 cyrix_write_reg(0x32, cyrix_read_reg(0x32) | 0x7f); 439 cyrix_write_reg(0x33, cyrix_read_reg(0x33) & ~0xffu); 440 cyrix_write_reg(0x3c, cyrix_read_reg(0x3c) | 0x87); 441 /* disable access to ccr4/ccr5 */ 442 cyrix_write_reg(0xC3, c3); 443 } 444 445 static void 446 cpu_probe_cyrix(struct cpu_info *ci) 447 { 448 449 if (cpu_vendor != CPUVENDOR_CYRIX || 450 CPUID_TO_FAMILY(ci->ci_signature) < 4 || 451 CPUID_TO_FAMILY(ci->ci_signature) > 6) 452 return; 453 454 cpu_probe_cyrix_cmn(ci); 455 } 456 457 static void 458 cpu_probe_winchip(struct cpu_info *ci) 459 { 460 461 if (cpu_vendor != CPUVENDOR_IDT || 462 CPUID_TO_FAMILY(ci->ci_signature) != 5) 463 return; 464 465 /* WinChip C6 */ 466 if (CPUID_TO_MODEL(ci->ci_signature) == 4) 467 ci->ci_feat_val[0] &= ~CPUID_TSC; 468 } 469 470 static void 471 cpu_probe_c3(struct cpu_info *ci) 472 { 473 u_int family, model, stepping, descs[4], lfunc, msr; 474 struct x86_cache_info *cai; 475 476 if (cpu_vendor != CPUVENDOR_IDT || 477 CPUID_TO_FAMILY(ci->ci_signature) < 6) 478 return; 479 480 family = CPUID_TO_FAMILY(ci->ci_signature); 481 model = CPUID_TO_MODEL(ci->ci_signature); 482 stepping = CPUID_TO_STEPPING(ci->ci_signature); 483 484 if (family == 6) { 485 /* 486 * VIA Eden ESP. 487 * 488 * Quoting from page 3-4 of: "VIA Eden ESP Processor Datasheet" 489 * http://www.via.com.tw/download/mainboards/6/14/Eden20v115.pdf 490 * 491 * 1. The CMPXCHG8B instruction is provided and always enabled, 492 * however, it appears disabled in the corresponding CPUID 493 * function bit 0 to avoid a bug in an early version of 494 * Windows NT. However, this default can be changed via a 495 * bit in the FCR MSR. 496 */ 497 ci->ci_feat_val[0] |= CPUID_CX8; 498 wrmsr(MSR_VIA_FCR, rdmsr(MSR_VIA_FCR) | VIA_FCR_CX8_REPORT); 499 500 /* 501 * For reference on VIA Alternate Instructions, see the VIA C3 502 * Processor Alternate Instruction Set Application Note, 2002. 503 * http://www.bitsavers.org/components/viaTechnologies/C3-ais-appnote.pdf 504 * 505 * Disable unsafe ALTINST mode for VIA C3 processors, if necessary. 506 * 507 * This is done for the security reasons, as some CPUs were 508 * found with ALTINST enabled by default. This functionality 509 * has ability to bypass many x86 architecture memory 510 * protections and privilege checks, exposing a possibility 511 * for backdoors and should not be enabled unintentionally. 512 */ 513 if (model > 0x5 && model < 0xA) { 514 int disable_ais = 0; 515 x86_cpuid(0xc0000000, descs); 516 lfunc = descs[0]; 517 /* Check AIS flags first if supported ("Nehemiah"). */ 518 if (lfunc >= 0xc0000001) { 519 x86_cpuid(0xc0000001, descs); 520 lfunc = descs[3]; 521 if ((lfunc & CPUID_VIA_HAS_AIS) 522 && (lfunc & CPUID_VIA_DO_AIS)) { 523 disable_ais = 1; 524 } 525 } else /* Explicitly disable AIS for pre-CX5L CPUs. */ 526 disable_ais = 1; 527 528 if (disable_ais) { 529 msr = rdmsr(MSR_VIA_FCR); 530 wrmsr(MSR_VIA_FCR, msr & ~VIA_FCR_ALTINST_ENABLE); 531 } 532 } 533 } 534 535 if (family > 6 || model > 0x9 || (model == 0x9 && stepping >= 3)) { 536 /* VIA Nehemiah or later. */ 537 x86_cpuid(0xc0000000, descs); 538 lfunc = descs[0]; 539 if (lfunc >= 0xc0000001) { /* has ACE, RNG */ 540 int rng_enable = 0, ace_enable = 0; 541 x86_cpuid(0xc0000001, descs); 542 lfunc = descs[3]; 543 ci->ci_feat_val[4] = lfunc; 544 /* Check for and enable RNG */ 545 if (lfunc & CPUID_VIA_HAS_RNG) { 546 if (!(lfunc & CPUID_VIA_DO_RNG)) { 547 rng_enable++; 548 ci->ci_feat_val[4] |= CPUID_VIA_DO_RNG; 549 } 550 } 551 /* Check for and enable ACE (AES-CBC) */ 552 if (lfunc & CPUID_VIA_HAS_ACE) { 553 if (!(lfunc & CPUID_VIA_DO_ACE)) { 554 ace_enable++; 555 ci->ci_feat_val[4] |= CPUID_VIA_DO_ACE; 556 } 557 } 558 /* Check for and enable SHA */ 559 if (lfunc & CPUID_VIA_HAS_PHE) { 560 if (!(lfunc & CPUID_VIA_DO_PHE)) { 561 ace_enable++; 562 ci->ci_feat_val[4] |= CPUID_VIA_DO_PHE; 563 } 564 } 565 /* Check for and enable ACE2 (AES-CTR) */ 566 if (lfunc & CPUID_VIA_HAS_ACE2) { 567 if (!(lfunc & CPUID_VIA_DO_ACE2)) { 568 ace_enable++; 569 ci->ci_feat_val[4] |= CPUID_VIA_DO_ACE2; 570 } 571 } 572 /* Check for and enable PMM (modmult engine) */ 573 if (lfunc & CPUID_VIA_HAS_PMM) { 574 if (!(lfunc & CPUID_VIA_DO_PMM)) { 575 ace_enable++; 576 ci->ci_feat_val[4] |= CPUID_VIA_DO_PMM; 577 } 578 } 579 580 /* 581 * Actually do the enables. It's a little gross, 582 * but per the PadLock programming guide, "Enabling 583 * PadLock", condition 3, we must enable SSE too or 584 * else the first use of RNG or ACE instructions 585 * will generate a trap. 586 * 587 * We must do this early because of kernel RNG 588 * initialization but it is safe without the full 589 * FPU-detect as all these CPUs have SSE. 590 */ 591 lcr4(rcr4() | CR4_OSFXSR); 592 593 if (rng_enable) { 594 msr = rdmsr(MSR_VIA_RNG); 595 msr |= MSR_VIA_RNG_ENABLE; 596 /* C7 stepping 8 and subsequent CPUs have dual RNG */ 597 if (model > 0xA || (model == 0xA && stepping > 0x7)) { 598 msr |= MSR_VIA_RNG_2NOISE; 599 } 600 wrmsr(MSR_VIA_RNG, msr); 601 } 602 603 if (ace_enable) { 604 msr = rdmsr(MSR_VIA_FCR); 605 wrmsr(MSR_VIA_FCR, msr | VIA_FCR_ACE_ENABLE); 606 } 607 } 608 } 609 610 /* Determine the largest extended function value. */ 611 x86_cpuid(0x80000000, descs); 612 lfunc = descs[0]; 613 614 /* 615 * Determine L1 cache/TLB info. 616 */ 617 if (lfunc < 0x80000005) { 618 /* No L1 cache info available. */ 619 return; 620 } 621 622 x86_cpuid(0x80000005, descs); 623 624 cai = &ci->ci_cinfo[CAI_ITLB]; 625 cai->cai_totalsize = VIA_L1_EBX_ITLB_ENTRIES(descs[1]); 626 cai->cai_associativity = VIA_L1_EBX_ITLB_ASSOC(descs[1]); 627 cai->cai_linesize = (4 * 1024); 628 629 cai = &ci->ci_cinfo[CAI_DTLB]; 630 cai->cai_totalsize = VIA_L1_EBX_DTLB_ENTRIES(descs[1]); 631 cai->cai_associativity = VIA_L1_EBX_DTLB_ASSOC(descs[1]); 632 cai->cai_linesize = (4 * 1024); 633 634 cai = &ci->ci_cinfo[CAI_DCACHE]; 635 cai->cai_totalsize = VIA_L1_ECX_DC_SIZE(descs[2]); 636 cai->cai_associativity = VIA_L1_ECX_DC_ASSOC(descs[2]); 637 cai->cai_linesize = VIA_L1_EDX_IC_LS(descs[2]); 638 if (family == 6 && model == 9 && stepping == 8) { 639 /* Erratum: stepping 8 reports 4 when it should be 2 */ 640 cai->cai_associativity = 2; 641 } 642 643 cai = &ci->ci_cinfo[CAI_ICACHE]; 644 cai->cai_totalsize = VIA_L1_EDX_IC_SIZE(descs[3]); 645 cai->cai_associativity = VIA_L1_EDX_IC_ASSOC(descs[3]); 646 cai->cai_linesize = VIA_L1_EDX_IC_LS(descs[3]); 647 if (family == 6 && model == 9 && stepping == 8) { 648 /* Erratum: stepping 8 reports 4 when it should be 2 */ 649 cai->cai_associativity = 2; 650 } 651 652 /* 653 * Determine L2 cache/TLB info. 654 */ 655 if (lfunc < 0x80000006) { 656 /* No L2 cache info available. */ 657 return; 658 } 659 660 x86_cpuid(0x80000006, descs); 661 662 cai = &ci->ci_cinfo[CAI_L2CACHE]; 663 if (family > 6 || model >= 9) { 664 cai->cai_totalsize = VIA_L2N_ECX_C_SIZE(descs[2]); 665 cai->cai_associativity = VIA_L2N_ECX_C_ASSOC(descs[2]); 666 cai->cai_linesize = VIA_L2N_ECX_C_LS(descs[2]); 667 } else { 668 cai->cai_totalsize = VIA_L2_ECX_C_SIZE(descs[2]); 669 cai->cai_associativity = VIA_L2_ECX_C_ASSOC(descs[2]); 670 cai->cai_linesize = VIA_L2_ECX_C_LS(descs[2]); 671 } 672 } 673 674 static void 675 cpu_probe_geode(struct cpu_info *ci) 676 { 677 678 if (memcmp("Geode by NSC", ci->ci_vendor, 12) != 0 || 679 CPUID_TO_FAMILY(ci->ci_signature) != 5) 680 return; 681 682 cpu_probe_cyrix_cmn(ci); 683 cpu_probe_amd_cache(ci); 684 } 685 686 static void 687 cpu_probe_vortex86(struct cpu_info *ci) 688 { 689 #define PCI_MODE1_ADDRESS_REG 0x0cf8 690 #define PCI_MODE1_DATA_REG 0x0cfc 691 #define PCI_MODE1_ENABLE 0x80000000UL 692 693 uint32_t reg, idx; 694 695 if (cpu_vendor != CPUVENDOR_VORTEX86) 696 return; 697 /* 698 * CPU model available from "Customer ID register" in 699 * North Bridge Function 0 PCI space 700 * we can't use pci_conf_read() because the PCI subsystem is not 701 * not initialised early enough 702 */ 703 704 outl(PCI_MODE1_ADDRESS_REG, PCI_MODE1_ENABLE | 0x90); 705 reg = inl(PCI_MODE1_DATA_REG); 706 707 if ((reg & 0xf0ffffff) != 0x30504d44) { 708 idx = 0; 709 } else { 710 idx = (reg >> 24) & 0xf; 711 } 712 713 static const char *cpu_vortex86_flavor[] = { 714 "??", "SX", "DX", "MX", "DX2", "MX+", "DX3", "EX", "EX2", 715 }; 716 idx = idx < __arraycount(cpu_vortex86_flavor) ? idx : 0; 717 snprintf(cpu_brand_string, sizeof(cpu_brand_string), "Vortex86%s", 718 cpu_vortex86_flavor[idx]); 719 720 #undef PCI_MODE1_ENABLE 721 #undef PCI_MODE1_ADDRESS_REG 722 #undef PCI_MODE1_DATA_REG 723 } 724 725 static void 726 cpu_probe_fpu_old(struct cpu_info *ci) 727 { 728 #if defined(__i386__) && !defined(XENPV) 729 730 clts(); 731 fninit(); 732 733 /* Check for 'FDIV' bug on the original Pentium */ 734 if (npx586bug1(4195835, 3145727) != 0) 735 /* NB 120+MHz cpus are not affected */ 736 i386_fpu_fdivbug = 1; 737 738 stts(); 739 #endif 740 } 741 742 static void 743 cpu_probe_fpu(struct cpu_info *ci) 744 { 745 u_int descs[4]; 746 int i; 747 748 x86_fpu_save = FPU_SAVE_FSAVE; 749 750 #ifdef i386 751 /* If we have FXSAVE/FXRESTOR, use them. */ 752 if ((ci->ci_feat_val[0] & CPUID_FXSR) == 0) { 753 i386_use_fxsave = 0; 754 cpu_probe_fpu_old(ci); 755 return; 756 } 757 758 i386_use_fxsave = 1; 759 /* 760 * If we have SSE/SSE2, enable XMM exceptions, and 761 * notify userland. 762 */ 763 if (ci->ci_feat_val[0] & CPUID_SSE) 764 i386_has_sse = 1; 765 if (ci->ci_feat_val[0] & CPUID_SSE2) 766 i386_has_sse2 = 1; 767 #else 768 /* 769 * For amd64 i386_use_fxsave, i386_has_sse and i386_has_sse2 are 770 * #defined to 1, because fxsave/sse/sse2 are always present. 771 */ 772 #endif 773 774 x86_fpu_save = FPU_SAVE_FXSAVE; 775 x86_fpu_save_size = sizeof(struct fxsave); 776 777 /* See if XSAVE is supported */ 778 if ((ci->ci_feat_val[1] & CPUID2_XSAVE) == 0) 779 return; 780 781 #ifdef XENPV 782 /* 783 * Xen kernel can disable XSAVE via "no-xsave" option, in that case 784 * the XSAVE/XRSTOR instructions become privileged and trigger 785 * supervisor trap. OSXSAVE flag seems to be reliably set according 786 * to whether XSAVE is actually available. 787 */ 788 if ((ci->ci_feat_val[1] & CPUID2_OSXSAVE) == 0) 789 return; 790 #endif 791 792 x86_fpu_save = FPU_SAVE_XSAVE; 793 794 x86_cpuid2(0xd, 1, descs); 795 if (descs[0] & CPUID_PES1_XSAVEOPT) 796 x86_fpu_save = FPU_SAVE_XSAVEOPT; 797 798 /* Get features and maximum size of the save area */ 799 x86_cpuid(0xd, descs); 800 if (descs[2] > sizeof(struct fxsave)) 801 x86_fpu_save_size = descs[2]; 802 803 x86_xsave_features = (uint64_t)descs[3] << 32 | descs[0]; 804 805 /* Get component offsets and sizes for the save area */ 806 for (i = XSAVE_YMM_Hi128; i < __arraycount(x86_xsave_offsets); i++) { 807 if (x86_xsave_features & __BIT(i)) { 808 x86_cpuid2(0xd, i, descs); 809 x86_xsave_offsets[i] = descs[1]; 810 x86_xsave_sizes[i] = descs[0]; 811 } 812 } 813 } 814 815 void 816 cpu_probe(struct cpu_info *ci) 817 { 818 u_int descs[4]; 819 int i; 820 uint32_t miscbytes; 821 uint32_t brand[12]; 822 823 if (ci == &cpu_info_primary) { 824 cpu_vendor = i386_nocpuid_cpus[cputype << 1]; 825 cpu_class = i386_nocpuid_cpus[(cputype << 1) + 1]; 826 } 827 828 if (cpuid_level < 0) { 829 /* cpuid instruction not supported */ 830 cpu_probe_fpu_old(ci); 831 return; 832 } 833 834 for (i = 0; i < __arraycount(ci->ci_feat_val); i++) { 835 ci->ci_feat_val[i] = 0; 836 } 837 838 x86_cpuid(0, descs); 839 cpuid_level = descs[0]; 840 ci->ci_max_cpuid = descs[0]; 841 842 ci->ci_vendor[0] = descs[1]; 843 ci->ci_vendor[2] = descs[2]; 844 ci->ci_vendor[1] = descs[3]; 845 ci->ci_vendor[3] = 0; 846 847 if (ci == &cpu_info_primary) { 848 if (memcmp(ci->ci_vendor, "GenuineIntel", 12) == 0) 849 cpu_vendor = CPUVENDOR_INTEL; 850 else if (memcmp(ci->ci_vendor, "AuthenticAMD", 12) == 0) 851 cpu_vendor = CPUVENDOR_AMD; 852 else if (memcmp(ci->ci_vendor, "CyrixInstead", 12) == 0) 853 cpu_vendor = CPUVENDOR_CYRIX; 854 else if (memcmp(ci->ci_vendor, "Geode by NSC", 12) == 0) 855 cpu_vendor = CPUVENDOR_CYRIX; 856 else if (memcmp(ci->ci_vendor, "CentaurHauls", 12) == 0) 857 cpu_vendor = CPUVENDOR_IDT; 858 else if (memcmp(ci->ci_vendor, "GenuineTMx86", 12) == 0) 859 cpu_vendor = CPUVENDOR_TRANSMETA; 860 else if (memcmp(ci->ci_vendor, "Vortex86 SoC", 12) == 0) 861 cpu_vendor = CPUVENDOR_VORTEX86; 862 else 863 cpu_vendor = CPUVENDOR_UNKNOWN; 864 } 865 866 if (cpuid_level >= 1) { 867 x86_cpuid(1, descs); 868 ci->ci_signature = descs[0]; 869 miscbytes = descs[1]; 870 ci->ci_feat_val[1] = descs[2]; 871 ci->ci_feat_val[0] = descs[3]; 872 873 if (ci == &cpu_info_primary) { 874 /* Determine family + class. */ 875 cpu_class = CPUID_TO_FAMILY(ci->ci_signature) 876 + (CPUCLASS_386 - 3); 877 if (cpu_class > CPUCLASS_686) 878 cpu_class = CPUCLASS_686; 879 } 880 881 /* CLFLUSH line size is next 8 bits */ 882 if (ci->ci_feat_val[0] & CPUID_CLFSH) 883 ci->ci_cflush_lsize 884 = __SHIFTOUT(miscbytes, CPUID_CLFLUSH_SIZE) << 3; 885 ci->ci_initapicid = __SHIFTOUT(miscbytes, CPUID_LOCAL_APIC_ID); 886 } 887 888 /* 889 * Get the basic information from the extended cpuid leafs. 890 * These were first implemented by amd, but most of the values 891 * match with those generated by modern intel cpus. 892 */ 893 x86_cpuid(0x80000000, descs); 894 if (descs[0] >= 0x80000000) 895 ci->ci_max_ext_cpuid = descs[0]; 896 else 897 ci->ci_max_ext_cpuid = 0; 898 899 if (ci->ci_max_ext_cpuid >= 0x80000001) { 900 /* Determine the extended feature flags. */ 901 x86_cpuid(0x80000001, descs); 902 ci->ci_feat_val[3] = descs[2]; /* %ecx */ 903 ci->ci_feat_val[2] = descs[3]; /* %edx */ 904 } 905 906 if (ci->ci_max_ext_cpuid >= 0x80000004) { 907 x86_cpuid(0x80000002, brand); 908 x86_cpuid(0x80000003, brand + 4); 909 x86_cpuid(0x80000004, brand + 8); 910 /* Skip leading spaces on brand */ 911 for (i = 0; i < 48; i++) { 912 if (((char *) brand)[i] != ' ') 913 break; 914 } 915 memcpy(cpu_brand_string, ((char *) brand) + i, 48 - i); 916 } 917 918 /* 919 * Get the structured extended features. 920 */ 921 if (cpuid_level >= 7) { 922 x86_cpuid(7, descs); 923 ci->ci_feat_val[5] = descs[1]; /* %ebx */ 924 ci->ci_feat_val[6] = descs[2]; /* %ecx */ 925 ci->ci_feat_val[7] = descs[3]; /* %edx */ 926 } 927 928 cpu_probe_intel(ci); 929 cpu_probe_amd(ci); 930 cpu_probe_cyrix(ci); 931 cpu_probe_winchip(ci); 932 cpu_probe_c3(ci); 933 cpu_probe_geode(ci); 934 cpu_probe_vortex86(ci); 935 936 if (ci == &cpu_info_primary) { 937 cpu_probe_fpu(ci); 938 } 939 940 #ifndef XENPV 941 x86_cpu_topology(ci); 942 #endif 943 944 if (cpu_vendor != CPUVENDOR_AMD && (ci->ci_feat_val[0] & CPUID_TM) && 945 (rdmsr(MSR_MISC_ENABLE) & (1 << 3)) == 0) { 946 /* Enable thermal monitor 1. */ 947 wrmsr(MSR_MISC_ENABLE, rdmsr(MSR_MISC_ENABLE) | (1<<3)); 948 } 949 950 ci->ci_feat_val[0] &= ~CPUID_FEAT_BLACKLIST; 951 if (ci == &cpu_info_primary) { 952 /* If first. Boot Processor is the cpu_feature reference. */ 953 for (i = 0; i < __arraycount(cpu_feature); i++) { 954 cpu_feature[i] = ci->ci_feat_val[i]; 955 } 956 identify_hypervisor(); 957 #ifndef XENPV 958 /* Early patch of text segment. */ 959 x86_patch(true); 960 #endif 961 962 /* AES */ 963 #ifdef __x86_64__ /* not yet implemented on i386 */ 964 if (cpu_feature[1] & CPUID2_AESNI) 965 aes_md_init(&aes_ni_impl); 966 else 967 #endif 968 if (cpu_feature[4] & CPUID_VIA_HAS_ACE) 969 aes_md_init(&aes_via_impl); 970 else if (i386_has_sse && i386_has_sse2 && 971 (cpu_feature[1] & CPUID2_SSE3) && 972 (cpu_feature[1] & CPUID2_SSSE3)) 973 aes_md_init(&aes_ssse3_impl); 974 else if (i386_has_sse && i386_has_sse2) 975 aes_md_init(&aes_sse2_impl); 976 977 /* ChaCha */ 978 if (i386_has_sse && i386_has_sse2) 979 chacha_md_init(&chacha_sse2_impl); 980 } else { 981 /* 982 * If not first. Warn about cpu_feature mismatch for 983 * secondary CPUs. 984 */ 985 for (i = 0; i < __arraycount(cpu_feature); i++) { 986 if (cpu_feature[i] != ci->ci_feat_val[i]) 987 aprint_error_dev(ci->ci_dev, 988 "feature mismatch: cpu_feature[%d] is " 989 "%#x, but CPU reported %#x\n", 990 i, cpu_feature[i], ci->ci_feat_val[i]); 991 } 992 } 993 } 994 995 /* Write what we know about the cpu to the console... */ 996 void 997 cpu_identify(struct cpu_info *ci) 998 { 999 1000 cpu_setmodel("%s %d86-class", 1001 cpu_vendor_names[cpu_vendor], cpu_class + 3); 1002 if (cpu_brand_string[0] != '\0') { 1003 aprint_normal_dev(ci->ci_dev, "%s", cpu_brand_string); 1004 } else { 1005 aprint_normal_dev(ci->ci_dev, "%s", cpu_getmodel()); 1006 if (ci->ci_data.cpu_cc_freq != 0) 1007 aprint_normal(", %dMHz", 1008 (int)(ci->ci_data.cpu_cc_freq / 1000000)); 1009 } 1010 if (ci->ci_signature != 0) 1011 aprint_normal(", id 0x%x", ci->ci_signature); 1012 aprint_normal("\n"); 1013 aprint_normal_dev(ci->ci_dev, "node %u, package %u, core %u, smt %u\n", 1014 ci->ci_numa_id, ci->ci_package_id, ci->ci_core_id, ci->ci_smt_id); 1015 if (cpu_brand_string[0] == '\0') { 1016 strlcpy(cpu_brand_string, cpu_getmodel(), 1017 sizeof(cpu_brand_string)); 1018 } 1019 if (cpu_class == CPUCLASS_386) { 1020 panic("NetBSD requires an 80486DX or later processor"); 1021 } 1022 if (cputype == CPU_486DLC) { 1023 aprint_error("WARNING: BUGGY CYRIX CACHE\n"); 1024 } 1025 1026 #if !defined(XENPV) || defined(DOM0OPS) /* on Xen PV rdmsr is for Dom0 only */ 1027 if (cpu_vendor == CPUVENDOR_AMD /* check enablement of an */ 1028 && device_unit(ci->ci_dev) == 0 /* AMD feature only once */ 1029 && ((cpu_feature[3] & CPUID_SVM) == CPUID_SVM)) { 1030 uint64_t val; 1031 1032 val = rdmsr(MSR_VMCR); 1033 if (((val & VMCR_SVMED) == VMCR_SVMED) 1034 && ((val & VMCR_LOCK) == VMCR_LOCK)) { 1035 aprint_normal_dev(ci->ci_dev, 1036 "SVM disabled by the BIOS\n"); 1037 } 1038 } 1039 #endif 1040 1041 #ifdef i386 1042 if (i386_fpu_fdivbug == 1) 1043 aprint_normal_dev(ci->ci_dev, 1044 "WARNING: Pentium FDIV bug detected!\n"); 1045 1046 if (cpu_vendor == CPUVENDOR_TRANSMETA) { 1047 u_int descs[4]; 1048 x86_cpuid(0x80860000, descs); 1049 if (descs[0] >= 0x80860007) 1050 /* Create longrun sysctls */ 1051 tmx86_init_longrun(); 1052 } 1053 #endif /* i386 */ 1054 1055 } 1056 1057 /* 1058 * Hypervisor 1059 */ 1060 vm_guest_t vm_guest = VM_GUEST_NO; 1061 1062 struct vm_name_guest { 1063 const char *name; 1064 vm_guest_t guest; 1065 }; 1066 1067 static const struct vm_name_guest vm_bios_vendors[] = { 1068 { "QEMU", VM_GUEST_VM }, /* QEMU */ 1069 { "Plex86", VM_GUEST_VM }, /* Plex86 */ 1070 { "Bochs", VM_GUEST_VM }, /* Bochs */ 1071 { "Xen", VM_GUEST_VM }, /* Xen */ 1072 { "BHYVE", VM_GUEST_VM }, /* bhyve */ 1073 { "Seabios", VM_GUEST_VM }, /* KVM */ 1074 { "innotek GmbH", VM_GUEST_VIRTUALBOX }, /* Oracle VirtualBox */ 1075 }; 1076 1077 static const struct vm_name_guest vm_system_products[] = { 1078 { "VMware Virtual Platform", VM_GUEST_VM }, /* VMWare VM */ 1079 { "Virtual Machine", VM_GUEST_VM }, /* Microsoft VirtualPC */ 1080 { "VirtualBox", VM_GUEST_VIRTUALBOX }, /* Sun xVM VirtualBox */ 1081 { "Parallels Virtual Platform", VM_GUEST_VM }, /* Parallels VM */ 1082 { "KVM", VM_GUEST_VM }, /* KVM */ 1083 }; 1084 1085 void 1086 identify_hypervisor(void) 1087 { 1088 u_int regs[6]; 1089 char hv_vendor[12]; 1090 const char *p; 1091 int i; 1092 1093 switch (vm_guest) { 1094 case VM_GUEST_XENPV: 1095 case VM_GUEST_XENPVH: 1096 /* guest type already known, no bios info */ 1097 return; 1098 default: 1099 break; 1100 } 1101 1102 /* 1103 * [RFC] CPUID usage for interaction between Hypervisors and Linux. 1104 * http://lkml.org/lkml/2008/10/1/246 1105 * 1106 * KB1009458: Mechanisms to determine if software is running in 1107 * a VMware virtual machine 1108 * http://kb.vmware.com/kb/1009458 1109 */ 1110 if (ISSET(cpu_feature[1], CPUID2_RAZ)) { 1111 vm_guest = VM_GUEST_VM; 1112 x86_cpuid(0x40000000, regs); 1113 if (regs[0] >= 0x40000000) { 1114 memcpy(&hv_vendor[0], ®s[1], sizeof(*regs)); 1115 memcpy(&hv_vendor[4], ®s[2], sizeof(*regs)); 1116 memcpy(&hv_vendor[8], ®s[3], sizeof(*regs)); 1117 if (memcmp(hv_vendor, "VMwareVMware", 12) == 0) 1118 vm_guest = VM_GUEST_VMWARE; 1119 else if (memcmp(hv_vendor, "Microsoft Hv", 12) == 0) { 1120 vm_guest = VM_GUEST_HV; 1121 #if NHYPERV > 0 1122 hyperv_early_init(); 1123 #endif 1124 } else if (memcmp(hv_vendor, "KVMKVMKVM\0\0\0", 12) == 0) 1125 vm_guest = VM_GUEST_KVM; 1126 else if (memcmp(hv_vendor, "XenVMMXenVMM", 12) == 0) 1127 vm_guest = VM_GUEST_XENHVM; 1128 /* FreeBSD bhyve: "bhyve bhyve " */ 1129 /* OpenBSD vmm: "OpenBSDVMM58" */ 1130 /* NetBSD nvmm: "___ NVMM ___" */ 1131 } 1132 // VirtualBox returns KVM, so keep going. 1133 if (vm_guest != VM_GUEST_KVM) 1134 return; 1135 } 1136 1137 /* 1138 * Examine SMBIOS strings for older hypervisors. 1139 */ 1140 p = pmf_get_platform("system-serial"); 1141 if (p != NULL) { 1142 if (strncmp(p, "VMware-", 7) == 0 || strncmp(p, "VMW", 3) == 0) { 1143 vmt_hvcall(VM_CMD_GET_VERSION, regs); 1144 if (regs[1] == VM_MAGIC) { 1145 vm_guest = VM_GUEST_VMWARE; 1146 return; 1147 } 1148 } 1149 } 1150 p = pmf_get_platform("bios-vendor"); 1151 if (p != NULL) { 1152 for (i = 0; i < __arraycount(vm_bios_vendors); i++) { 1153 if (strcmp(p, vm_bios_vendors[i].name) == 0) { 1154 vm_guest = vm_bios_vendors[i].guest; 1155 return; 1156 } 1157 } 1158 } 1159 p = pmf_get_platform("system-product"); 1160 if (p != NULL) { 1161 for (i = 0; i < __arraycount(vm_system_products); i++) { 1162 if (strcmp(p, vm_system_products[i].name) == 0) { 1163 vm_guest = vm_system_products[i].guest; 1164 return; 1165 } 1166 } 1167 } 1168 } 1169