1 /* $NetBSD: identcpu.c,v 1.43 2014/02/25 17:56:03 dsl Exp $ */ 2 3 /*- 4 * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Frank van der Linden, and by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: identcpu.c,v 1.43 2014/02/25 17:56:03 dsl Exp $"); 34 35 #include "opt_xen.h" 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/device.h> 40 41 #include <uvm/uvm_extern.h> 42 43 #include <machine/specialreg.h> 44 #include <machine/pio.h> 45 #include <machine/cpu.h> 46 47 #include <x86/cputypes.h> 48 #include <x86/cacheinfo.h> 49 #include <x86/cpuvar.h> 50 #include <x86/cpu_msr.h> 51 52 static const struct x86_cache_info intel_cpuid_cache_info[] = INTEL_CACHE_INFO; 53 54 static const struct x86_cache_info amd_cpuid_l2cache_assoc_info[] = 55 AMD_L2CACHE_INFO; 56 57 static const struct x86_cache_info amd_cpuid_l3cache_assoc_info[] = 58 AMD_L3CACHE_INFO; 59 60 int cpu_vendor; 61 char cpu_brand_string[49]; 62 63 int x86_fpu_save = FPU_SAVE_FSAVE; 64 unsigned int x86_fpu_save_size = 512; 65 uint64_t x86_xsave_features = 0; 66 67 /* 68 * Info for CTL_HW 69 */ 70 char cpu_model[120]; 71 72 /* 73 * Note: these are just the ones that may not have a cpuid instruction. 74 * We deal with the rest in a different way. 75 */ 76 const int i386_nocpuid_cpus[] = { 77 CPUVENDOR_INTEL, CPUCLASS_386, /* CPU_386SX */ 78 CPUVENDOR_INTEL, CPUCLASS_386, /* CPU_386 */ 79 CPUVENDOR_INTEL, CPUCLASS_486, /* CPU_486SX */ 80 CPUVENDOR_INTEL, CPUCLASS_486, /* CPU_486 */ 81 CPUVENDOR_CYRIX, CPUCLASS_486, /* CPU_486DLC */ 82 CPUVENDOR_CYRIX, CPUCLASS_486, /* CPU_6x86 */ 83 CPUVENDOR_NEXGEN, CPUCLASS_386, /* CPU_NX586 */ 84 }; 85 86 static const char cpu_vendor_names[][10] = { 87 "Unknown", "Intel", "NS/Cyrix", "NexGen", "AMD", "IDT/VIA", "Transmeta", 88 "Vortex86" 89 }; 90 91 static const struct x86_cache_info * 92 cache_info_lookup(const struct x86_cache_info *cai, uint8_t desc) 93 { 94 int i; 95 96 for (i = 0; cai[i].cai_desc != 0; i++) { 97 if (cai[i].cai_desc == desc) 98 return (&cai[i]); 99 } 100 101 return (NULL); 102 } 103 104 static void 105 cpu_probe_intel_cache(struct cpu_info *ci) 106 { 107 const struct x86_cache_info *cai; 108 u_int descs[4]; 109 int iterations, i, j; 110 uint8_t desc; 111 112 if (cpuid_level >= 2) { 113 /* Parse the cache info from `cpuid leaf 2', if we have it. */ 114 x86_cpuid(2, descs); 115 iterations = descs[0] & 0xff; 116 while (iterations-- > 0) { 117 for (i = 0; i < 4; i++) { 118 if (descs[i] & 0x80000000) 119 continue; 120 for (j = 0; j < 4; j++) { 121 if (i == 0 && j == 0) 122 continue; 123 desc = (descs[i] >> (j * 8)) & 0xff; 124 if (desc == 0) 125 continue; 126 cai = cache_info_lookup( 127 intel_cpuid_cache_info, desc); 128 if (cai != NULL) { 129 ci->ci_cinfo[cai->cai_index] = 130 *cai; 131 } 132 } 133 } 134 } 135 } 136 137 if (cpuid_level >= 4) { 138 int type, level; 139 int ways, partitions, linesize, sets; 140 int caitype = -1; 141 int totalsize; 142 143 /* Parse the cache info from `cpuid leaf 4', if we have it. */ 144 for (i = 0; ; i++) { 145 x86_cpuid2(4, i, descs); 146 type = __SHIFTOUT(descs[0], CPUID_DCP_CACHETYPE); 147 if (type == CPUID_DCP_CACHETYPE_N) 148 break; 149 level = __SHIFTOUT(descs[0], CPUID_DCP_CACHELEVEL); 150 switch (level) { 151 case 1: 152 if (type == CPUID_DCP_CACHETYPE_I) 153 caitype = CAI_ICACHE; 154 else if (type == CPUID_DCP_CACHETYPE_D) 155 caitype = CAI_DCACHE; 156 else 157 caitype = -1; 158 break; 159 case 2: 160 if (type == CPUID_DCP_CACHETYPE_U) 161 caitype = CAI_L2CACHE; 162 else 163 caitype = -1; 164 break; 165 case 3: 166 if (type == CPUID_DCP_CACHETYPE_U) 167 caitype = CAI_L3CACHE; 168 else 169 caitype = -1; 170 break; 171 default: 172 caitype = -1; 173 break; 174 } 175 if (caitype == -1) 176 continue; 177 178 ways = __SHIFTOUT(descs[1], CPUID_DCP_WAYS) + 1; 179 partitions =__SHIFTOUT(descs[1], CPUID_DCP_PARTITIONS) 180 + 1; 181 linesize = __SHIFTOUT(descs[1], CPUID_DCP_LINESIZE) 182 + 1; 183 sets = descs[2] + 1; 184 totalsize = ways * partitions * linesize * sets; 185 ci->ci_cinfo[caitype].cai_totalsize = totalsize; 186 ci->ci_cinfo[caitype].cai_associativity = ways; 187 ci->ci_cinfo[caitype].cai_linesize = linesize; 188 } 189 } 190 } 191 192 static void 193 cpu_probe_intel(struct cpu_info *ci) 194 { 195 196 if (cpu_vendor != CPUVENDOR_INTEL) 197 return; 198 199 cpu_probe_intel_cache(ci); 200 } 201 202 static void 203 cpu_probe_amd_cache(struct cpu_info *ci) 204 { 205 const struct x86_cache_info *cp; 206 struct x86_cache_info *cai; 207 int family, model; 208 u_int descs[4]; 209 u_int lfunc; 210 211 family = CPUID_TO_FAMILY(ci->ci_signature); 212 model = CPUID_TO_MODEL(ci->ci_signature); 213 214 /* 215 * K5 model 0 has none of this info. 216 */ 217 if (family == 5 && model == 0) 218 return; 219 220 /* 221 * Determine the largest extended function value. 222 */ 223 x86_cpuid(0x80000000, descs); 224 lfunc = descs[0]; 225 226 /* 227 * Determine L1 cache/TLB info. 228 */ 229 if (lfunc < 0x80000005) { 230 /* No L1 cache info available. */ 231 return; 232 } 233 234 x86_cpuid(0x80000005, descs); 235 236 /* 237 * K6-III and higher have large page TLBs. 238 */ 239 if ((family == 5 && model >= 9) || family >= 6) { 240 cai = &ci->ci_cinfo[CAI_ITLB2]; 241 cai->cai_totalsize = AMD_L1_EAX_ITLB_ENTRIES(descs[0]); 242 cai->cai_associativity = AMD_L1_EAX_ITLB_ASSOC(descs[0]); 243 cai->cai_linesize = (4 * 1024 * 1024); 244 245 cai = &ci->ci_cinfo[CAI_DTLB2]; 246 cai->cai_totalsize = AMD_L1_EAX_DTLB_ENTRIES(descs[0]); 247 cai->cai_associativity = AMD_L1_EAX_DTLB_ASSOC(descs[0]); 248 cai->cai_linesize = (4 * 1024 * 1024); 249 } 250 251 cai = &ci->ci_cinfo[CAI_ITLB]; 252 cai->cai_totalsize = AMD_L1_EBX_ITLB_ENTRIES(descs[1]); 253 cai->cai_associativity = AMD_L1_EBX_ITLB_ASSOC(descs[1]); 254 cai->cai_linesize = (4 * 1024); 255 256 cai = &ci->ci_cinfo[CAI_DTLB]; 257 cai->cai_totalsize = AMD_L1_EBX_DTLB_ENTRIES(descs[1]); 258 cai->cai_associativity = AMD_L1_EBX_DTLB_ASSOC(descs[1]); 259 cai->cai_linesize = (4 * 1024); 260 261 cai = &ci->ci_cinfo[CAI_DCACHE]; 262 cai->cai_totalsize = AMD_L1_ECX_DC_SIZE(descs[2]); 263 cai->cai_associativity = AMD_L1_ECX_DC_ASSOC(descs[2]); 264 cai->cai_linesize = AMD_L1_ECX_DC_LS(descs[2]); 265 266 cai = &ci->ci_cinfo[CAI_ICACHE]; 267 cai->cai_totalsize = AMD_L1_EDX_IC_SIZE(descs[3]); 268 cai->cai_associativity = AMD_L1_EDX_IC_ASSOC(descs[3]); 269 cai->cai_linesize = AMD_L1_EDX_IC_LS(descs[3]); 270 271 /* 272 * Determine L2 cache/TLB info. 273 */ 274 if (lfunc < 0x80000006) { 275 /* No L2 cache info available. */ 276 return; 277 } 278 279 x86_cpuid(0x80000006, descs); 280 281 cai = &ci->ci_cinfo[CAI_L2CACHE]; 282 cai->cai_totalsize = AMD_L2_ECX_C_SIZE(descs[2]); 283 cai->cai_associativity = AMD_L2_ECX_C_ASSOC(descs[2]); 284 cai->cai_linesize = AMD_L2_ECX_C_LS(descs[2]); 285 286 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 287 cai->cai_associativity); 288 if (cp != NULL) 289 cai->cai_associativity = cp->cai_associativity; 290 else 291 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 292 293 if (family < 0xf) { 294 /* No L3 cache info available. */ 295 return; 296 } 297 298 cai = &ci->ci_cinfo[CAI_L3CACHE]; 299 cai->cai_totalsize = AMD_L3_EDX_C_SIZE(descs[3]); 300 cai->cai_associativity = AMD_L3_EDX_C_ASSOC(descs[3]); 301 cai->cai_linesize = AMD_L3_EDX_C_LS(descs[3]); 302 303 cp = cache_info_lookup(amd_cpuid_l3cache_assoc_info, 304 cai->cai_associativity); 305 if (cp != NULL) 306 cai->cai_associativity = cp->cai_associativity; 307 else 308 cai->cai_associativity = 0; /* XXX Unknown reserved */ 309 310 if (lfunc < 0x80000019) { 311 /* No 1GB Page TLB */ 312 return; 313 } 314 315 x86_cpuid(0x80000019, descs); 316 317 cai = &ci->ci_cinfo[CAI_L1_1GBDTLB]; 318 cai->cai_totalsize = AMD_L1_1GB_EAX_DTLB_ENTRIES(descs[1]); 319 cai->cai_associativity = AMD_L1_1GB_EAX_DTLB_ASSOC(descs[1]); 320 cai->cai_linesize = (1 * 1024); 321 322 cai = &ci->ci_cinfo[CAI_L1_1GBITLB]; 323 cai->cai_totalsize = AMD_L1_1GB_EAX_IUTLB_ENTRIES(descs[0]); 324 cai->cai_associativity = AMD_L1_1GB_EAX_IUTLB_ASSOC(descs[0]); 325 cai->cai_linesize = (1 * 1024); 326 327 cai = &ci->ci_cinfo[CAI_L2_1GBDTLB]; 328 cai->cai_totalsize = AMD_L2_1GB_EBX_DUTLB_ENTRIES(descs[1]); 329 cai->cai_associativity = AMD_L2_1GB_EBX_DUTLB_ASSOC(descs[1]); 330 cai->cai_linesize = (1 * 1024); 331 332 cai = &ci->ci_cinfo[CAI_L2_1GBITLB]; 333 cai->cai_totalsize = AMD_L2_1GB_EBX_IUTLB_ENTRIES(descs[0]); 334 cai->cai_associativity = AMD_L2_1GB_EBX_IUTLB_ASSOC(descs[0]); 335 cai->cai_linesize = (1 * 1024); 336 } 337 338 static void 339 cpu_probe_k5(struct cpu_info *ci) 340 { 341 int flag; 342 343 if (cpu_vendor != CPUVENDOR_AMD || 344 CPUID_TO_FAMILY(ci->ci_signature) != 5) 345 return; 346 347 if (CPUID_TO_MODEL(ci->ci_signature) == 0) { 348 /* 349 * According to the AMD Processor Recognition App Note, 350 * the AMD-K5 Model 0 uses the wrong bit to indicate 351 * support for global PTEs, instead using bit 9 (APIC) 352 * rather than bit 13 (i.e. "0x200" vs. 0x2000". Oops!). 353 */ 354 flag = ci->ci_feat_val[0]; 355 if ((flag & CPUID_APIC) != 0) 356 flag = (flag & ~CPUID_APIC) | CPUID_PGE; 357 ci->ci_feat_val[0] = flag; 358 } 359 360 cpu_probe_amd_cache(ci); 361 } 362 363 static void 364 cpu_probe_k678(struct cpu_info *ci) 365 { 366 367 if (cpu_vendor != CPUVENDOR_AMD || 368 CPUID_TO_FAMILY(ci->ci_signature) < 6) 369 return; 370 371 cpu_probe_amd_cache(ci); 372 } 373 374 static inline uint8_t 375 cyrix_read_reg(uint8_t reg) 376 { 377 378 outb(0x22, reg); 379 return inb(0x23); 380 } 381 382 static inline void 383 cyrix_write_reg(uint8_t reg, uint8_t data) 384 { 385 386 outb(0x22, reg); 387 outb(0x23, data); 388 } 389 390 static void 391 cpu_probe_cyrix_cmn(struct cpu_info *ci) 392 { 393 /* 394 * i8254 latch check routine: 395 * National Geode (formerly Cyrix MediaGX) has a serious bug in 396 * its built-in i8254-compatible clock module (cs5510 cs5520). 397 * Set the variable 'clock_broken_latch' to indicate it. 398 * 399 * This bug is not present in the cs5530, and the flag 400 * is disabled again in sys/arch/i386/pci/pcib.c if this later 401 * model device is detected. Ideally, this work-around should not 402 * even be in here, it should be in there. XXX 403 */ 404 uint8_t c3; 405 #ifndef XEN 406 extern int clock_broken_latch; 407 408 switch (ci->ci_signature) { 409 case 0x440: /* Cyrix MediaGX */ 410 case 0x540: /* GXm */ 411 clock_broken_latch = 1; 412 break; 413 } 414 #endif 415 416 /* set up various cyrix registers */ 417 /* 418 * Enable suspend on halt (powersave mode). 419 * When powersave mode is enabled, the TSC stops counting 420 * while the CPU is halted in idle() waiting for an interrupt. 421 * This means we can't use the TSC for interval time in 422 * microtime(9), and thus it is disabled here. 423 * 424 * It still makes a perfectly good cycle counter 425 * for program profiling, so long as you remember you're 426 * counting cycles, and not time. Further, if you don't 427 * mind not using powersave mode, the TSC works just fine, 428 * so this should really be optional. XXX 429 */ 430 cyrix_write_reg(0xc2, cyrix_read_reg(0xc2) | 0x08); 431 432 /* 433 * Do not disable the TSC on the Geode GX, it's reported to 434 * work fine. 435 */ 436 if (ci->ci_signature != 0x552) 437 ci->ci_feat_val[0] &= ~CPUID_TSC; 438 439 /* enable access to ccr4/ccr5 */ 440 c3 = cyrix_read_reg(0xC3); 441 cyrix_write_reg(0xC3, c3 | 0x10); 442 /* cyrix's workaround for the "coma bug" */ 443 cyrix_write_reg(0x31, cyrix_read_reg(0x31) | 0xf8); 444 cyrix_write_reg(0x32, cyrix_read_reg(0x32) | 0x7f); 445 cyrix_write_reg(0x33, cyrix_read_reg(0x33) & ~0xff); 446 cyrix_write_reg(0x3c, cyrix_read_reg(0x3c) | 0x87); 447 /* disable access to ccr4/ccr5 */ 448 cyrix_write_reg(0xC3, c3); 449 } 450 451 static void 452 cpu_probe_cyrix(struct cpu_info *ci) 453 { 454 455 if (cpu_vendor != CPUVENDOR_CYRIX || 456 CPUID_TO_FAMILY(ci->ci_signature) < 4 || 457 CPUID_TO_FAMILY(ci->ci_signature) > 6) 458 return; 459 460 cpu_probe_cyrix_cmn(ci); 461 } 462 463 static void 464 cpu_probe_winchip(struct cpu_info *ci) 465 { 466 467 if (cpu_vendor != CPUVENDOR_IDT) 468 return; 469 470 switch (CPUID_TO_FAMILY(ci->ci_signature)) { 471 case 5: 472 /* WinChip C6 */ 473 if (CPUID_TO_MODEL(ci->ci_signature) == 4) 474 ci->ci_feat_val[0] &= ~CPUID_TSC; 475 break; 476 case 6: 477 /* 478 * VIA Eden ESP 479 * 480 * Quoting from page 3-4 of: "VIA Eden ESP Processor Datasheet" 481 * http://www.via.com.tw/download/mainboards/6/14/Eden20v115.pdf 482 * 483 * 1. The CMPXCHG8B instruction is provided and always enabled, 484 * however, it appears disabled in the corresponding CPUID 485 * function bit 0 to avoid a bug in an early version of 486 * Windows NT. However, this default can be changed via a 487 * bit in the FCR MSR. 488 */ 489 ci->ci_feat_val[0] |= CPUID_CX8; 490 wrmsr(MSR_VIA_FCR, rdmsr(MSR_VIA_FCR) | 0x00000001); 491 break; 492 } 493 } 494 495 static void 496 cpu_probe_c3(struct cpu_info *ci) 497 { 498 u_int family, model, stepping, descs[4], lfunc, msr; 499 struct x86_cache_info *cai; 500 501 if (cpu_vendor != CPUVENDOR_IDT || 502 CPUID_TO_FAMILY(ci->ci_signature) < 6) 503 return; 504 505 family = CPUID_TO_FAMILY(ci->ci_signature); 506 model = CPUID_TO_MODEL(ci->ci_signature); 507 stepping = CPUID_TO_STEPPING(ci->ci_signature); 508 509 /* Determine the largest extended function value. */ 510 x86_cpuid(0x80000000, descs); 511 lfunc = descs[0]; 512 513 if (family > 6 || model > 0x9 || (model == 0x9 && stepping >= 3)) { 514 /* Nehemiah or Esther */ 515 x86_cpuid(0xc0000000, descs); 516 lfunc = descs[0]; 517 if (lfunc >= 0xc0000001) { /* has ACE, RNG */ 518 int rng_enable = 0, ace_enable = 0; 519 x86_cpuid(0xc0000001, descs); 520 lfunc = descs[3]; 521 ci->ci_feat_val[4] = lfunc; 522 /* Check for and enable RNG */ 523 if (lfunc & CPUID_VIA_HAS_RNG) { 524 if (!(lfunc & CPUID_VIA_DO_RNG)) { 525 rng_enable++; 526 ci->ci_feat_val[4] |= CPUID_VIA_DO_RNG; 527 } 528 } 529 /* Check for and enable ACE (AES-CBC) */ 530 if (lfunc & CPUID_VIA_HAS_ACE) { 531 if (!(lfunc & CPUID_VIA_DO_ACE)) { 532 ace_enable++; 533 ci->ci_feat_val[4] |= CPUID_VIA_DO_ACE; 534 } 535 } 536 /* Check for and enable SHA */ 537 if (lfunc & CPUID_VIA_HAS_PHE) { 538 if (!(lfunc & CPUID_VIA_DO_PHE)) { 539 ace_enable++; 540 ci->ci_feat_val[4] |= CPUID_VIA_DO_PHE; 541 } 542 } 543 /* Check for and enable ACE2 (AES-CTR) */ 544 if (lfunc & CPUID_VIA_HAS_ACE2) { 545 if (!(lfunc & CPUID_VIA_DO_ACE2)) { 546 ace_enable++; 547 ci->ci_feat_val[4] |= CPUID_VIA_DO_ACE2; 548 } 549 } 550 /* Check for and enable PMM (modmult engine) */ 551 if (lfunc & CPUID_VIA_HAS_PMM) { 552 if (!(lfunc & CPUID_VIA_DO_PMM)) { 553 ace_enable++; 554 ci->ci_feat_val[4] |= CPUID_VIA_DO_PMM; 555 } 556 } 557 558 /* Actually do the enables. */ 559 if (rng_enable) { 560 msr = rdmsr(MSR_VIA_RNG); 561 wrmsr(MSR_VIA_RNG, msr | MSR_VIA_RNG_ENABLE); 562 } 563 if (ace_enable) { 564 msr = rdmsr(MSR_VIA_ACE); 565 wrmsr(MSR_VIA_ACE, msr | MSR_VIA_ACE_ENABLE); 566 } 567 568 } 569 } 570 571 /* 572 * Determine L1 cache/TLB info. 573 */ 574 if (lfunc < 0x80000005) { 575 /* No L1 cache info available. */ 576 return; 577 } 578 579 x86_cpuid(0x80000005, descs); 580 581 cai = &ci->ci_cinfo[CAI_ITLB]; 582 cai->cai_totalsize = VIA_L1_EBX_ITLB_ENTRIES(descs[1]); 583 cai->cai_associativity = VIA_L1_EBX_ITLB_ASSOC(descs[1]); 584 cai->cai_linesize = (4 * 1024); 585 586 cai = &ci->ci_cinfo[CAI_DTLB]; 587 cai->cai_totalsize = VIA_L1_EBX_DTLB_ENTRIES(descs[1]); 588 cai->cai_associativity = VIA_L1_EBX_DTLB_ASSOC(descs[1]); 589 cai->cai_linesize = (4 * 1024); 590 591 cai = &ci->ci_cinfo[CAI_DCACHE]; 592 cai->cai_totalsize = VIA_L1_ECX_DC_SIZE(descs[2]); 593 cai->cai_associativity = VIA_L1_ECX_DC_ASSOC(descs[2]); 594 cai->cai_linesize = VIA_L1_EDX_IC_LS(descs[2]); 595 if (family == 6 && model == 9 && stepping == 8) { 596 /* Erratum: stepping 8 reports 4 when it should be 2 */ 597 cai->cai_associativity = 2; 598 } 599 600 cai = &ci->ci_cinfo[CAI_ICACHE]; 601 cai->cai_totalsize = VIA_L1_EDX_IC_SIZE(descs[3]); 602 cai->cai_associativity = VIA_L1_EDX_IC_ASSOC(descs[3]); 603 cai->cai_linesize = VIA_L1_EDX_IC_LS(descs[3]); 604 if (family == 6 && model == 9 && stepping == 8) { 605 /* Erratum: stepping 8 reports 4 when it should be 2 */ 606 cai->cai_associativity = 2; 607 } 608 609 /* 610 * Determine L2 cache/TLB info. 611 */ 612 if (lfunc < 0x80000006) { 613 /* No L2 cache info available. */ 614 return; 615 } 616 617 x86_cpuid(0x80000006, descs); 618 619 cai = &ci->ci_cinfo[CAI_L2CACHE]; 620 if (family > 6 || model >= 9) { 621 cai->cai_totalsize = VIA_L2N_ECX_C_SIZE(descs[2]); 622 cai->cai_associativity = VIA_L2N_ECX_C_ASSOC(descs[2]); 623 cai->cai_linesize = VIA_L2N_ECX_C_LS(descs[2]); 624 } else { 625 cai->cai_totalsize = VIA_L2_ECX_C_SIZE(descs[2]); 626 cai->cai_associativity = VIA_L2_ECX_C_ASSOC(descs[2]); 627 cai->cai_linesize = VIA_L2_ECX_C_LS(descs[2]); 628 } 629 } 630 631 static void 632 cpu_probe_geode(struct cpu_info *ci) 633 { 634 635 if (memcmp("Geode by NSC", ci->ci_vendor, 12) != 0 || 636 CPUID_TO_FAMILY(ci->ci_signature) != 5) 637 return; 638 639 cpu_probe_cyrix_cmn(ci); 640 cpu_probe_amd_cache(ci); 641 } 642 643 static void 644 cpu_probe_vortex86(struct cpu_info *ci) 645 { 646 #define PCI_MODE1_ADDRESS_REG 0x0cf8 647 #define PCI_MODE1_DATA_REG 0x0cfc 648 #define PCI_MODE1_ENABLE 0x80000000UL 649 650 uint32_t reg; 651 652 if (cpu_vendor != CPUVENDOR_VORTEX86) 653 return; 654 /* 655 * CPU model available from "Customer ID register" in 656 * North Bridge Function 0 PCI space 657 * we can't use pci_conf_read() because the PCI subsystem is not 658 * not initialised early enough 659 */ 660 661 outl(PCI_MODE1_ADDRESS_REG, PCI_MODE1_ENABLE | 0x90); 662 reg = inl(PCI_MODE1_DATA_REG); 663 664 switch(reg) { 665 case 0x31504d44: 666 strcpy(cpu_brand_string, "Vortex86SX"); 667 break; 668 case 0x32504d44: 669 strcpy(cpu_brand_string, "Vortex86DX"); 670 break; 671 case 0x33504d44: 672 strcpy(cpu_brand_string, "Vortex86MX"); 673 break; 674 default: 675 strcpy(cpu_brand_string, "Unknown Vortex86"); 676 break; 677 } 678 679 #undef PCI_MODE1_ENABLE 680 #undef PCI_MODE1_ADDRESS_REG 681 #undef PCI_MODE1_DATA_REG 682 } 683 684 #if !defined(__i386__) || defined(XEN) 685 #define cpu_probe_old_fpu(ci) 686 #else 687 static void 688 cpu_probe_old_fpu(struct cpu_info *ci) 689 { 690 uint16_t control; 691 692 /* Check that there really is an fpu (496SX) */ 693 clts(); 694 fninit(); 695 /* Read default control word */ 696 fnstcw(&control); 697 if (control != __INITIAL_NPXCW__) { 698 /* Must be a 486SX, trap FP instructions */ 699 lcr0((rcr0() & ~CR0_MP) | CR0_EM); 700 i386_fpu_present = 0; 701 return; 702 } 703 704 /* Check for 'FDIV' bug on the original Pentium */ 705 if (npx586bug1(4195835, 3145727) != 0) 706 /* NB 120+MHz cpus are not affected */ 707 i386_fpu_fdivbug = 1; 708 709 stts(); 710 } 711 #endif 712 713 static void 714 cpu_probe_fpu(struct cpu_info *ci) 715 { 716 u_int descs[4]; 717 718 #ifdef i386 /* amd64 always has fxsave, sse and sse2 */ 719 /* If we have FXSAVE/FXRESTOR, use them. */ 720 if ((ci->ci_feat_val[0] & CPUID_FXSR) == 0) { 721 i386_use_fxsave = 0; 722 /* Allow for no fpu even if cpuid is supported */ 723 cpu_probe_old_fpu(ci); 724 return; 725 } 726 727 i386_use_fxsave = 1; 728 /* 729 * If we have SSE/SSE2, enable XMM exceptions, and 730 * notify userland. 731 */ 732 if (ci->ci_feat_val[0] & CPUID_SSE) 733 i386_has_sse = 1; 734 if (ci->ci_feat_val[0] & CPUID_SSE2) 735 i386_has_sse2 = 1; 736 #else 737 /* 738 * For amd64 i386_use_fxsave, i386_has_sse and i386_has_sse2 are 739 * #defined to 1. 740 */ 741 #endif /* i386 */ 742 743 x86_fpu_save = FPU_SAVE_FXSAVE; 744 745 /* See if xsave (for AVX is supported) */ 746 if ((ci->ci_feat_val[1] & CPUID2_XSAVE) == 0) 747 return; 748 749 x86_fpu_save = FPU_SAVE_XSAVE; 750 751 /* xsaveopt ought to be faster than xsave */ 752 x86_cpuid2(0xd, 1, descs); 753 if (descs[0] & CPUID_PES1_XSAVEOPT) 754 x86_fpu_save = FPU_SAVE_XSAVEOPT; 755 756 /* Get features and maximum size of the save area */ 757 x86_cpuid(0xd, descs); 758 /* XXX these probably ought to be per-cpu */ 759 if (descs[2] > 512) 760 x86_fpu_save_size = descs[2]; 761 x86_xsave_features = (uint64_t)descs[3] << 32 | descs[0]; 762 } 763 764 void 765 cpu_probe(struct cpu_info *ci) 766 { 767 u_int descs[4]; 768 int i; 769 uint32_t miscbytes; 770 uint32_t brand[12]; 771 772 cpu_vendor = i386_nocpuid_cpus[cputype << 1]; 773 cpu_class = i386_nocpuid_cpus[(cputype << 1) + 1]; 774 775 if (cpuid_level < 0) { 776 /* cpuid instruction not supported */ 777 cpu_probe_old_fpu(ci); 778 return; 779 } 780 781 for (i = 0; i < __arraycount(ci->ci_feat_val); i++) { 782 ci->ci_feat_val[i] = 0; 783 } 784 785 x86_cpuid(0, descs); 786 cpuid_level = descs[0]; 787 ci->ci_max_cpuid = descs[0]; 788 789 ci->ci_vendor[0] = descs[1]; 790 ci->ci_vendor[2] = descs[2]; 791 ci->ci_vendor[1] = descs[3]; 792 ci->ci_vendor[3] = 0; 793 794 if (memcmp(ci->ci_vendor, "GenuineIntel", 12) == 0) 795 cpu_vendor = CPUVENDOR_INTEL; 796 else if (memcmp(ci->ci_vendor, "AuthenticAMD", 12) == 0) 797 cpu_vendor = CPUVENDOR_AMD; 798 else if (memcmp(ci->ci_vendor, "CyrixInstead", 12) == 0) 799 cpu_vendor = CPUVENDOR_CYRIX; 800 else if (memcmp(ci->ci_vendor, "Geode by NSC", 12) == 0) 801 cpu_vendor = CPUVENDOR_CYRIX; 802 else if (memcmp(ci->ci_vendor, "CentaurHauls", 12) == 0) 803 cpu_vendor = CPUVENDOR_IDT; 804 else if (memcmp(ci->ci_vendor, "GenuineTMx86", 12) == 0) 805 cpu_vendor = CPUVENDOR_TRANSMETA; 806 else if (memcmp(ci->ci_vendor, "Vortex86 SoC", 12) == 0) 807 cpu_vendor = CPUVENDOR_VORTEX86; 808 else 809 cpu_vendor = CPUVENDOR_UNKNOWN; 810 811 if (cpuid_level >= 1) { 812 x86_cpuid(1, descs); 813 ci->ci_signature = descs[0]; 814 miscbytes = descs[1]; 815 ci->ci_feat_val[1] = descs[2]; 816 ci->ci_feat_val[0] = descs[3]; 817 818 /* Determine family + class. */ 819 cpu_class = CPUID_TO_FAMILY(ci->ci_signature) 820 + (CPUCLASS_386 - 3); 821 if (cpu_class > CPUCLASS_686) 822 cpu_class = CPUCLASS_686; 823 824 /* CLFLUSH line size is next 8 bits */ 825 if (ci->ci_feat_val[0] & CPUID_CFLUSH) 826 ci->ci_cflush_lsize = ((miscbytes >> 8) & 0xff) << 3; 827 ci->ci_initapicid = (miscbytes >> 24) & 0xff; 828 } 829 830 /* 831 * Get the basic information from the extended cpuid leafs. 832 * These were first implemented by amd, but most of the values 833 * match with those generated by modern intel cpus. 834 */ 835 x86_cpuid(0x80000000, descs); 836 if (descs[0] >= 0x80000000) 837 ci->ci_max_ext_cpuid = descs[0]; 838 else 839 ci->ci_max_ext_cpuid = 0; 840 841 if (ci->ci_max_ext_cpuid >= 0x80000001) { 842 /* Determine the extended feature flags. */ 843 x86_cpuid(0x80000001, descs); 844 ci->ci_feat_val[3] = descs[2]; /* %ecx */ 845 ci->ci_feat_val[2] = descs[3]; /* %edx */ 846 } 847 848 if (ci->ci_max_ext_cpuid >= 0x80000004) { 849 x86_cpuid(0x80000002, brand); 850 x86_cpuid(0x80000003, brand + 4); 851 x86_cpuid(0x80000004, brand + 8); 852 /* Skip leading spaces on brand */ 853 for (i = 0; i < 48; i++) { 854 if (((char *) brand)[i] != ' ') 855 break; 856 } 857 memcpy(cpu_brand_string, ((char *) brand) + i, 48 - i); 858 } 859 860 cpu_probe_intel(ci); 861 cpu_probe_k5(ci); 862 cpu_probe_k678(ci); 863 cpu_probe_cyrix(ci); 864 cpu_probe_winchip(ci); 865 cpu_probe_c3(ci); 866 cpu_probe_geode(ci); 867 cpu_probe_vortex86(ci); 868 869 cpu_probe_fpu(ci); 870 871 x86_cpu_topology(ci); 872 873 if (cpu_vendor != CPUVENDOR_AMD && (ci->ci_feat_val[0] & CPUID_TM) && 874 (rdmsr(MSR_MISC_ENABLE) & (1 << 3)) == 0) { 875 /* Enable thermal monitor 1. */ 876 wrmsr(MSR_MISC_ENABLE, rdmsr(MSR_MISC_ENABLE) | (1<<3)); 877 } 878 879 ci->ci_feat_val[0] &= ~CPUID_FEAT_BLACKLIST; 880 if (ci == &cpu_info_primary) { 881 /* If first. Boot Processor is the cpu_feature reference. */ 882 for (i = 0; i < __arraycount(cpu_feature); i++) { 883 cpu_feature[i] = ci->ci_feat_val[i]; 884 } 885 #ifndef XEN 886 /* Early patch of text segment. */ 887 x86_patch(true); 888 #endif 889 } else { 890 /* 891 * If not first. Warn about cpu_feature mismatch for 892 * secondary CPUs. 893 */ 894 for (i = 0; i < __arraycount(cpu_feature); i++) { 895 if (cpu_feature[i] != ci->ci_feat_val[i]) 896 aprint_error_dev(ci->ci_dev, 897 "feature mismatch: cpu_feature[%d] is " 898 "%#x, but CPU reported %#x\n", 899 i, cpu_feature[i], ci->ci_feat_val[i]); 900 } 901 } 902 } 903 904 /* Write what we know about the cpu to the console... */ 905 void 906 cpu_identify(struct cpu_info *ci) 907 { 908 909 snprintf(cpu_model, sizeof(cpu_model), "%s %d86-class", 910 cpu_vendor_names[cpu_vendor], cpu_class + 3); 911 if (cpu_brand_string[0] != '\0') { 912 aprint_normal(": %s", cpu_brand_string); 913 } else { 914 aprint_normal(": %s", cpu_model); 915 if (ci->ci_data.cpu_cc_freq != 0) 916 aprint_normal(", %dMHz", 917 (int)(ci->ci_data.cpu_cc_freq / 1000000)); 918 } 919 if (ci->ci_signature != 0) 920 aprint_normal(", id 0x%x", ci->ci_signature); 921 aprint_normal("\n"); 922 923 if (cpu_brand_string[0] == '\0') { 924 strlcpy(cpu_brand_string, cpu_model, sizeof(cpu_brand_string)); 925 } 926 if (cpu_class == CPUCLASS_386) { 927 panic("NetBSD requires an 80486DX or later processor"); 928 } 929 if (cputype == CPU_486DLC) { 930 aprint_error("WARNING: BUGGY CYRIX CACHE\n"); 931 } 932 933 #if !defined(XEN) || defined(DOM0OPS) /* on Xen rdmsr is for Dom0 only */ 934 if (cpu_vendor == CPUVENDOR_AMD /* check enablement of an */ 935 && device_unit(ci->ci_dev) == 0 /* AMD feature only once */ 936 && ((cpu_feature[3] & CPUID_SVM) == CPUID_SVM)) { 937 uint64_t val; 938 939 val = rdmsr(MSR_VMCR); 940 if (((val & VMCR_SVMED) == VMCR_SVMED) 941 && ((val & VMCR_LOCK) == VMCR_LOCK)) { 942 aprint_normal_dev(ci->ci_dev, 943 "SVM disabled by the BIOS\n"); 944 } 945 } 946 #endif 947 948 #ifdef i386 949 if (i386_fpu_present == 0) 950 aprint_normal_dev(ci->ci_dev, "no fpu\n"); 951 952 if (i386_fpu_fdivbug == 1) 953 aprint_normal_dev(ci->ci_dev, 954 "WARNING: Pentium FDIV bug detected!\n"); 955 956 if (cpu_vendor == CPUVENDOR_TRANSMETA) { 957 u_int descs[4]; 958 x86_cpuid(0x80860000, descs); 959 if (descs[0] >= 0x80860007) 960 /* Create longrun sysctls */ 961 tmx86_init_longrun(); 962 } 963 #endif /* i386 */ 964 965 } 966