1 /* $NetBSD: pci_machdep.c,v 1.77 2017/02/09 03:38:01 msaitoh Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved. 35 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 1. Redistributions of source code must retain the above copyright 41 * notice, this list of conditions and the following disclaimer. 42 * 2. Redistributions in binary form must reproduce the above copyright 43 * notice, this list of conditions and the following disclaimer in the 44 * documentation and/or other materials provided with the distribution. 45 * 3. All advertising materials mentioning features or use of this software 46 * must display the following acknowledgement: 47 * This product includes software developed by Charles M. Hannum. 48 * 4. The name of the author may not be used to endorse or promote products 49 * derived from this software without specific prior written permission. 50 * 51 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 52 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 53 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 54 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 55 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 56 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 57 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 58 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 59 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 60 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 61 */ 62 63 /* 64 * Machine-specific functions for PCI autoconfiguration. 65 * 66 * On PCs, there are two methods of generating PCI configuration cycles. 67 * We try to detect the appropriate mechanism for this machine and set 68 * up a few function pointers to access the correct method directly. 69 * 70 * The configuration method can be hard-coded in the config file by 71 * using `options PCI_CONF_MODE=N', where `N' is the configuration mode 72 * as defined in section 3.6.4.1, `Generating Configuration Cycles'. 73 */ 74 75 #include <sys/cdefs.h> 76 __KERNEL_RCSID(0, "$NetBSD: pci_machdep.c,v 1.77 2017/02/09 03:38:01 msaitoh Exp $"); 77 78 #include <sys/types.h> 79 #include <sys/param.h> 80 #include <sys/time.h> 81 #include <sys/systm.h> 82 #include <sys/errno.h> 83 #include <sys/device.h> 84 #include <sys/bus.h> 85 #include <sys/cpu.h> 86 #include <sys/kmem.h> 87 88 #include <uvm/uvm_extern.h> 89 90 #include <machine/bus_private.h> 91 92 #include <machine/pio.h> 93 #include <machine/lock.h> 94 95 #include <dev/isa/isareg.h> 96 #include <dev/isa/isavar.h> 97 #include <dev/pci/pcivar.h> 98 #include <dev/pci/pcireg.h> 99 #include <dev/pci/pccbbreg.h> 100 #include <dev/pci/pcidevs.h> 101 #include <dev/pci/genfb_pcivar.h> 102 103 #include <dev/wsfb/genfbvar.h> 104 #include <arch/x86/include/genfb_machdep.h> 105 #include <dev/ic/vgareg.h> 106 107 #include "acpica.h" 108 #include "genfb.h" 109 #include "isa.h" 110 #include "opt_acpi.h" 111 #include "opt_ddb.h" 112 #include "opt_mpbios.h" 113 #include "opt_puc.h" 114 #include "opt_vga.h" 115 #include "pci.h" 116 #include "wsdisplay.h" 117 #include "com.h" 118 119 #ifdef DDB 120 #include <machine/db_machdep.h> 121 #include <ddb/db_sym.h> 122 #include <ddb/db_extern.h> 123 #endif 124 125 #ifdef VGA_POST 126 #include <x86/vga_post.h> 127 #endif 128 129 #include <x86/cpuvar.h> 130 131 #include <machine/autoconf.h> 132 #include <machine/bootinfo.h> 133 134 #ifdef MPBIOS 135 #include <machine/mpbiosvar.h> 136 #endif 137 138 #if NACPICA > 0 139 #include <machine/mpacpi.h> 140 #if !defined(NO_PCI_EXTENDED_CONFIG) 141 #include <dev/acpi/acpivar.h> 142 #include <dev/acpi/acpi_mcfg.h> 143 #endif 144 #endif 145 146 #include <machine/mpconfig.h> 147 148 #if NCOM > 0 149 #include <dev/pci/puccn.h> 150 #endif 151 152 #include "opt_pci_conf_mode.h" 153 154 #ifdef PCI_CONF_MODE 155 #if (PCI_CONF_MODE == 1) || (PCI_CONF_MODE == 2) 156 static int pci_mode = PCI_CONF_MODE; 157 #else 158 #error Invalid PCI configuration mode. 159 #endif 160 #else 161 static int pci_mode = -1; 162 #endif 163 164 struct pci_conf_lock { 165 uint32_t cl_cpuno; /* 0: unlocked 166 * 1 + n: locked by CPU n (0 <= n) 167 */ 168 uint32_t cl_sel; /* the address that's being read. */ 169 }; 170 171 static void pci_conf_unlock(struct pci_conf_lock *); 172 static uint32_t pci_conf_selector(pcitag_t, int); 173 static unsigned int pci_conf_port(pcitag_t, int); 174 static void pci_conf_select(uint32_t); 175 static void pci_conf_lock(struct pci_conf_lock *, uint32_t); 176 static void pci_bridge_hook(pci_chipset_tag_t, pcitag_t, void *); 177 struct pci_bridge_hook_arg { 178 void (*func)(pci_chipset_tag_t, pcitag_t, void *); 179 void *arg; 180 }; 181 182 #define PCI_MODE1_ENABLE 0x80000000UL 183 #define PCI_MODE1_ADDRESS_REG 0x0cf8 184 #define PCI_MODE1_DATA_REG 0x0cfc 185 186 #define PCI_MODE2_ENABLE_REG 0x0cf8 187 #define PCI_MODE2_FORWARD_REG 0x0cfa 188 189 #define _tag(b, d, f) \ 190 {.mode1 = PCI_MODE1_ENABLE | ((b) << 16) | ((d) << 11) | ((f) << 8)} 191 #define _qe(bus, dev, fcn, vend, prod) \ 192 {_tag(bus, dev, fcn), PCI_ID_CODE(vend, prod)} 193 const struct { 194 pcitag_t tag; 195 pcireg_t id; 196 } pcim1_quirk_tbl[] = { 197 _qe(0, 0, 0, PCI_VENDOR_INVALID, 0x0000), /* patchable */ 198 _qe(0, 0, 0, PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_TRIFLEX1), 199 /* XXX Triflex2 not tested */ 200 _qe(0, 0, 0, PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_TRIFLEX2), 201 _qe(0, 0, 0, PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_TRIFLEX4), 202 /* Triton needed for Connectix Virtual PC */ 203 _qe(0, 0, 0, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82437FX), 204 /* Connectix Virtual PC 5 has a 440BX */ 205 _qe(0, 0, 0, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82443BX_NOAGP), 206 /* Parallels Desktop for Mac */ 207 _qe(0, 2, 0, PCI_VENDOR_PARALLELS, PCI_PRODUCT_PARALLELS_VIDEO), 208 _qe(0, 3, 0, PCI_VENDOR_PARALLELS, PCI_PRODUCT_PARALLELS_TOOLS), 209 /* SIS 740 */ 210 _qe(0, 0, 0, PCI_VENDOR_SIS, PCI_PRODUCT_SIS_740), 211 /* SIS 741 */ 212 _qe(0, 0, 0, PCI_VENDOR_SIS, PCI_PRODUCT_SIS_741), 213 /* VIA Technologies VX900 */ 214 _qe(0, 0, 0, PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VX900_HB) 215 }; 216 #undef _tag 217 #undef _qe 218 219 /* arch/xen does not support MSI/MSI-X yet. */ 220 #ifdef __HAVE_PCI_MSI_MSIX 221 #define PCI_QUIRK_DISABLE_MSI 1 /* Neigher MSI nor MSI-X work */ 222 #define PCI_QUIRK_DISABLE_MSIX 2 /* MSI-X does not work */ 223 #define PCI_QUIRK_ENABLE_MSI_VM 3 /* Older chipset in VM where MSI and MSI-X works */ 224 225 #define _dme(vend, prod) \ 226 { PCI_QUIRK_DISABLE_MSI, PCI_ID_CODE(vend, prod) } 227 #define _dmxe(vend, prod) \ 228 { PCI_QUIRK_DISABLE_MSIX, PCI_ID_CODE(vend, prod) } 229 #define _emve(vend, prod) \ 230 { PCI_QUIRK_ENABLE_MSI_VM, PCI_ID_CODE(vend, prod) } 231 const struct { 232 int type; 233 pcireg_t id; 234 } pci_msi_quirk_tbl[] = { 235 _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PCMC), 236 _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82437FX), 237 _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82437MX), 238 _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82437VX), 239 _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82439HX), 240 _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82439TX), 241 _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82443GX), 242 _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82443GX_AGP), 243 _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82440MX), 244 _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82441FX), 245 _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82443BX), 246 _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82443BX_AGP), 247 _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82443BX_NOAGP), 248 _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82443GX_NOAGP), 249 _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82443LX), 250 _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82443LX_AGP), 251 _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82810_MCH), 252 _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82810E_MCH), 253 _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82815_FULL_HUB), 254 _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82820_MCH), 255 _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82830MP_IO_1), 256 _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82840_HB), 257 _dme(PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE_PCHB), 258 _dme(PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_PCHB), 259 _dme(PCI_VENDOR_AMD, PCI_PRODUCT_AMD_SC751_SC), 260 _dme(PCI_VENDOR_AMD, PCI_PRODUCT_AMD_SC761_SC), 261 _dme(PCI_VENDOR_AMD, PCI_PRODUCT_AMD_SC762_NB), 262 263 _emve(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82441FX), /* QEMU */ 264 _emve(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82443BX), /* VMWare */ 265 }; 266 #undef _dme 267 #undef _dmxe 268 #undef _emve 269 #endif /* __HAVE_PCI_MSI_MSIX */ 270 271 /* 272 * PCI doesn't have any special needs; just use the generic versions 273 * of these functions. 274 */ 275 struct x86_bus_dma_tag pci_bus_dma_tag = { 276 ._tag_needs_free = 0, 277 #if defined(_LP64) || defined(PAE) 278 ._bounce_thresh = PCI32_DMA_BOUNCE_THRESHOLD, 279 ._bounce_alloc_lo = ISA_DMA_BOUNCE_THRESHOLD, 280 ._bounce_alloc_hi = PCI32_DMA_BOUNCE_THRESHOLD, 281 #else 282 ._bounce_thresh = 0, 283 ._bounce_alloc_lo = 0, 284 ._bounce_alloc_hi = 0, 285 #endif 286 ._may_bounce = NULL, 287 }; 288 289 #ifdef _LP64 290 struct x86_bus_dma_tag pci_bus_dma64_tag = { 291 ._tag_needs_free = 0, 292 ._bounce_thresh = 0, 293 ._bounce_alloc_lo = 0, 294 ._bounce_alloc_hi = 0, 295 ._may_bounce = NULL, 296 }; 297 #endif 298 299 static struct pci_conf_lock cl0 = { 300 .cl_cpuno = 0UL 301 , .cl_sel = 0UL 302 }; 303 304 static struct pci_conf_lock * const cl = &cl0; 305 306 #if NGENFB > 0 && NACPICA > 0 && defined(VGA_POST) 307 extern int acpi_md_vbios_reset; 308 extern int acpi_md_vesa_modenum; 309 #endif 310 311 static struct genfb_colormap_callback gfb_cb; 312 static struct genfb_pmf_callback pmf_cb; 313 static struct genfb_mode_callback mode_cb; 314 #ifdef VGA_POST 315 static struct vga_post *vga_posth = NULL; 316 #endif 317 318 static void 319 pci_conf_lock(struct pci_conf_lock *ocl, uint32_t sel) 320 { 321 uint32_t cpuno; 322 323 KASSERT(sel != 0); 324 325 kpreempt_disable(); 326 cpuno = cpu_number() + 1; 327 /* If the kernel enters pci_conf_lock() through an interrupt 328 * handler, then the CPU may already hold the lock. 329 * 330 * If the CPU does not already hold the lock, spin until 331 * we can acquire it. 332 */ 333 if (cpuno == cl->cl_cpuno) { 334 ocl->cl_cpuno = cpuno; 335 } else { 336 u_int spins; 337 338 ocl->cl_cpuno = 0; 339 340 spins = SPINLOCK_BACKOFF_MIN; 341 while (atomic_cas_32(&cl->cl_cpuno, 0, cpuno) != 0) { 342 SPINLOCK_BACKOFF(spins); 343 #ifdef LOCKDEBUG 344 if (SPINLOCK_SPINOUT(spins)) { 345 panic("%s: cpu %" PRId32 346 " spun out waiting for cpu %" PRId32, 347 __func__, cpuno, cl->cl_cpuno); 348 } 349 #endif /* LOCKDEBUG */ 350 } 351 } 352 353 /* Only one CPU can be here, so an interlocked atomic_swap(3) 354 * is not necessary. 355 * 356 * Evaluating atomic_cas_32_ni()'s argument, cl->cl_sel, 357 * and applying atomic_cas_32_ni() is not an atomic operation, 358 * however, any interrupt that, in the middle of the 359 * operation, modifies cl->cl_sel, will also restore 360 * cl->cl_sel. So cl->cl_sel will have the same value when 361 * we apply atomic_cas_32_ni() as when we evaluated it, 362 * before. 363 */ 364 ocl->cl_sel = atomic_cas_32_ni(&cl->cl_sel, cl->cl_sel, sel); 365 pci_conf_select(sel); 366 } 367 368 static void 369 pci_conf_unlock(struct pci_conf_lock *ocl) 370 { 371 atomic_cas_32_ni(&cl->cl_sel, cl->cl_sel, ocl->cl_sel); 372 pci_conf_select(ocl->cl_sel); 373 if (ocl->cl_cpuno != cl->cl_cpuno) 374 atomic_cas_32(&cl->cl_cpuno, cl->cl_cpuno, ocl->cl_cpuno); 375 kpreempt_enable(); 376 } 377 378 static uint32_t 379 pci_conf_selector(pcitag_t tag, int reg) 380 { 381 static const pcitag_t mode2_mask = { 382 .mode2 = { 383 .enable = 0xff 384 , .forward = 0xff 385 } 386 }; 387 388 switch (pci_mode) { 389 case 1: 390 return tag.mode1 | reg; 391 case 2: 392 return tag.mode1 & mode2_mask.mode1; 393 default: 394 panic("%s: mode %d not configured", __func__, pci_mode); 395 } 396 } 397 398 static unsigned int 399 pci_conf_port(pcitag_t tag, int reg) 400 { 401 switch (pci_mode) { 402 case 1: 403 return PCI_MODE1_DATA_REG; 404 case 2: 405 return tag.mode2.port | reg; 406 default: 407 panic("%s: mode %d not configured", __func__, pci_mode); 408 } 409 } 410 411 static void 412 pci_conf_select(uint32_t sel) 413 { 414 pcitag_t tag; 415 416 switch (pci_mode) { 417 case 1: 418 outl(PCI_MODE1_ADDRESS_REG, sel); 419 return; 420 case 2: 421 tag.mode1 = sel; 422 outb(PCI_MODE2_ENABLE_REG, tag.mode2.enable); 423 if (tag.mode2.enable != 0) 424 outb(PCI_MODE2_FORWARD_REG, tag.mode2.forward); 425 return; 426 default: 427 panic("%s: mode %d not configured", __func__, pci_mode); 428 } 429 } 430 431 #ifdef __HAVE_PCI_MSI_MSIX 432 static int 433 pci_has_msi_quirk(pcireg_t id, int type) 434 { 435 int i; 436 437 for (i = 0; i < __arraycount(pci_msi_quirk_tbl); i++) { 438 if (id == pci_msi_quirk_tbl[i].id && 439 type == pci_msi_quirk_tbl[i].type) 440 return 1; 441 } 442 443 return 0; 444 } 445 #endif 446 447 void 448 pci_attach_hook(device_t parent, device_t self, struct pcibus_attach_args *pba) 449 { 450 #ifdef __HAVE_PCI_MSI_MSIX 451 pci_chipset_tag_t pc = pba->pba_pc; 452 pcitag_t tag; 453 pcireg_t id, class; 454 #endif 455 456 if (pba->pba_bus == 0) 457 aprint_normal(": configuration mode %d", pci_mode); 458 #ifdef MPBIOS 459 mpbios_pci_attach_hook(parent, self, pba); 460 #endif 461 #if NACPICA > 0 462 mpacpi_pci_attach_hook(parent, self, pba); 463 #endif 464 #if NACPICA > 0 && !defined(NO_PCI_EXTENDED_CONFIG) 465 acpimcfg_map_bus(self, pba->pba_pc, pba->pba_bus); 466 #endif 467 468 #ifdef __HAVE_PCI_MSI_MSIX 469 /* 470 * In order to decide whether the system supports MSI we look 471 * at the host bridge, which should be device 0 function 0 on 472 * bus 0. It is better to not enable MSI on systems that 473 * support it than the other way around, so be conservative 474 * here. So we don't enable MSI if we don't find a host 475 * bridge there. We also deliberately don't enable MSI on 476 * chipsets from low-end manifacturers like VIA and SiS. 477 */ 478 tag = pci_make_tag(pc, 0, 0, 0); 479 id = pci_conf_read(pc, tag, PCI_ID_REG); 480 class = pci_conf_read(pc, tag, PCI_CLASS_REG); 481 482 if (PCI_CLASS(class) != PCI_CLASS_BRIDGE || 483 PCI_SUBCLASS(class) != PCI_SUBCLASS_BRIDGE_HOST) 484 return; 485 486 /* VMware and KVM use old chipset, but they can use MSI/MSI-X */ 487 if ((cpu_feature[1] & CPUID2_RAZ) 488 && (pci_has_msi_quirk(id, PCI_QUIRK_ENABLE_MSI_VM))) { 489 pba->pba_flags |= PCI_FLAGS_MSI_OKAY; 490 pba->pba_flags |= PCI_FLAGS_MSIX_OKAY; 491 } else if (pci_has_msi_quirk(id, PCI_QUIRK_DISABLE_MSI)) { 492 pba->pba_flags &= ~PCI_FLAGS_MSI_OKAY; 493 pba->pba_flags &= ~PCI_FLAGS_MSIX_OKAY; 494 aprint_verbose("\n"); 495 aprint_verbose_dev(self, 496 "This pci host supports neither MSI nor MSI-X."); 497 } else if (pci_has_msi_quirk(id, PCI_QUIRK_DISABLE_MSIX)) { 498 pba->pba_flags |= PCI_FLAGS_MSI_OKAY; 499 pba->pba_flags &= ~PCI_FLAGS_MSIX_OKAY; 500 aprint_verbose("\n"); 501 aprint_verbose_dev(self, 502 "This pci host does not support MSI-X."); 503 } else { 504 pba->pba_flags |= PCI_FLAGS_MSI_OKAY; 505 pba->pba_flags |= PCI_FLAGS_MSIX_OKAY; 506 } 507 508 /* 509 * Don't enable MSI on a HyperTransport bus. In order to 510 * determine that bus 0 is a HyperTransport bus, we look at 511 * device 24 function 0, which is the HyperTransport 512 * host/primary interface integrated on most 64-bit AMD CPUs. 513 * If that device has a HyperTransport capability, bus 0 must 514 * be a HyperTransport bus and we disable MSI. 515 */ 516 if (24 < pci_bus_maxdevs(pc, 0)) { 517 tag = pci_make_tag(pc, 0, 24, 0); 518 if (pci_get_capability(pc, tag, PCI_CAP_LDT, NULL, NULL)) { 519 pba->pba_flags &= ~PCI_FLAGS_MSI_OKAY; 520 pba->pba_flags &= ~PCI_FLAGS_MSIX_OKAY; 521 } 522 } 523 #endif /* __HAVE_PCI_MSI_MSIX */ 524 } 525 526 int 527 pci_bus_maxdevs(pci_chipset_tag_t pc, int busno) 528 { 529 /* 530 * Bus number is irrelevant. If Configuration Mechanism 2 is in 531 * use, can only have devices 0-15 on any bus. If Configuration 532 * Mechanism 1 is in use, can have devices 0-32 (i.e. the `normal' 533 * range). 534 */ 535 if (pci_mode == 2) 536 return (16); 537 else 538 return (32); 539 } 540 541 pcitag_t 542 pci_make_tag(pci_chipset_tag_t pc, int bus, int device, int function) 543 { 544 pci_chipset_tag_t ipc; 545 pcitag_t tag; 546 547 for (ipc = pc; ipc != NULL; ipc = ipc->pc_super) { 548 if ((ipc->pc_present & PCI_OVERRIDE_MAKE_TAG) == 0) 549 continue; 550 return (*ipc->pc_ov->ov_make_tag)(ipc->pc_ctx, 551 pc, bus, device, function); 552 } 553 554 switch (pci_mode) { 555 case 1: 556 if (bus >= 256 || device >= 32 || function >= 8) 557 panic("%s: bad request(%d, %d, %d)", __func__, 558 bus, device, function); 559 560 tag.mode1 = PCI_MODE1_ENABLE | 561 (bus << 16) | (device << 11) | (function << 8); 562 return tag; 563 case 2: 564 if (bus >= 256 || device >= 16 || function >= 8) 565 panic("%s: bad request(%d, %d, %d)", __func__, 566 bus, device, function); 567 568 tag.mode2.port = 0xc000 | (device << 8); 569 tag.mode2.enable = 0xf0 | (function << 1); 570 tag.mode2.forward = bus; 571 return tag; 572 default: 573 panic("%s: mode %d not configured", __func__, pci_mode); 574 } 575 } 576 577 void 578 pci_decompose_tag(pci_chipset_tag_t pc, pcitag_t tag, 579 int *bp, int *dp, int *fp) 580 { 581 pci_chipset_tag_t ipc; 582 583 for (ipc = pc; ipc != NULL; ipc = ipc->pc_super) { 584 if ((ipc->pc_present & PCI_OVERRIDE_DECOMPOSE_TAG) == 0) 585 continue; 586 (*ipc->pc_ov->ov_decompose_tag)(ipc->pc_ctx, 587 pc, tag, bp, dp, fp); 588 return; 589 } 590 591 switch (pci_mode) { 592 case 1: 593 if (bp != NULL) 594 *bp = (tag.mode1 >> 16) & 0xff; 595 if (dp != NULL) 596 *dp = (tag.mode1 >> 11) & 0x1f; 597 if (fp != NULL) 598 *fp = (tag.mode1 >> 8) & 0x7; 599 return; 600 case 2: 601 if (bp != NULL) 602 *bp = tag.mode2.forward & 0xff; 603 if (dp != NULL) 604 *dp = (tag.mode2.port >> 8) & 0xf; 605 if (fp != NULL) 606 *fp = (tag.mode2.enable >> 1) & 0x7; 607 return; 608 default: 609 panic("%s: mode %d not configured", __func__, pci_mode); 610 } 611 } 612 613 pcireg_t 614 pci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg) 615 { 616 pci_chipset_tag_t ipc; 617 pcireg_t data; 618 struct pci_conf_lock ocl; 619 int dev; 620 621 KASSERT((reg & 0x3) == 0); 622 623 for (ipc = pc; ipc != NULL; ipc = ipc->pc_super) { 624 if ((ipc->pc_present & PCI_OVERRIDE_CONF_READ) == 0) 625 continue; 626 return (*ipc->pc_ov->ov_conf_read)(ipc->pc_ctx, pc, tag, reg); 627 } 628 629 pci_decompose_tag(pc, tag, NULL, &dev, NULL); 630 if (__predict_false(pci_mode == 2 && dev >= 16)) 631 return (pcireg_t) -1; 632 633 if (reg < 0) 634 return (pcireg_t) -1; 635 if (reg >= PCI_CONF_SIZE) { 636 #if NACPICA > 0 && !defined(NO_PCI_EXTENDED_CONFIG) 637 if (reg >= PCI_EXTCONF_SIZE) 638 return (pcireg_t) -1; 639 acpimcfg_conf_read(pc, tag, reg, &data); 640 return data; 641 #else 642 return (pcireg_t) -1; 643 #endif 644 } 645 646 pci_conf_lock(&ocl, pci_conf_selector(tag, reg)); 647 data = inl(pci_conf_port(tag, reg)); 648 pci_conf_unlock(&ocl); 649 return data; 650 } 651 652 void 653 pci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data) 654 { 655 pci_chipset_tag_t ipc; 656 struct pci_conf_lock ocl; 657 int dev; 658 659 KASSERT((reg & 0x3) == 0); 660 661 for (ipc = pc; ipc != NULL; ipc = ipc->pc_super) { 662 if ((ipc->pc_present & PCI_OVERRIDE_CONF_WRITE) == 0) 663 continue; 664 (*ipc->pc_ov->ov_conf_write)(ipc->pc_ctx, pc, tag, reg, 665 data); 666 return; 667 } 668 669 pci_decompose_tag(pc, tag, NULL, &dev, NULL); 670 if (__predict_false(pci_mode == 2 && dev >= 16)) { 671 return; 672 } 673 674 if (reg < 0) 675 return; 676 if (reg >= PCI_CONF_SIZE) { 677 #if NACPICA > 0 && !defined(NO_PCI_EXTENDED_CONFIG) 678 if (reg >= PCI_EXTCONF_SIZE) 679 return; 680 acpimcfg_conf_write(pc, tag, reg, data); 681 #endif 682 return; 683 } 684 685 pci_conf_lock(&ocl, pci_conf_selector(tag, reg)); 686 outl(pci_conf_port(tag, reg), data); 687 pci_conf_unlock(&ocl); 688 } 689 690 void 691 pci_mode_set(int mode) 692 { 693 KASSERT(pci_mode == -1 || pci_mode == mode); 694 695 pci_mode = mode; 696 } 697 698 int 699 pci_mode_detect(void) 700 { 701 uint32_t sav, val; 702 int i; 703 pcireg_t idreg; 704 extern char cpu_brand_string[]; 705 706 if (pci_mode != -1) 707 return pci_mode; 708 709 /* 710 * We try to divine which configuration mode the host bridge wants. 711 */ 712 713 sav = inl(PCI_MODE1_ADDRESS_REG); 714 715 pci_mode = 1; /* assume this for now */ 716 /* 717 * catch some known buggy implementations of mode 1 718 */ 719 for (i = 0; i < __arraycount(pcim1_quirk_tbl); i++) { 720 pcitag_t t; 721 722 if (PCI_VENDOR(pcim1_quirk_tbl[i].id) == PCI_VENDOR_INVALID) 723 continue; 724 t.mode1 = pcim1_quirk_tbl[i].tag.mode1; 725 idreg = pci_conf_read(NULL, t, PCI_ID_REG); /* needs "pci_mode" */ 726 if (idreg == pcim1_quirk_tbl[i].id) { 727 #ifdef DEBUG 728 printf("%s: known mode 1 PCI chipset (%08x)\n", 729 __func__, idreg); 730 #endif 731 return (pci_mode); 732 } 733 } 734 735 const char *reason, *system_vendor, *system_product; 736 if (memcmp(cpu_brand_string, "QEMU", 4) == 0) 737 /* PR 45671, https://bugs.launchpad.net/qemu/+bug/897771 */ 738 reason = "QEMU"; 739 else if ((system_vendor = pmf_get_platform("system-vendor")) != NULL && 740 strcmp(system_vendor, "Xen") == 0 && 741 (system_product = pmf_get_platform("system-product")) != NULL && 742 strcmp(system_product, "HVM domU") == 0) 743 reason = "Xen"; 744 else 745 reason = NULL; 746 747 if (reason) { 748 #ifdef DEBUG 749 printf("%s: forcing PCI mode 1 for %s\n", __func__, reason); 750 #endif 751 return (pci_mode); 752 } 753 754 /* 755 * Strong check for standard compliant mode 1: 756 * 1. bit 31 ("enable") can be set 757 * 2. byte/word access does not affect register 758 */ 759 outl(PCI_MODE1_ADDRESS_REG, PCI_MODE1_ENABLE); 760 outb(PCI_MODE1_ADDRESS_REG + 3, 0); 761 outw(PCI_MODE1_ADDRESS_REG + 2, 0); 762 val = inl(PCI_MODE1_ADDRESS_REG); 763 if ((val & 0x80fffffc) != PCI_MODE1_ENABLE) { 764 #ifdef DEBUG 765 printf("%s: mode 1 enable failed (%x)\n", __func__, val); 766 #endif 767 goto not1; 768 } 769 outl(PCI_MODE1_ADDRESS_REG, 0); 770 val = inl(PCI_MODE1_ADDRESS_REG); 771 if ((val & 0x80fffffc) != 0) 772 goto not1; 773 return (pci_mode); 774 not1: 775 outl(PCI_MODE1_ADDRESS_REG, sav); 776 777 /* 778 * This mode 2 check is quite weak (and known to give false 779 * positives on some Compaq machines). 780 * However, this doesn't matter, because this is the 781 * last test, and simply no PCI devices will be found if 782 * this happens. 783 */ 784 outb(PCI_MODE2_ENABLE_REG, 0); 785 outb(PCI_MODE2_FORWARD_REG, 0); 786 if (inb(PCI_MODE2_ENABLE_REG) != 0 || 787 inb(PCI_MODE2_FORWARD_REG) != 0) 788 goto not2; 789 return (pci_mode = 2); 790 not2: 791 792 return (pci_mode = 0); 793 } 794 795 void 796 pci_device_foreach(pci_chipset_tag_t pc, int maxbus, 797 void (*func)(pci_chipset_tag_t, pcitag_t, void *), void *context) 798 { 799 pci_device_foreach_min(pc, 0, maxbus, func, context); 800 } 801 802 void 803 pci_device_foreach_min(pci_chipset_tag_t pc, int minbus, int maxbus, 804 void (*func)(pci_chipset_tag_t, pcitag_t, void *), void *context) 805 { 806 const struct pci_quirkdata *qd; 807 int bus, device, function, maxdevs, nfuncs; 808 pcireg_t id, bhlcr; 809 pcitag_t tag; 810 811 for (bus = minbus; bus <= maxbus; bus++) { 812 maxdevs = pci_bus_maxdevs(pc, bus); 813 for (device = 0; device < maxdevs; device++) { 814 tag = pci_make_tag(pc, bus, device, 0); 815 id = pci_conf_read(pc, tag, PCI_ID_REG); 816 817 /* Invalid vendor ID value? */ 818 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 819 continue; 820 /* XXX Not invalid, but we've done this ~forever. */ 821 if (PCI_VENDOR(id) == 0) 822 continue; 823 824 qd = pci_lookup_quirkdata(PCI_VENDOR(id), 825 PCI_PRODUCT(id)); 826 827 bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 828 if (PCI_HDRTYPE_MULTIFN(bhlcr) || 829 (qd != NULL && 830 (qd->quirks & PCI_QUIRK_MULTIFUNCTION) != 0)) 831 nfuncs = 8; 832 else 833 nfuncs = 1; 834 835 for (function = 0; function < nfuncs; function++) { 836 tag = pci_make_tag(pc, bus, device, function); 837 id = pci_conf_read(pc, tag, PCI_ID_REG); 838 839 /* Invalid vendor ID value? */ 840 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 841 continue; 842 /* 843 * XXX Not invalid, but we've done this 844 * ~forever. 845 */ 846 if (PCI_VENDOR(id) == 0) 847 continue; 848 (*func)(pc, tag, context); 849 } 850 } 851 } 852 } 853 854 void 855 pci_bridge_foreach(pci_chipset_tag_t pc, int minbus, int maxbus, 856 void (*func)(pci_chipset_tag_t, pcitag_t, void *), void *ctx) 857 { 858 struct pci_bridge_hook_arg bridge_hook; 859 860 bridge_hook.func = func; 861 bridge_hook.arg = ctx; 862 863 pci_device_foreach_min(pc, minbus, maxbus, pci_bridge_hook, 864 &bridge_hook); 865 } 866 867 static void 868 pci_bridge_hook(pci_chipset_tag_t pc, pcitag_t tag, void *ctx) 869 { 870 struct pci_bridge_hook_arg *bridge_hook = (void *)ctx; 871 pcireg_t reg; 872 873 reg = pci_conf_read(pc, tag, PCI_CLASS_REG); 874 if (PCI_CLASS(reg) == PCI_CLASS_BRIDGE && 875 (PCI_SUBCLASS(reg) == PCI_SUBCLASS_BRIDGE_PCI || 876 PCI_SUBCLASS(reg) == PCI_SUBCLASS_BRIDGE_CARDBUS)) { 877 (*bridge_hook->func)(pc, tag, bridge_hook->arg); 878 } 879 } 880 881 static const void * 882 bit_to_function_pointer(const struct pci_overrides *ov, uint64_t bit) 883 { 884 switch (bit) { 885 case PCI_OVERRIDE_CONF_READ: 886 return ov->ov_conf_read; 887 case PCI_OVERRIDE_CONF_WRITE: 888 return ov->ov_conf_write; 889 case PCI_OVERRIDE_INTR_MAP: 890 return ov->ov_intr_map; 891 case PCI_OVERRIDE_INTR_STRING: 892 return ov->ov_intr_string; 893 case PCI_OVERRIDE_INTR_EVCNT: 894 return ov->ov_intr_evcnt; 895 case PCI_OVERRIDE_INTR_ESTABLISH: 896 return ov->ov_intr_establish; 897 case PCI_OVERRIDE_INTR_DISESTABLISH: 898 return ov->ov_intr_disestablish; 899 case PCI_OVERRIDE_MAKE_TAG: 900 return ov->ov_make_tag; 901 case PCI_OVERRIDE_DECOMPOSE_TAG: 902 return ov->ov_decompose_tag; 903 default: 904 return NULL; 905 } 906 } 907 908 void 909 pci_chipset_tag_destroy(pci_chipset_tag_t pc) 910 { 911 kmem_free(pc, sizeof(struct pci_chipset_tag)); 912 } 913 914 int 915 pci_chipset_tag_create(pci_chipset_tag_t opc, const uint64_t present, 916 const struct pci_overrides *ov, void *ctx, pci_chipset_tag_t *pcp) 917 { 918 uint64_t bit, bits, nbits; 919 pci_chipset_tag_t pc; 920 const void *fp; 921 922 if (ov == NULL || present == 0) 923 return EINVAL; 924 925 pc = kmem_alloc(sizeof(struct pci_chipset_tag), KM_SLEEP); 926 927 if (pc == NULL) 928 return ENOMEM; 929 930 pc->pc_super = opc; 931 932 for (bits = present; bits != 0; bits = nbits) { 933 nbits = bits & (bits - 1); 934 bit = nbits ^ bits; 935 if ((fp = bit_to_function_pointer(ov, bit)) == NULL) { 936 #ifdef DEBUG 937 printf("%s: missing bit %" PRIx64 "\n", __func__, bit); 938 #endif 939 goto einval; 940 } 941 } 942 943 pc->pc_ov = ov; 944 pc->pc_present = present; 945 pc->pc_ctx = ctx; 946 947 *pcp = pc; 948 949 return 0; 950 einval: 951 kmem_free(pc, sizeof(struct pci_chipset_tag)); 952 return EINVAL; 953 } 954 955 static void 956 x86_genfb_set_mapreg(void *opaque, int index, int r, int g, int b) 957 { 958 outb(IO_VGA + VGA_DAC_ADDRW, index); 959 outb(IO_VGA + VGA_DAC_PALETTE, (uint8_t)r >> 2); 960 outb(IO_VGA + VGA_DAC_PALETTE, (uint8_t)g >> 2); 961 outb(IO_VGA + VGA_DAC_PALETTE, (uint8_t)b >> 2); 962 } 963 964 static bool 965 x86_genfb_setmode(struct genfb_softc *sc, int newmode) 966 { 967 #if NGENFB > 0 968 # if NACPICA > 0 && defined(VGA_POST) 969 static int curmode = WSDISPLAYIO_MODE_EMUL; 970 # endif 971 972 switch (newmode) { 973 case WSDISPLAYIO_MODE_EMUL: 974 x86_genfb_mtrr_init(sc->sc_fboffset, 975 sc->sc_height * sc->sc_stride); 976 # if NACPICA > 0 && defined(VGA_POST) 977 if (curmode != newmode) { 978 if (vga_posth != NULL && acpi_md_vesa_modenum != 0) { 979 vga_post_set_vbe(vga_posth, 980 acpi_md_vesa_modenum); 981 } 982 } 983 # endif 984 break; 985 } 986 987 # if NACPICA > 0 && defined(VGA_POST) 988 curmode = newmode; 989 # endif 990 #endif 991 return true; 992 } 993 994 static bool 995 x86_genfb_suspend(device_t dev, const pmf_qual_t *qual) 996 { 997 return true; 998 } 999 1000 static bool 1001 x86_genfb_resume(device_t dev, const pmf_qual_t *qual) 1002 { 1003 #if NGENFB > 0 1004 struct pci_genfb_softc *psc = device_private(dev); 1005 1006 #if NACPICA > 0 && defined(VGA_POST) 1007 if (vga_posth != NULL && acpi_md_vbios_reset == 2) { 1008 vga_post_call(vga_posth); 1009 if (acpi_md_vesa_modenum != 0) 1010 vga_post_set_vbe(vga_posth, acpi_md_vesa_modenum); 1011 } 1012 #endif 1013 genfb_restore_palette(&psc->sc_gen); 1014 #endif 1015 1016 return true; 1017 } 1018 1019 device_t 1020 device_pci_register(device_t dev, void *aux) 1021 { 1022 static bool found_console = false; 1023 1024 device_pci_props_register(dev, aux); 1025 1026 /* 1027 * Handle network interfaces here, the attachment information is 1028 * not available driver-independently later. 1029 * 1030 * For disks, there is nothing useful available at attach time. 1031 */ 1032 if (device_class(dev) == DV_IFNET) { 1033 struct btinfo_netif *bin = lookup_bootinfo(BTINFO_NETIF); 1034 if (bin == NULL) 1035 return NULL; 1036 1037 /* 1038 * We don't check the driver name against the device name 1039 * passed by the boot ROM. The ROM should stay usable if 1040 * the driver becomes obsolete. The physical attachment 1041 * information (checked below) must be sufficient to 1042 * identify the device. 1043 */ 1044 if (bin->bus == BI_BUS_PCI && 1045 device_is_a(device_parent(dev), "pci")) { 1046 struct pci_attach_args *paa = aux; 1047 int b, d, f; 1048 1049 /* 1050 * Calculate BIOS representation of: 1051 * 1052 * <bus,device,function> 1053 * 1054 * and compare. 1055 */ 1056 pci_decompose_tag(paa->pa_pc, paa->pa_tag, &b, &d, &f); 1057 if (bin->addr.tag == ((b << 8) | (d << 3) | f)) 1058 return dev; 1059 } 1060 } 1061 if (device_parent(dev) && device_is_a(device_parent(dev), "pci") && 1062 found_console == false) { 1063 struct btinfo_framebuffer *fbinfo; 1064 struct pci_attach_args *pa = aux; 1065 prop_dictionary_t dict; 1066 1067 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_DISPLAY) { 1068 #if NWSDISPLAY > 0 && NGENFB > 0 1069 extern struct vcons_screen x86_genfb_console_screen; 1070 struct rasops_info *ri; 1071 1072 ri = &x86_genfb_console_screen.scr_ri; 1073 #endif 1074 1075 fbinfo = lookup_bootinfo(BTINFO_FRAMEBUFFER); 1076 dict = device_properties(dev); 1077 /* 1078 * framebuffer drivers other than genfb can work 1079 * without the address property 1080 */ 1081 if (fbinfo != NULL) { 1082 if (fbinfo->physaddr != 0) { 1083 prop_dictionary_set_uint32(dict, "width", 1084 fbinfo->width); 1085 prop_dictionary_set_uint32(dict, "height", 1086 fbinfo->height); 1087 prop_dictionary_set_uint8(dict, "depth", 1088 fbinfo->depth); 1089 prop_dictionary_set_uint16(dict, "linebytes", 1090 fbinfo->stride); 1091 1092 prop_dictionary_set_uint64(dict, "address", 1093 fbinfo->physaddr); 1094 #if NWSDISPLAY > 0 && NGENFB > 0 1095 if (ri->ri_bits != NULL) { 1096 prop_dictionary_set_uint64(dict, 1097 "virtual_address", 1098 (vaddr_t)ri->ri_origbits); 1099 } 1100 #endif 1101 } 1102 #if notyet 1103 prop_dictionary_set_bool(dict, "splash", 1104 fbinfo->flags & BI_FB_SPLASH ? 1105 true : false); 1106 #endif 1107 if (fbinfo->depth == 8) { 1108 gfb_cb.gcc_cookie = NULL; 1109 gfb_cb.gcc_set_mapreg = 1110 x86_genfb_set_mapreg; 1111 prop_dictionary_set_uint64(dict, 1112 "cmap_callback", 1113 (uint64_t)(uintptr_t)&gfb_cb); 1114 } 1115 if (fbinfo->physaddr != 0) { 1116 mode_cb.gmc_setmode = x86_genfb_setmode; 1117 prop_dictionary_set_uint64(dict, 1118 "mode_callback", 1119 (uint64_t)(uintptr_t)&mode_cb); 1120 } 1121 1122 #if NWSDISPLAY > 0 && NGENFB > 0 1123 if (device_is_a(dev, "genfb")) { 1124 x86_genfb_set_console_dev(dev); 1125 #ifdef DDB 1126 db_trap_callback = 1127 x86_genfb_ddb_trap_callback; 1128 #endif 1129 } 1130 #endif 1131 } 1132 #if 1 && NWSDISPLAY > 0 && NGENFB > 0 1133 /* XXX */ 1134 if (device_is_a(dev, "genfb")) { 1135 prop_dictionary_set_bool(dict, "is_console", 1136 genfb_is_console()); 1137 } else 1138 #endif 1139 prop_dictionary_set_bool(dict, "is_console", true); 1140 1141 prop_dictionary_set_bool(dict, "clear-screen", false); 1142 #if NWSDISPLAY > 0 && NGENFB > 0 1143 prop_dictionary_set_uint16(dict, "cursor-row", 1144 x86_genfb_console_screen.scr_ri.ri_crow); 1145 #endif 1146 #if notyet 1147 prop_dictionary_set_bool(dict, "splash", 1148 fbinfo->flags & BI_FB_SPLASH ? true : false); 1149 #endif 1150 pmf_cb.gpc_suspend = x86_genfb_suspend; 1151 pmf_cb.gpc_resume = x86_genfb_resume; 1152 prop_dictionary_set_uint64(dict, 1153 "pmf_callback", (uint64_t)(uintptr_t)&pmf_cb); 1154 #ifdef VGA_POST 1155 vga_posth = vga_post_init(pa->pa_bus, pa->pa_device, 1156 pa->pa_function); 1157 #endif 1158 found_console = true; 1159 return NULL; 1160 } 1161 } 1162 return NULL; 1163 } 1164 1165 #ifndef PUC_CNBUS 1166 #define PUC_CNBUS 0 1167 #endif 1168 1169 #if NCOM > 0 1170 int 1171 cpu_puc_cnprobe(struct consdev *cn, struct pci_attach_args *pa) 1172 { 1173 pci_mode_detect(); 1174 pa->pa_iot = x86_bus_space_io; 1175 pa->pa_memt = x86_bus_space_mem; 1176 pa->pa_pc = 0; 1177 pa->pa_tag = pci_make_tag(0, PUC_CNBUS, pci_bus_maxdevs(NULL, 0) - 1, 1178 0); 1179 1180 return 0; 1181 } 1182 #endif 1183