1 /* $NetBSD: pci_machdep.c,v 1.94 2023/08/07 06:23:39 msaitoh Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved. 35 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 1. Redistributions of source code must retain the above copyright 41 * notice, this list of conditions and the following disclaimer. 42 * 2. Redistributions in binary form must reproduce the above copyright 43 * notice, this list of conditions and the following disclaimer in the 44 * documentation and/or other materials provided with the distribution. 45 * 3. All advertising materials mentioning features or use of this software 46 * must display the following acknowledgement: 47 * This product includes software developed by Charles M. Hannum. 48 * 4. The name of the author may not be used to endorse or promote products 49 * derived from this software without specific prior written permission. 50 * 51 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 52 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 53 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 54 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 55 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 56 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 57 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 58 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 59 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 60 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 61 */ 62 63 /* 64 * Machine-specific functions for PCI autoconfiguration. 65 * 66 * On PCs, there are two methods of generating PCI configuration cycles. 67 * We try to detect the appropriate mechanism for this machine and set 68 * up a few function pointers to access the correct method directly. 69 * 70 * The configuration method can be hard-coded in the config file by 71 * using `options PCI_CONF_MODE=N', where `N' is the configuration mode 72 * as defined in section 3.6.4.1, `Generating Configuration Cycles'. 73 */ 74 75 #include <sys/cdefs.h> 76 __KERNEL_RCSID(0, "$NetBSD: pci_machdep.c,v 1.94 2023/08/07 06:23:39 msaitoh Exp $"); 77 78 #include <sys/types.h> 79 #include <sys/param.h> 80 #include <sys/time.h> 81 #include <sys/systm.h> 82 #include <sys/errno.h> 83 #include <sys/device.h> 84 #include <sys/bus.h> 85 #include <sys/cpu.h> 86 #include <sys/kmem.h> 87 88 #include <uvm/uvm_extern.h> 89 90 #include <machine/bus_private.h> 91 92 #include <machine/pio.h> 93 #include <machine/lock.h> 94 95 #include <dev/isa/isareg.h> 96 #include <dev/isa/isavar.h> 97 #include <dev/pci/pcivar.h> 98 #include <dev/pci/pcireg.h> 99 #include <dev/pci/pccbbreg.h> 100 #include <dev/pci/pcidevs.h> 101 #include <dev/pci/ppbvar.h> 102 #include <dev/pci/genfb_pcivar.h> 103 104 #include <dev/wsfb/genfbvar.h> 105 #include <arch/x86/include/genfb_machdep.h> 106 #include <dev/ic/vgareg.h> 107 108 #include "acpica.h" 109 #include "genfb.h" 110 #include "isa.h" 111 #include "opt_acpi.h" 112 #include "opt_ddb.h" 113 #include "opt_mpbios.h" 114 #include "opt_puc.h" 115 #include "opt_vga.h" 116 #include "pci.h" 117 #include "wsdisplay.h" 118 #include "com.h" 119 120 #ifdef DDB 121 #include <machine/db_machdep.h> 122 #include <ddb/db_sym.h> 123 #include <ddb/db_extern.h> 124 #endif 125 126 #ifdef VGA_POST 127 #include <x86/vga_post.h> 128 #endif 129 130 #include <x86/cpuvar.h> 131 132 #include <machine/autoconf.h> 133 #include <machine/bootinfo.h> 134 135 #ifdef MPBIOS 136 #include <machine/mpbiosvar.h> 137 #endif 138 139 #if NACPICA > 0 140 #include <machine/mpacpi.h> 141 #if !defined(NO_PCI_EXTENDED_CONFIG) 142 #include <dev/acpi/acpivar.h> 143 #include <dev/acpi/acpi_mcfg.h> 144 #endif 145 #endif 146 147 #include <machine/mpconfig.h> 148 149 #if NCOM > 0 150 #include <dev/pci/puccn.h> 151 #endif 152 153 #ifndef XENPV 154 #include <x86/efi.h> 155 #endif 156 157 #include "opt_pci_conf_mode.h" 158 159 #ifdef PCI_CONF_MODE 160 #if (PCI_CONF_MODE == 1) || (PCI_CONF_MODE == 2) 161 static int pci_mode = PCI_CONF_MODE; 162 #else 163 #error Invalid PCI configuration mode. 164 #endif 165 #else 166 static int pci_mode = -1; 167 #endif 168 169 struct pci_conf_lock { 170 uint32_t cl_cpuno; /* 0: unlocked 171 * 1 + n: locked by CPU n (0 <= n) 172 */ 173 uint32_t cl_sel; /* the address that's being read. */ 174 }; 175 176 static void pci_conf_unlock(struct pci_conf_lock *); 177 static uint32_t pci_conf_selector(pcitag_t, int); 178 static unsigned int pci_conf_port(pcitag_t, int); 179 static void pci_conf_select(uint32_t); 180 static void pci_conf_lock(struct pci_conf_lock *, uint32_t); 181 static void pci_bridge_hook(pci_chipset_tag_t, pcitag_t, void *); 182 struct pci_bridge_hook_arg { 183 void (*func)(pci_chipset_tag_t, pcitag_t, void *); 184 void *arg; 185 }; 186 187 #define PCI_MODE1_ENABLE 0x80000000UL 188 #define PCI_MODE1_ADDRESS_REG 0x0cf8 189 #define PCI_MODE1_DATA_REG 0x0cfc 190 191 #define PCI_MODE2_ENABLE_REG 0x0cf8 192 #define PCI_MODE2_FORWARD_REG 0x0cfa 193 194 #define _tag(b, d, f) \ 195 {.mode1 = PCI_MODE1_ENABLE | ((b) << 16) | ((d) << 11) | ((f) << 8)} 196 #define _qe(bus, dev, fcn, vend, prod) \ 197 {_tag(bus, dev, fcn), PCI_ID_CODE(vend, prod)} 198 const struct { 199 pcitag_t tag; 200 pcireg_t id; 201 } pcim1_quirk_tbl[] = { 202 _qe(0, 0, 0, PCI_VENDOR_INVALID, 0x0000), /* patchable */ 203 _qe(0, 0, 0, PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_TRIFLEX1), 204 /* XXX Triflex2 not tested */ 205 _qe(0, 0, 0, PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_TRIFLEX2), 206 _qe(0, 0, 0, PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_TRIFLEX4), 207 #if 0 208 /* Triton needed for Connectix Virtual PC */ 209 _qe(0, 0, 0, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82437FX), 210 /* Connectix Virtual PC 5 has a 440BX */ 211 _qe(0, 0, 0, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82443BX_NOAGP), 212 /* Parallels Desktop for Mac */ 213 _qe(0, 2, 0, PCI_VENDOR_PARALLELS, PCI_PRODUCT_PARALLELS_VIDEO), 214 _qe(0, 3, 0, PCI_VENDOR_PARALLELS, PCI_PRODUCT_PARALLELS_TOOLS), 215 /* SIS 740 */ 216 _qe(0, 0, 0, PCI_VENDOR_SIS, PCI_PRODUCT_SIS_740), 217 /* SIS 741 */ 218 _qe(0, 0, 0, PCI_VENDOR_SIS, PCI_PRODUCT_SIS_741), 219 /* VIA Technologies VX900 */ 220 _qe(0, 0, 0, PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VX900_HB) 221 #endif 222 }; 223 #undef _tag 224 #undef _qe 225 226 /* arch/xen does not support MSI/MSI-X yet. */ 227 #ifdef __HAVE_PCI_MSI_MSIX 228 #define PCI_QUIRK_DISABLE_MSI 1 /* Neigher MSI nor MSI-X work */ 229 #define PCI_QUIRK_DISABLE_MSIX 2 /* MSI-X does not work */ 230 #define PCI_QUIRK_ENABLE_MSI_VM 3 /* Older chipset in VM where MSI and MSI-X works */ 231 232 #define _dme(vend, prod) \ 233 { PCI_QUIRK_DISABLE_MSI, PCI_ID_CODE(vend, prod) } 234 #define _dmxe(vend, prod) \ 235 { PCI_QUIRK_DISABLE_MSIX, PCI_ID_CODE(vend, prod) } 236 #define _emve(vend, prod) \ 237 { PCI_QUIRK_ENABLE_MSI_VM, PCI_ID_CODE(vend, prod) } 238 const struct { 239 int type; 240 pcireg_t id; 241 } pci_msi_quirk_tbl[] = { 242 _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PCMC), 243 _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82437FX), 244 _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82437MX), 245 _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82437VX), 246 _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82439HX), 247 _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82439TX), 248 _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82443GX), 249 _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82443GX_AGP), 250 _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82440MX), 251 _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82441FX), 252 _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82443BX), 253 _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82443BX_AGP), 254 _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82443BX_NOAGP), 255 _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82443GX_NOAGP), 256 _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82443LX), 257 _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82443LX_AGP), 258 _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82810_MCH), 259 _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82810E_MCH), 260 _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82815_FULL_HUB), 261 _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82820_MCH), 262 _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82830MP_IO_1), 263 _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82840_HB), 264 _dme(PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE_PCHB), 265 _dme(PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_PCHB), 266 _dme(PCI_VENDOR_AMD, PCI_PRODUCT_AMD_SC751_SC), 267 _dme(PCI_VENDOR_AMD, PCI_PRODUCT_AMD_SC761_SC), 268 _dme(PCI_VENDOR_AMD, PCI_PRODUCT_AMD_SC762_NB), 269 270 _emve(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82441FX), /* QEMU */ 271 _emve(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82443BX), /* VMWare */ 272 }; 273 #undef _dme 274 #undef _dmxe 275 #undef _emve 276 #endif /* __HAVE_PCI_MSI_MSIX */ 277 278 /* 279 * PCI doesn't have any special needs; just use the generic versions 280 * of these functions. 281 */ 282 struct x86_bus_dma_tag pci_bus_dma_tag = { 283 ._tag_needs_free = 0, 284 #if defined(_LP64) || defined(PAE) 285 ._bounce_thresh = PCI32_DMA_BOUNCE_THRESHOLD, 286 ._bounce_alloc_lo = ISA_DMA_BOUNCE_THRESHOLD, 287 ._bounce_alloc_hi = PCI32_DMA_BOUNCE_THRESHOLD, 288 #else 289 ._bounce_thresh = 0, 290 ._bounce_alloc_lo = 0, 291 ._bounce_alloc_hi = 0, 292 #endif 293 ._may_bounce = NULL, 294 }; 295 296 #ifdef _LP64 297 struct x86_bus_dma_tag pci_bus_dma64_tag = { 298 ._tag_needs_free = 0, 299 ._bounce_thresh = 0, 300 ._bounce_alloc_lo = 0, 301 ._bounce_alloc_hi = 0, 302 ._may_bounce = NULL, 303 }; 304 #endif 305 306 static struct pci_conf_lock cl0 = { 307 .cl_cpuno = 0UL 308 , .cl_sel = 0UL 309 }; 310 311 static struct pci_conf_lock * const cl = &cl0; 312 313 #if NGENFB > 0 && NACPICA > 0 && defined(VGA_POST) 314 extern int acpi_md_vbios_reset; 315 extern int acpi_md_vesa_modenum; 316 #endif 317 318 static struct genfb_colormap_callback gfb_cb; 319 static struct genfb_pmf_callback pmf_cb; 320 static struct genfb_mode_callback mode_cb; 321 #ifdef VGA_POST 322 static struct vga_post *vga_posth = NULL; 323 #endif 324 325 static void 326 pci_conf_lock(struct pci_conf_lock *ocl, uint32_t sel) 327 { 328 uint32_t cpuno; 329 330 KASSERT(sel != 0); 331 332 kpreempt_disable(); 333 cpuno = cpu_number() + 1; 334 /* If the kernel enters pci_conf_lock() through an interrupt 335 * handler, then the CPU may already hold the lock. 336 * 337 * If the CPU does not already hold the lock, spin until 338 * we can acquire it. 339 */ 340 if (cpuno == cl->cl_cpuno) { 341 ocl->cl_cpuno = cpuno; 342 } else { 343 #ifdef LOCKDEBUG 344 u_int spins = 0; 345 #endif 346 u_int count; 347 count = SPINLOCK_BACKOFF_MIN; 348 349 ocl->cl_cpuno = 0; 350 351 while (atomic_cas_32(&cl->cl_cpuno, 0, cpuno) != 0) { 352 SPINLOCK_BACKOFF(count); 353 #ifdef LOCKDEBUG 354 if (SPINLOCK_SPINOUT(spins)) { 355 panic("%s: cpu %" PRId32 356 " spun out waiting for cpu %" PRId32, 357 __func__, cpuno, cl->cl_cpuno); 358 } 359 #endif 360 } 361 } 362 363 /* Only one CPU can be here, so an interlocked atomic_swap(3) 364 * is not necessary. 365 * 366 * Evaluating atomic_cas_32_ni()'s argument, cl->cl_sel, 367 * and applying atomic_cas_32_ni() is not an atomic operation, 368 * however, any interrupt that, in the middle of the 369 * operation, modifies cl->cl_sel, will also restore 370 * cl->cl_sel. So cl->cl_sel will have the same value when 371 * we apply atomic_cas_32_ni() as when we evaluated it, 372 * before. 373 */ 374 ocl->cl_sel = atomic_cas_32_ni(&cl->cl_sel, cl->cl_sel, sel); 375 pci_conf_select(sel); 376 } 377 378 static void 379 pci_conf_unlock(struct pci_conf_lock *ocl) 380 { 381 atomic_cas_32_ni(&cl->cl_sel, cl->cl_sel, ocl->cl_sel); 382 pci_conf_select(ocl->cl_sel); 383 if (ocl->cl_cpuno != cl->cl_cpuno) 384 atomic_cas_32(&cl->cl_cpuno, cl->cl_cpuno, ocl->cl_cpuno); 385 kpreempt_enable(); 386 } 387 388 static uint32_t 389 pci_conf_selector(pcitag_t tag, int reg) 390 { 391 static const pcitag_t mode2_mask = { 392 .mode2 = { 393 .enable = 0xff 394 , .forward = 0xff 395 } 396 }; 397 398 switch (pci_mode) { 399 case 1: 400 return tag.mode1 | reg; 401 case 2: 402 return tag.mode1 & mode2_mask.mode1; 403 default: 404 panic("%s: mode %d not configured", __func__, pci_mode); 405 } 406 } 407 408 static unsigned int 409 pci_conf_port(pcitag_t tag, int reg) 410 { 411 switch (pci_mode) { 412 case 1: 413 return PCI_MODE1_DATA_REG; 414 case 2: 415 return tag.mode2.port | reg; 416 default: 417 panic("%s: mode %d not configured", __func__, pci_mode); 418 } 419 } 420 421 static void 422 pci_conf_select(uint32_t sel) 423 { 424 pcitag_t tag; 425 426 switch (pci_mode) { 427 case 1: 428 outl(PCI_MODE1_ADDRESS_REG, sel); 429 return; 430 case 2: 431 tag.mode1 = sel; 432 outb(PCI_MODE2_ENABLE_REG, tag.mode2.enable); 433 if (tag.mode2.enable != 0) 434 outb(PCI_MODE2_FORWARD_REG, tag.mode2.forward); 435 return; 436 default: 437 panic("%s: mode %d not configured", __func__, pci_mode); 438 } 439 } 440 441 static int 442 pci_mode_check(void) 443 { 444 pcireg_t x; 445 pcitag_t t; 446 int device; 447 const int maxdev = pci_bus_maxdevs(NULL, 0); 448 449 for (device = 0; device < maxdev; device++) { 450 t = pci_make_tag(NULL, 0, device, 0); 451 x = pci_conf_read(NULL, t, PCI_CLASS_REG); 452 if (PCI_CLASS(x) == PCI_CLASS_BRIDGE && 453 PCI_SUBCLASS(x) == PCI_SUBCLASS_BRIDGE_HOST) 454 return 0; 455 x = pci_conf_read(NULL, t, PCI_ID_REG); 456 switch (PCI_VENDOR(x)) { 457 case PCI_VENDOR_COMPAQ: 458 case PCI_VENDOR_INTEL: 459 case PCI_VENDOR_VIATECH: 460 return 0; 461 } 462 } 463 return -1; 464 } 465 #ifdef __HAVE_PCI_MSI_MSIX 466 static int 467 pci_has_msi_quirk(pcireg_t id, int type) 468 { 469 int i; 470 471 for (i = 0; i < __arraycount(pci_msi_quirk_tbl); i++) { 472 if (id == pci_msi_quirk_tbl[i].id && 473 type == pci_msi_quirk_tbl[i].type) 474 return 1; 475 } 476 477 return 0; 478 } 479 #endif 480 481 void 482 pci_attach_hook(device_t parent, device_t self, struct pcibus_attach_args *pba) 483 { 484 #ifdef __HAVE_PCI_MSI_MSIX 485 pci_chipset_tag_t pc = pba->pba_pc; 486 pcitag_t tag; 487 pcireg_t id, class; 488 int i; 489 bool havehb = false; 490 #endif 491 492 if (pba->pba_bus == 0) 493 aprint_normal(": configuration mode %d", pci_mode); 494 #ifdef MPBIOS 495 mpbios_pci_attach_hook(parent, self, pba); 496 #endif 497 #if NACPICA > 0 498 mpacpi_pci_attach_hook(parent, self, pba); 499 #endif 500 #if NACPICA > 0 && !defined(NO_PCI_EXTENDED_CONFIG) 501 acpimcfg_map_bus(self, pba->pba_pc, pba->pba_bus); 502 #endif 503 504 #ifdef __HAVE_PCI_MSI_MSIX 505 /* 506 * In order to decide whether the system supports MSI we look 507 * at the host bridge, which should be device 0 on bus 0. 508 * It is better to not enable MSI on systems that 509 * support it than the other way around, so be conservative 510 * here. So we don't enable MSI if we don't find a host 511 * bridge there. We also deliberately don't enable MSI on 512 * chipsets from low-end manifacturers like VIA and SiS. 513 */ 514 for (i = 0; i <= 7; i++) { 515 tag = pci_make_tag(pc, 0, 0, i); 516 id = pci_conf_read(pc, tag, PCI_ID_REG); 517 class = pci_conf_read(pc, tag, PCI_CLASS_REG); 518 519 if (PCI_CLASS(class) == PCI_CLASS_BRIDGE && 520 PCI_SUBCLASS(class) == PCI_SUBCLASS_BRIDGE_HOST) { 521 havehb = true; 522 break; 523 } 524 } 525 if (havehb == false) 526 return; 527 528 /* VMware and KVM use old chipset, but they can use MSI/MSI-X */ 529 if ((cpu_feature[1] & CPUID2_RAZ) 530 && (pci_has_msi_quirk(id, PCI_QUIRK_ENABLE_MSI_VM))) { 531 pba->pba_flags |= PCI_FLAGS_MSI_OKAY; 532 pba->pba_flags |= PCI_FLAGS_MSIX_OKAY; 533 } else if (pci_has_msi_quirk(id, PCI_QUIRK_DISABLE_MSI)) { 534 pba->pba_flags &= ~PCI_FLAGS_MSI_OKAY; 535 pba->pba_flags &= ~PCI_FLAGS_MSIX_OKAY; 536 aprint_verbose("\n"); 537 aprint_verbose_dev(self, 538 "This pci host supports neither MSI nor MSI-X."); 539 } else if (pci_has_msi_quirk(id, PCI_QUIRK_DISABLE_MSIX)) { 540 pba->pba_flags |= PCI_FLAGS_MSI_OKAY; 541 pba->pba_flags &= ~PCI_FLAGS_MSIX_OKAY; 542 aprint_verbose("\n"); 543 aprint_verbose_dev(self, 544 "This pci host does not support MSI-X."); 545 #if NACPICA > 0 546 } else if (acpi_active && 547 AcpiGbl_FADT.Header.Revision >= 4 && 548 (AcpiGbl_FADT.BootFlags & ACPI_FADT_NO_MSI) != 0) { 549 pba->pba_flags &= ~PCI_FLAGS_MSI_OKAY; 550 pba->pba_flags &= ~PCI_FLAGS_MSIX_OKAY; 551 aprint_verbose("\n"); 552 aprint_verbose_dev(self, 553 "MSI support disabled via ACPI IAPC_BOOT_ARCH flag.\n"); 554 #endif 555 } else { 556 pba->pba_flags |= PCI_FLAGS_MSI_OKAY; 557 pba->pba_flags |= PCI_FLAGS_MSIX_OKAY; 558 } 559 560 /* 561 * Don't enable MSI on a HyperTransport bus. In order to 562 * determine that bus 0 is a HyperTransport bus, we look at 563 * device 24 function 0, which is the HyperTransport 564 * host/primary interface integrated on most 64-bit AMD CPUs. 565 * If that device has a HyperTransport capability, bus 0 must 566 * be a HyperTransport bus and we disable MSI. 567 */ 568 if (24 < pci_bus_maxdevs(pc, 0)) { 569 tag = pci_make_tag(pc, 0, 24, 0); 570 if (pci_get_capability(pc, tag, PCI_CAP_LDT, NULL, NULL)) { 571 pba->pba_flags &= ~PCI_FLAGS_MSI_OKAY; 572 pba->pba_flags &= ~PCI_FLAGS_MSIX_OKAY; 573 } 574 } 575 576 #endif /* __HAVE_PCI_MSI_MSIX */ 577 } 578 579 int 580 pci_bus_maxdevs(pci_chipset_tag_t pc, int busno) 581 { 582 /* 583 * Bus number is irrelevant. If Configuration Mechanism 2 is in 584 * use, can only have devices 0-15 on any bus. If Configuration 585 * Mechanism 1 is in use, can have devices 0-32 (i.e. the `normal' 586 * range). 587 */ 588 if (pci_mode == 2) 589 return (16); 590 else 591 return (32); 592 } 593 594 pcitag_t 595 pci_make_tag(pci_chipset_tag_t pc, int bus, int device, int function) 596 { 597 pci_chipset_tag_t ipc; 598 pcitag_t tag; 599 600 for (ipc = pc; ipc != NULL; ipc = ipc->pc_super) { 601 if ((ipc->pc_present & PCI_OVERRIDE_MAKE_TAG) == 0) 602 continue; 603 return (*ipc->pc_ov->ov_make_tag)(ipc->pc_ctx, 604 pc, bus, device, function); 605 } 606 607 switch (pci_mode) { 608 case 1: 609 if (bus >= 256 || device >= 32 || function >= 8) 610 panic("%s: bad request(%d, %d, %d)", __func__, 611 bus, device, function); 612 613 tag.mode1 = PCI_MODE1_ENABLE | 614 (bus << 16) | (device << 11) | (function << 8); 615 return tag; 616 case 2: 617 if (bus >= 256 || device >= 16 || function >= 8) 618 panic("%s: bad request(%d, %d, %d)", __func__, 619 bus, device, function); 620 621 tag.mode2.port = 0xc000 | (device << 8); 622 tag.mode2.enable = 0xf0 | (function << 1); 623 tag.mode2.forward = bus; 624 return tag; 625 default: 626 panic("%s: mode %d not configured", __func__, pci_mode); 627 } 628 } 629 630 void 631 pci_decompose_tag(pci_chipset_tag_t pc, pcitag_t tag, 632 int *bp, int *dp, int *fp) 633 { 634 pci_chipset_tag_t ipc; 635 636 for (ipc = pc; ipc != NULL; ipc = ipc->pc_super) { 637 if ((ipc->pc_present & PCI_OVERRIDE_DECOMPOSE_TAG) == 0) 638 continue; 639 (*ipc->pc_ov->ov_decompose_tag)(ipc->pc_ctx, 640 pc, tag, bp, dp, fp); 641 return; 642 } 643 644 switch (pci_mode) { 645 case 1: 646 if (bp != NULL) 647 *bp = (tag.mode1 >> 16) & 0xff; 648 if (dp != NULL) 649 *dp = (tag.mode1 >> 11) & 0x1f; 650 if (fp != NULL) 651 *fp = (tag.mode1 >> 8) & 0x7; 652 return; 653 case 2: 654 if (bp != NULL) 655 *bp = tag.mode2.forward & 0xff; 656 if (dp != NULL) 657 *dp = (tag.mode2.port >> 8) & 0xf; 658 if (fp != NULL) 659 *fp = (tag.mode2.enable >> 1) & 0x7; 660 return; 661 default: 662 panic("%s: mode %d not configured", __func__, pci_mode); 663 } 664 } 665 666 pcireg_t 667 pci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg) 668 { 669 pci_chipset_tag_t ipc; 670 pcireg_t data; 671 struct pci_conf_lock ocl; 672 int dev; 673 674 KASSERT((reg & 0x3) == 0); 675 676 for (ipc = pc; ipc != NULL; ipc = ipc->pc_super) { 677 if ((ipc->pc_present & PCI_OVERRIDE_CONF_READ) == 0) 678 continue; 679 return (*ipc->pc_ov->ov_conf_read)(ipc->pc_ctx, pc, tag, reg); 680 } 681 682 pci_decompose_tag(pc, tag, NULL, &dev, NULL); 683 if (__predict_false(pci_mode == 2 && dev >= 16)) 684 return (pcireg_t) -1; 685 686 if (reg < 0) 687 return (pcireg_t) -1; 688 if (reg >= PCI_CONF_SIZE) { 689 #if NACPICA > 0 && !defined(NO_PCI_EXTENDED_CONFIG) 690 if (reg >= PCI_EXTCONF_SIZE) 691 return (pcireg_t) -1; 692 acpimcfg_conf_read(pc, tag, reg, &data); 693 return data; 694 #else 695 return (pcireg_t) -1; 696 #endif 697 } 698 699 pci_conf_lock(&ocl, pci_conf_selector(tag, reg)); 700 data = inl(pci_conf_port(tag, reg)); 701 pci_conf_unlock(&ocl); 702 return data; 703 } 704 705 void 706 pci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data) 707 { 708 pci_chipset_tag_t ipc; 709 struct pci_conf_lock ocl; 710 int dev; 711 712 KASSERT((reg & 0x3) == 0); 713 714 for (ipc = pc; ipc != NULL; ipc = ipc->pc_super) { 715 if ((ipc->pc_present & PCI_OVERRIDE_CONF_WRITE) == 0) 716 continue; 717 (*ipc->pc_ov->ov_conf_write)(ipc->pc_ctx, pc, tag, reg, 718 data); 719 return; 720 } 721 722 pci_decompose_tag(pc, tag, NULL, &dev, NULL); 723 if (__predict_false(pci_mode == 2 && dev >= 16)) { 724 return; 725 } 726 727 if (reg < 0) 728 return; 729 if (reg >= PCI_CONF_SIZE) { 730 #if NACPICA > 0 && !defined(NO_PCI_EXTENDED_CONFIG) 731 if (reg >= PCI_EXTCONF_SIZE) 732 return; 733 acpimcfg_conf_write(pc, tag, reg, data); 734 #endif 735 return; 736 } 737 738 pci_conf_lock(&ocl, pci_conf_selector(tag, reg)); 739 outl(pci_conf_port(tag, reg), data); 740 pci_conf_unlock(&ocl); 741 } 742 743 #ifdef XENPV 744 void 745 pci_conf_write16(pci_chipset_tag_t pc, pcitag_t tag, int reg, uint16_t data) 746 { 747 pci_chipset_tag_t ipc; 748 struct pci_conf_lock ocl; 749 int dev; 750 751 KASSERT((reg & 0x1) == 0); 752 753 for (ipc = pc; ipc != NULL; ipc = ipc->pc_super) { 754 if ((ipc->pc_present & PCI_OVERRIDE_CONF_WRITE) == 0) 755 continue; 756 panic("pci_conf_write16 and override"); 757 } 758 759 pci_decompose_tag(pc, tag, NULL, &dev, NULL); 760 if (__predict_false(pci_mode == 2 && dev >= 16)) { 761 return; 762 } 763 764 if (reg < 0) 765 return; 766 if (reg >= PCI_CONF_SIZE) { 767 #if NACPICA > 0 && !defined(NO_PCI_EXTENDED_CONFIG) 768 if (reg >= PCI_EXTCONF_SIZE) 769 return; 770 panic("pci_conf_write16 and reg >= PCI_CONF_SIZE"); 771 #endif 772 return; 773 } 774 775 pci_conf_lock(&ocl, pci_conf_selector(tag, reg & ~0x3)); 776 outl(pci_conf_port(tag, reg & ~0x3) + (reg & 0x3), data); 777 pci_conf_unlock(&ocl); 778 } 779 #endif /* XENPV */ 780 781 void 782 pci_mode_set(int mode) 783 { 784 KASSERT(pci_mode == -1 || pci_mode == mode); 785 786 pci_mode = mode; 787 } 788 789 int 790 pci_mode_detect(void) 791 { 792 uint32_t sav, val; 793 int i; 794 pcireg_t idreg; 795 796 if (pci_mode != -1) 797 return pci_mode; 798 799 /* 800 * We try to divine which configuration mode the host bridge wants. 801 */ 802 803 sav = inl(PCI_MODE1_ADDRESS_REG); 804 805 pci_mode = 1; /* assume this for now */ 806 /* 807 * catch some known buggy implementations of mode 1 808 */ 809 for (i = 0; i < __arraycount(pcim1_quirk_tbl); i++) { 810 pcitag_t t; 811 812 if (PCI_VENDOR(pcim1_quirk_tbl[i].id) == PCI_VENDOR_INVALID) 813 continue; 814 t.mode1 = pcim1_quirk_tbl[i].tag.mode1; 815 idreg = pci_conf_read(NULL, t, PCI_ID_REG); /* needs "pci_mode" */ 816 if (idreg == pcim1_quirk_tbl[i].id) { 817 #ifdef DEBUG 818 printf("%s: known mode 1 PCI chipset (%08x)\n", 819 __func__, idreg); 820 #endif 821 return (pci_mode); 822 } 823 } 824 825 #if 0 826 extern char cpu_brand_string[]; 827 const char *reason, *system_vendor, *system_product; 828 if (memcmp(cpu_brand_string, "QEMU", 4) == 0) 829 /* PR 45671, https://bugs.launchpad.net/qemu/+bug/897771 */ 830 reason = "QEMU"; 831 else if ((system_vendor = pmf_get_platform("system-vendor")) != NULL && 832 strcmp(system_vendor, "Xen") == 0 && 833 (system_product = pmf_get_platform("system-product")) != NULL && 834 strcmp(system_product, "HVM domU") == 0) 835 reason = "Xen"; 836 else 837 reason = NULL; 838 839 if (reason) { 840 #ifdef DEBUG 841 printf("%s: forcing PCI mode 1 for %s\n", __func__, reason); 842 #endif 843 return (pci_mode); 844 } 845 #endif 846 /* 847 * Strong check for standard compliant mode 1: 848 * 1. bit 31 ("enable") can be set 849 * 2. byte/word access does not affect register 850 */ 851 outl(PCI_MODE1_ADDRESS_REG, PCI_MODE1_ENABLE); 852 outb(PCI_MODE1_ADDRESS_REG + 3, 0); 853 outw(PCI_MODE1_ADDRESS_REG + 2, 0); 854 val = inl(PCI_MODE1_ADDRESS_REG); 855 if ((val & 0x80fffffc) != PCI_MODE1_ENABLE) { 856 #ifdef DEBUG 857 printf("%s: mode 1 enable failed (%x)\n", __func__, val); 858 #endif 859 /* Try out mode 1 to see if we can find a host bridge. */ 860 if (pci_mode_check() == 0) { 861 #ifdef DEBUG 862 printf("%s: mode 1 functional, using\n", __func__); 863 #endif 864 return (pci_mode); 865 } 866 goto not1; 867 } 868 outl(PCI_MODE1_ADDRESS_REG, 0); 869 val = inl(PCI_MODE1_ADDRESS_REG); 870 if ((val & 0x80fffffc) != 0) 871 goto not1; 872 return (pci_mode); 873 not1: 874 outl(PCI_MODE1_ADDRESS_REG, sav); 875 876 /* 877 * This mode 2 check is quite weak (and known to give false 878 * positives on some Compaq machines). 879 * However, this doesn't matter, because this is the 880 * last test, and simply no PCI devices will be found if 881 * this happens. 882 */ 883 outb(PCI_MODE2_ENABLE_REG, 0); 884 outb(PCI_MODE2_FORWARD_REG, 0); 885 if (inb(PCI_MODE2_ENABLE_REG) != 0 || 886 inb(PCI_MODE2_FORWARD_REG) != 0) 887 goto not2; 888 return (pci_mode = 2); 889 not2: 890 891 return (pci_mode = 0); 892 } 893 894 void 895 pci_device_foreach(pci_chipset_tag_t pc, int maxbus, 896 void (*func)(pci_chipset_tag_t, pcitag_t, void *), void *context) 897 { 898 pci_device_foreach_min(pc, 0, maxbus, func, context); 899 } 900 901 void 902 pci_device_foreach_min(pci_chipset_tag_t pc, int minbus, int maxbus, 903 void (*func)(pci_chipset_tag_t, pcitag_t, void *), void *context) 904 { 905 const struct pci_quirkdata *qd; 906 int bus, device, function, maxdevs, nfuncs; 907 pcireg_t id, bhlcr; 908 pcitag_t tag; 909 910 for (bus = minbus; bus <= maxbus; bus++) { 911 maxdevs = pci_bus_maxdevs(pc, bus); 912 for (device = 0; device < maxdevs; device++) { 913 tag = pci_make_tag(pc, bus, device, 0); 914 id = pci_conf_read(pc, tag, PCI_ID_REG); 915 916 /* Invalid vendor ID value? */ 917 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 918 continue; 919 /* XXX Not invalid, but we've done this ~forever. */ 920 if (PCI_VENDOR(id) == 0) 921 continue; 922 923 qd = pci_lookup_quirkdata(PCI_VENDOR(id), 924 PCI_PRODUCT(id)); 925 926 bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 927 if (PCI_HDRTYPE_MULTIFN(bhlcr) || 928 (qd != NULL && 929 (qd->quirks & PCI_QUIRK_MULTIFUNCTION) != 0)) 930 nfuncs = 8; 931 else 932 nfuncs = 1; 933 934 for (function = 0; function < nfuncs; function++) { 935 tag = pci_make_tag(pc, bus, device, function); 936 id = pci_conf_read(pc, tag, PCI_ID_REG); 937 938 /* Invalid vendor ID value? */ 939 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 940 continue; 941 /* 942 * XXX Not invalid, but we've done this 943 * ~forever. 944 */ 945 if (PCI_VENDOR(id) == 0) 946 continue; 947 (*func)(pc, tag, context); 948 } 949 } 950 } 951 } 952 953 void 954 pci_bridge_foreach(pci_chipset_tag_t pc, int minbus, int maxbus, 955 void (*func)(pci_chipset_tag_t, pcitag_t, void *), void *ctx) 956 { 957 struct pci_bridge_hook_arg bridge_hook; 958 959 bridge_hook.func = func; 960 bridge_hook.arg = ctx; 961 962 pci_device_foreach_min(pc, minbus, maxbus, pci_bridge_hook, 963 &bridge_hook); 964 } 965 966 static void 967 pci_bridge_hook(pci_chipset_tag_t pc, pcitag_t tag, void *ctx) 968 { 969 struct pci_bridge_hook_arg *bridge_hook = (void *)ctx; 970 pcireg_t reg; 971 972 reg = pci_conf_read(pc, tag, PCI_CLASS_REG); 973 if (PCI_CLASS(reg) == PCI_CLASS_BRIDGE && 974 (PCI_SUBCLASS(reg) == PCI_SUBCLASS_BRIDGE_PCI || 975 PCI_SUBCLASS(reg) == PCI_SUBCLASS_BRIDGE_CARDBUS)) { 976 (*bridge_hook->func)(pc, tag, bridge_hook->arg); 977 } 978 } 979 980 static const void * 981 bit_to_function_pointer(const struct pci_overrides *ov, uint64_t bit) 982 { 983 switch (bit) { 984 case PCI_OVERRIDE_CONF_READ: 985 return ov->ov_conf_read; 986 case PCI_OVERRIDE_CONF_WRITE: 987 return ov->ov_conf_write; 988 case PCI_OVERRIDE_INTR_MAP: 989 return ov->ov_intr_map; 990 case PCI_OVERRIDE_INTR_STRING: 991 return ov->ov_intr_string; 992 case PCI_OVERRIDE_INTR_EVCNT: 993 return ov->ov_intr_evcnt; 994 case PCI_OVERRIDE_INTR_ESTABLISH: 995 return ov->ov_intr_establish; 996 case PCI_OVERRIDE_INTR_DISESTABLISH: 997 return ov->ov_intr_disestablish; 998 case PCI_OVERRIDE_MAKE_TAG: 999 return ov->ov_make_tag; 1000 case PCI_OVERRIDE_DECOMPOSE_TAG: 1001 return ov->ov_decompose_tag; 1002 default: 1003 return NULL; 1004 } 1005 } 1006 1007 void 1008 pci_chipset_tag_destroy(pci_chipset_tag_t pc) 1009 { 1010 kmem_free(pc, sizeof(struct pci_chipset_tag)); 1011 } 1012 1013 int 1014 pci_chipset_tag_create(pci_chipset_tag_t opc, const uint64_t present, 1015 const struct pci_overrides *ov, void *ctx, pci_chipset_tag_t *pcp) 1016 { 1017 uint64_t bit, bits, nbits; 1018 pci_chipset_tag_t pc; 1019 const void *fp; 1020 1021 if (ov == NULL || present == 0) 1022 return EINVAL; 1023 1024 pc = kmem_alloc(sizeof(struct pci_chipset_tag), KM_SLEEP); 1025 pc->pc_super = opc; 1026 1027 for (bits = present; bits != 0; bits = nbits) { 1028 nbits = bits & (bits - 1); 1029 bit = nbits ^ bits; 1030 if ((fp = bit_to_function_pointer(ov, bit)) == NULL) { 1031 #ifdef DEBUG 1032 printf("%s: missing bit %" PRIx64 "\n", __func__, bit); 1033 #endif 1034 goto einval; 1035 } 1036 } 1037 1038 pc->pc_ov = ov; 1039 pc->pc_present = present; 1040 pc->pc_ctx = ctx; 1041 1042 *pcp = pc; 1043 1044 return 0; 1045 einval: 1046 kmem_free(pc, sizeof(struct pci_chipset_tag)); 1047 return EINVAL; 1048 } 1049 1050 static void 1051 x86_genfb_set_mapreg(void *opaque, int index, int r, int g, int b) 1052 { 1053 outb(IO_VGA + VGA_DAC_ADDRW, index); 1054 outb(IO_VGA + VGA_DAC_PALETTE, (uint8_t)r >> 2); 1055 outb(IO_VGA + VGA_DAC_PALETTE, (uint8_t)g >> 2); 1056 outb(IO_VGA + VGA_DAC_PALETTE, (uint8_t)b >> 2); 1057 } 1058 1059 static bool 1060 x86_genfb_setmode(struct genfb_softc *sc, int newmode) 1061 { 1062 #if NGENFB > 0 1063 # if NACPICA > 0 && defined(VGA_POST) 1064 static int curmode = WSDISPLAYIO_MODE_EMUL; 1065 # endif 1066 1067 switch (newmode) { 1068 case WSDISPLAYIO_MODE_EMUL: 1069 # if NACPICA > 0 && defined(VGA_POST) 1070 if (curmode != newmode) { 1071 if (vga_posth != NULL && acpi_md_vesa_modenum != 0) { 1072 vga_post_set_vbe(vga_posth, 1073 acpi_md_vesa_modenum); 1074 } 1075 } 1076 # endif 1077 break; 1078 } 1079 1080 # if NACPICA > 0 && defined(VGA_POST) 1081 curmode = newmode; 1082 # endif 1083 #endif 1084 return true; 1085 } 1086 1087 static bool 1088 x86_genfb_suspend(device_t dev, const pmf_qual_t *qual) 1089 { 1090 return true; 1091 } 1092 1093 static bool 1094 x86_genfb_resume(device_t dev, const pmf_qual_t *qual) 1095 { 1096 #if NGENFB > 0 1097 struct pci_genfb_softc *psc = device_private(dev); 1098 1099 #if NACPICA > 0 && defined(VGA_POST) 1100 if (vga_posth != NULL && acpi_md_vbios_reset == 2) { 1101 vga_post_call(vga_posth); 1102 if (acpi_md_vesa_modenum != 0) 1103 vga_post_set_vbe(vga_posth, acpi_md_vesa_modenum); 1104 } 1105 #endif 1106 genfb_restore_palette(&psc->sc_gen); 1107 #endif 1108 1109 return true; 1110 } 1111 1112 static void 1113 populate_fbinfo(device_t dev, prop_dictionary_t dict) 1114 { 1115 #if NWSDISPLAY > 0 && NGENFB > 0 1116 extern struct vcons_screen x86_genfb_console_screen; 1117 struct rasops_info *ri = &x86_genfb_console_screen.scr_ri; 1118 #endif 1119 const void *fbptr = lookup_bootinfo(BTINFO_FRAMEBUFFER); 1120 struct btinfo_framebuffer fbinfo; 1121 1122 if (fbptr == NULL) 1123 return; 1124 1125 memcpy(&fbinfo, fbptr, sizeof(fbinfo)); 1126 1127 if (fbinfo.physaddr != 0) { 1128 prop_dictionary_set_uint32(dict, "width", fbinfo.width); 1129 prop_dictionary_set_uint32(dict, "height", fbinfo.height); 1130 prop_dictionary_set_uint8(dict, "depth", fbinfo.depth); 1131 prop_dictionary_set_uint16(dict, "linebytes", fbinfo.stride); 1132 1133 prop_dictionary_set_uint64(dict, "address", fbinfo.physaddr); 1134 #if NWSDISPLAY > 0 && NGENFB > 0 1135 if (ri->ri_bits != NULL) { 1136 prop_dictionary_set_uint64(dict, "virtual_address", 1137 ri->ri_hwbits != NULL ? 1138 (vaddr_t)ri->ri_hworigbits : 1139 (vaddr_t)ri->ri_origbits); 1140 } 1141 #endif 1142 } 1143 #if notyet 1144 prop_dictionary_set_bool(dict, "splash", 1145 (fbinfo.flags & BI_FB_SPLASH) != 0); 1146 #endif 1147 if (fbinfo.depth == 8) { 1148 gfb_cb.gcc_cookie = NULL; 1149 gfb_cb.gcc_set_mapreg = x86_genfb_set_mapreg; 1150 prop_dictionary_set_uint64(dict, "cmap_callback", 1151 (uint64_t)(uintptr_t)&gfb_cb); 1152 } 1153 if (fbinfo.physaddr != 0) { 1154 mode_cb.gmc_setmode = x86_genfb_setmode; 1155 prop_dictionary_set_uint64(dict, "mode_callback", 1156 (uint64_t)(uintptr_t)&mode_cb); 1157 } 1158 1159 #if NWSDISPLAY > 0 && NGENFB > 0 1160 if (device_is_a(dev, "genfb")) { 1161 prop_dictionary_set_bool(dict, "enable_shadowfb", 1162 ri->ri_hwbits != NULL); 1163 1164 x86_genfb_set_console_dev(dev); 1165 #ifdef DDB 1166 db_trap_callback = x86_genfb_ddb_trap_callback; 1167 #endif 1168 } 1169 #endif 1170 } 1171 1172 device_t 1173 device_pci_register(device_t dev, void *aux) 1174 { 1175 device_t parent = device_parent(dev); 1176 1177 device_pci_props_register(dev, aux); 1178 1179 /* 1180 * Handle network interfaces here, the attachment information is 1181 * not available driver-independently later. 1182 * 1183 * For disks, there is nothing useful available at attach time. 1184 */ 1185 if (device_class(dev) == DV_IFNET) { 1186 struct btinfo_netif *bin = lookup_bootinfo(BTINFO_NETIF); 1187 if (bin == NULL) 1188 return NULL; 1189 1190 /* 1191 * We don't check the driver name against the device name 1192 * passed by the boot ROM. The ROM should stay usable if 1193 * the driver becomes obsolete. The physical attachment 1194 * information (checked below) must be sufficient to 1195 * identify the device. 1196 */ 1197 if (bin->bus == BI_BUS_PCI && device_is_a(parent, "pci")) { 1198 struct pci_attach_args *paa = aux; 1199 int b, d, f; 1200 1201 /* 1202 * Calculate BIOS representation of: 1203 * 1204 * <bus,device,function> 1205 * 1206 * and compare. 1207 */ 1208 pci_decompose_tag(paa->pa_pc, paa->pa_tag, &b, &d, &f); 1209 if (bin->addr.tag == ((b << 8) | (d << 3) | f)) 1210 return dev; 1211 1212 #ifndef XENPV 1213 /* 1214 * efiboot reports parent ppb bus/device/function. 1215 */ 1216 device_t grand = device_parent(parent); 1217 if (efi_probe() && grand && device_is_a(grand, "ppb")) { 1218 struct ppb_softc *ppb_sc = device_private(grand); 1219 pci_decompose_tag(ppb_sc->sc_pc, ppb_sc->sc_tag, 1220 &b, &d, &f); 1221 if (bin->addr.tag == ((b << 8) | (d << 3) | f)) 1222 return dev; 1223 } 1224 #endif 1225 } 1226 } 1227 if (parent && device_is_a(parent, "pci") && 1228 x86_found_console == false) { 1229 struct pci_attach_args *pa = aux; 1230 1231 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_DISPLAY) { 1232 prop_dictionary_t dict = device_properties(dev); 1233 /* 1234 * framebuffer drivers other than genfb can work 1235 * without the address property 1236 */ 1237 populate_fbinfo(dev, dict); 1238 1239 /* 1240 * If the bootloader requested console=pc and 1241 * specified a framebuffer, and if 1242 * x86_genfb_cnattach succeeded in setting it 1243 * up during consinit, then consinit will call 1244 * genfb_cnattach which makes genfb_is_console 1245 * return true. In this case, if it's the 1246 * first genfb we've seen, we will instruct the 1247 * genfb driver via the is_console property 1248 * that it has been selected as the console. 1249 * 1250 * If not all of that happened, then consinit 1251 * can't have selected a genfb console, so this 1252 * device is definitely not the console. 1253 * 1254 * XXX What happens if there's more than one 1255 * PCI display device, and the bootloader picks 1256 * the second one's framebuffer as the console 1257 * framebuffer address? Tough...but this has 1258 * probably never worked. 1259 */ 1260 #if NGENFB > 0 1261 prop_dictionary_set_bool(dict, "is_console", 1262 genfb_is_console()); 1263 #else 1264 prop_dictionary_set_bool(dict, "is_console", 1265 true); 1266 #endif 1267 1268 prop_dictionary_set_bool(dict, "clear-screen", false); 1269 #if NWSDISPLAY > 0 && NGENFB > 0 1270 extern struct vcons_screen x86_genfb_console_screen; 1271 prop_dictionary_set_uint16(dict, "cursor-row", 1272 x86_genfb_console_screen.scr_ri.ri_crow); 1273 #endif 1274 #if notyet 1275 prop_dictionary_set_bool(dict, "splash", 1276 (fbinfo->flags & BI_FB_SPLASH) != 0); 1277 #endif 1278 pmf_cb.gpc_suspend = x86_genfb_suspend; 1279 pmf_cb.gpc_resume = x86_genfb_resume; 1280 prop_dictionary_set_uint64(dict, 1281 "pmf_callback", (uint64_t)(uintptr_t)&pmf_cb); 1282 #ifdef VGA_POST 1283 vga_posth = vga_post_init(pa->pa_bus, pa->pa_device, 1284 pa->pa_function); 1285 #endif 1286 x86_found_console = true; 1287 return NULL; 1288 } 1289 } 1290 return NULL; 1291 } 1292 1293 #ifndef PUC_CNBUS 1294 #define PUC_CNBUS 0 1295 #endif 1296 1297 #if NCOM > 0 1298 int 1299 cpu_puc_cnprobe(struct consdev *cn, struct pci_attach_args *pa) 1300 { 1301 pci_mode_detect(); 1302 pa->pa_iot = x86_bus_space_io; 1303 pa->pa_memt = x86_bus_space_mem; 1304 pa->pa_pc = 0; 1305 pa->pa_tag = pci_make_tag(0, PUC_CNBUS, pci_bus_maxdevs(NULL, 0) - 1, 1306 0); 1307 1308 return 0; 1309 } 1310 #endif 1311