1 /* $NetBSD: pci_machdep.c,v 1.80 2018/04/11 10:34:19 nonaka Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved. 35 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 1. Redistributions of source code must retain the above copyright 41 * notice, this list of conditions and the following disclaimer. 42 * 2. Redistributions in binary form must reproduce the above copyright 43 * notice, this list of conditions and the following disclaimer in the 44 * documentation and/or other materials provided with the distribution. 45 * 3. All advertising materials mentioning features or use of this software 46 * must display the following acknowledgement: 47 * This product includes software developed by Charles M. Hannum. 48 * 4. The name of the author may not be used to endorse or promote products 49 * derived from this software without specific prior written permission. 50 * 51 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 52 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 53 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 54 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 55 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 56 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 57 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 58 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 59 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 60 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 61 */ 62 63 /* 64 * Machine-specific functions for PCI autoconfiguration. 65 * 66 * On PCs, there are two methods of generating PCI configuration cycles. 67 * We try to detect the appropriate mechanism for this machine and set 68 * up a few function pointers to access the correct method directly. 69 * 70 * The configuration method can be hard-coded in the config file by 71 * using `options PCI_CONF_MODE=N', where `N' is the configuration mode 72 * as defined in section 3.6.4.1, `Generating Configuration Cycles'. 73 */ 74 75 #include <sys/cdefs.h> 76 __KERNEL_RCSID(0, "$NetBSD: pci_machdep.c,v 1.80 2018/04/11 10:34:19 nonaka Exp $"); 77 78 #include <sys/types.h> 79 #include <sys/param.h> 80 #include <sys/time.h> 81 #include <sys/systm.h> 82 #include <sys/errno.h> 83 #include <sys/device.h> 84 #include <sys/bus.h> 85 #include <sys/cpu.h> 86 #include <sys/kmem.h> 87 88 #include <uvm/uvm_extern.h> 89 90 #include <machine/bus_private.h> 91 92 #include <machine/pio.h> 93 #include <machine/lock.h> 94 95 #include <dev/isa/isareg.h> 96 #include <dev/isa/isavar.h> 97 #include <dev/pci/pcivar.h> 98 #include <dev/pci/pcireg.h> 99 #include <dev/pci/pccbbreg.h> 100 #include <dev/pci/pcidevs.h> 101 #include <dev/pci/ppbvar.h> 102 #include <dev/pci/genfb_pcivar.h> 103 104 #include <dev/wsfb/genfbvar.h> 105 #include <arch/x86/include/genfb_machdep.h> 106 #include <dev/ic/vgareg.h> 107 108 #include "acpica.h" 109 #include "genfb.h" 110 #include "isa.h" 111 #include "opt_acpi.h" 112 #include "opt_ddb.h" 113 #include "opt_mpbios.h" 114 #include "opt_puc.h" 115 #include "opt_vga.h" 116 #include "pci.h" 117 #include "wsdisplay.h" 118 #include "com.h" 119 120 #ifdef DDB 121 #include <machine/db_machdep.h> 122 #include <ddb/db_sym.h> 123 #include <ddb/db_extern.h> 124 #endif 125 126 #ifdef VGA_POST 127 #include <x86/vga_post.h> 128 #endif 129 130 #include <x86/cpuvar.h> 131 132 #include <machine/autoconf.h> 133 #include <machine/bootinfo.h> 134 135 #ifdef MPBIOS 136 #include <machine/mpbiosvar.h> 137 #endif 138 139 #if NACPICA > 0 140 #include <machine/mpacpi.h> 141 #if !defined(NO_PCI_EXTENDED_CONFIG) 142 #include <dev/acpi/acpivar.h> 143 #include <dev/acpi/acpi_mcfg.h> 144 #endif 145 #endif 146 147 #include <machine/mpconfig.h> 148 149 #if NCOM > 0 150 #include <dev/pci/puccn.h> 151 #endif 152 153 #ifndef XEN 154 #include <x86/efi.h> 155 #endif 156 157 #include "opt_pci_conf_mode.h" 158 159 #ifdef PCI_CONF_MODE 160 #if (PCI_CONF_MODE == 1) || (PCI_CONF_MODE == 2) 161 static int pci_mode = PCI_CONF_MODE; 162 #else 163 #error Invalid PCI configuration mode. 164 #endif 165 #else 166 static int pci_mode = -1; 167 #endif 168 169 struct pci_conf_lock { 170 uint32_t cl_cpuno; /* 0: unlocked 171 * 1 + n: locked by CPU n (0 <= n) 172 */ 173 uint32_t cl_sel; /* the address that's being read. */ 174 }; 175 176 static void pci_conf_unlock(struct pci_conf_lock *); 177 static uint32_t pci_conf_selector(pcitag_t, int); 178 static unsigned int pci_conf_port(pcitag_t, int); 179 static void pci_conf_select(uint32_t); 180 static void pci_conf_lock(struct pci_conf_lock *, uint32_t); 181 static void pci_bridge_hook(pci_chipset_tag_t, pcitag_t, void *); 182 struct pci_bridge_hook_arg { 183 void (*func)(pci_chipset_tag_t, pcitag_t, void *); 184 void *arg; 185 }; 186 187 #define PCI_MODE1_ENABLE 0x80000000UL 188 #define PCI_MODE1_ADDRESS_REG 0x0cf8 189 #define PCI_MODE1_DATA_REG 0x0cfc 190 191 #define PCI_MODE2_ENABLE_REG 0x0cf8 192 #define PCI_MODE2_FORWARD_REG 0x0cfa 193 194 #define _tag(b, d, f) \ 195 {.mode1 = PCI_MODE1_ENABLE | ((b) << 16) | ((d) << 11) | ((f) << 8)} 196 #define _qe(bus, dev, fcn, vend, prod) \ 197 {_tag(bus, dev, fcn), PCI_ID_CODE(vend, prod)} 198 const struct { 199 pcitag_t tag; 200 pcireg_t id; 201 } pcim1_quirk_tbl[] = { 202 _qe(0, 0, 0, PCI_VENDOR_INVALID, 0x0000), /* patchable */ 203 _qe(0, 0, 0, PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_TRIFLEX1), 204 /* XXX Triflex2 not tested */ 205 _qe(0, 0, 0, PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_TRIFLEX2), 206 _qe(0, 0, 0, PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_TRIFLEX4), 207 /* Triton needed for Connectix Virtual PC */ 208 _qe(0, 0, 0, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82437FX), 209 /* Connectix Virtual PC 5 has a 440BX */ 210 _qe(0, 0, 0, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82443BX_NOAGP), 211 /* Parallels Desktop for Mac */ 212 _qe(0, 2, 0, PCI_VENDOR_PARALLELS, PCI_PRODUCT_PARALLELS_VIDEO), 213 _qe(0, 3, 0, PCI_VENDOR_PARALLELS, PCI_PRODUCT_PARALLELS_TOOLS), 214 /* SIS 740 */ 215 _qe(0, 0, 0, PCI_VENDOR_SIS, PCI_PRODUCT_SIS_740), 216 /* SIS 741 */ 217 _qe(0, 0, 0, PCI_VENDOR_SIS, PCI_PRODUCT_SIS_741), 218 /* VIA Technologies VX900 */ 219 _qe(0, 0, 0, PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VX900_HB) 220 }; 221 #undef _tag 222 #undef _qe 223 224 /* arch/xen does not support MSI/MSI-X yet. */ 225 #ifdef __HAVE_PCI_MSI_MSIX 226 #define PCI_QUIRK_DISABLE_MSI 1 /* Neigher MSI nor MSI-X work */ 227 #define PCI_QUIRK_DISABLE_MSIX 2 /* MSI-X does not work */ 228 #define PCI_QUIRK_ENABLE_MSI_VM 3 /* Older chipset in VM where MSI and MSI-X works */ 229 230 #define _dme(vend, prod) \ 231 { PCI_QUIRK_DISABLE_MSI, PCI_ID_CODE(vend, prod) } 232 #define _dmxe(vend, prod) \ 233 { PCI_QUIRK_DISABLE_MSIX, PCI_ID_CODE(vend, prod) } 234 #define _emve(vend, prod) \ 235 { PCI_QUIRK_ENABLE_MSI_VM, PCI_ID_CODE(vend, prod) } 236 const struct { 237 int type; 238 pcireg_t id; 239 } pci_msi_quirk_tbl[] = { 240 _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PCMC), 241 _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82437FX), 242 _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82437MX), 243 _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82437VX), 244 _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82439HX), 245 _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82439TX), 246 _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82443GX), 247 _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82443GX_AGP), 248 _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82440MX), 249 _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82441FX), 250 _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82443BX), 251 _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82443BX_AGP), 252 _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82443BX_NOAGP), 253 _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82443GX_NOAGP), 254 _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82443LX), 255 _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82443LX_AGP), 256 _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82810_MCH), 257 _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82810E_MCH), 258 _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82815_FULL_HUB), 259 _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82820_MCH), 260 _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82830MP_IO_1), 261 _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82840_HB), 262 _dme(PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE_PCHB), 263 _dme(PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_PCHB), 264 _dme(PCI_VENDOR_AMD, PCI_PRODUCT_AMD_SC751_SC), 265 _dme(PCI_VENDOR_AMD, PCI_PRODUCT_AMD_SC761_SC), 266 _dme(PCI_VENDOR_AMD, PCI_PRODUCT_AMD_SC762_NB), 267 268 _emve(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82441FX), /* QEMU */ 269 _emve(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82443BX), /* VMWare */ 270 }; 271 #undef _dme 272 #undef _dmxe 273 #undef _emve 274 #endif /* __HAVE_PCI_MSI_MSIX */ 275 276 /* 277 * PCI doesn't have any special needs; just use the generic versions 278 * of these functions. 279 */ 280 struct x86_bus_dma_tag pci_bus_dma_tag = { 281 ._tag_needs_free = 0, 282 #if defined(_LP64) || defined(PAE) 283 ._bounce_thresh = PCI32_DMA_BOUNCE_THRESHOLD, 284 ._bounce_alloc_lo = ISA_DMA_BOUNCE_THRESHOLD, 285 ._bounce_alloc_hi = PCI32_DMA_BOUNCE_THRESHOLD, 286 #else 287 ._bounce_thresh = 0, 288 ._bounce_alloc_lo = 0, 289 ._bounce_alloc_hi = 0, 290 #endif 291 ._may_bounce = NULL, 292 }; 293 294 #ifdef _LP64 295 struct x86_bus_dma_tag pci_bus_dma64_tag = { 296 ._tag_needs_free = 0, 297 ._bounce_thresh = 0, 298 ._bounce_alloc_lo = 0, 299 ._bounce_alloc_hi = 0, 300 ._may_bounce = NULL, 301 }; 302 #endif 303 304 static struct pci_conf_lock cl0 = { 305 .cl_cpuno = 0UL 306 , .cl_sel = 0UL 307 }; 308 309 static struct pci_conf_lock * const cl = &cl0; 310 311 #if NGENFB > 0 && NACPICA > 0 && defined(VGA_POST) 312 extern int acpi_md_vbios_reset; 313 extern int acpi_md_vesa_modenum; 314 #endif 315 316 static struct genfb_colormap_callback gfb_cb; 317 static struct genfb_pmf_callback pmf_cb; 318 static struct genfb_mode_callback mode_cb; 319 #ifdef VGA_POST 320 static struct vga_post *vga_posth = NULL; 321 #endif 322 323 static void 324 pci_conf_lock(struct pci_conf_lock *ocl, uint32_t sel) 325 { 326 uint32_t cpuno; 327 328 KASSERT(sel != 0); 329 330 kpreempt_disable(); 331 cpuno = cpu_number() + 1; 332 /* If the kernel enters pci_conf_lock() through an interrupt 333 * handler, then the CPU may already hold the lock. 334 * 335 * If the CPU does not already hold the lock, spin until 336 * we can acquire it. 337 */ 338 if (cpuno == cl->cl_cpuno) { 339 ocl->cl_cpuno = cpuno; 340 } else { 341 u_int spins; 342 343 ocl->cl_cpuno = 0; 344 345 spins = SPINLOCK_BACKOFF_MIN; 346 while (atomic_cas_32(&cl->cl_cpuno, 0, cpuno) != 0) { 347 SPINLOCK_BACKOFF(spins); 348 #ifdef LOCKDEBUG 349 if (SPINLOCK_SPINOUT(spins)) { 350 panic("%s: cpu %" PRId32 351 " spun out waiting for cpu %" PRId32, 352 __func__, cpuno, cl->cl_cpuno); 353 } 354 #endif /* LOCKDEBUG */ 355 } 356 } 357 358 /* Only one CPU can be here, so an interlocked atomic_swap(3) 359 * is not necessary. 360 * 361 * Evaluating atomic_cas_32_ni()'s argument, cl->cl_sel, 362 * and applying atomic_cas_32_ni() is not an atomic operation, 363 * however, any interrupt that, in the middle of the 364 * operation, modifies cl->cl_sel, will also restore 365 * cl->cl_sel. So cl->cl_sel will have the same value when 366 * we apply atomic_cas_32_ni() as when we evaluated it, 367 * before. 368 */ 369 ocl->cl_sel = atomic_cas_32_ni(&cl->cl_sel, cl->cl_sel, sel); 370 pci_conf_select(sel); 371 } 372 373 static void 374 pci_conf_unlock(struct pci_conf_lock *ocl) 375 { 376 atomic_cas_32_ni(&cl->cl_sel, cl->cl_sel, ocl->cl_sel); 377 pci_conf_select(ocl->cl_sel); 378 if (ocl->cl_cpuno != cl->cl_cpuno) 379 atomic_cas_32(&cl->cl_cpuno, cl->cl_cpuno, ocl->cl_cpuno); 380 kpreempt_enable(); 381 } 382 383 static uint32_t 384 pci_conf_selector(pcitag_t tag, int reg) 385 { 386 static const pcitag_t mode2_mask = { 387 .mode2 = { 388 .enable = 0xff 389 , .forward = 0xff 390 } 391 }; 392 393 switch (pci_mode) { 394 case 1: 395 return tag.mode1 | reg; 396 case 2: 397 return tag.mode1 & mode2_mask.mode1; 398 default: 399 panic("%s: mode %d not configured", __func__, pci_mode); 400 } 401 } 402 403 static unsigned int 404 pci_conf_port(pcitag_t tag, int reg) 405 { 406 switch (pci_mode) { 407 case 1: 408 return PCI_MODE1_DATA_REG; 409 case 2: 410 return tag.mode2.port | reg; 411 default: 412 panic("%s: mode %d not configured", __func__, pci_mode); 413 } 414 } 415 416 static void 417 pci_conf_select(uint32_t sel) 418 { 419 pcitag_t tag; 420 421 switch (pci_mode) { 422 case 1: 423 outl(PCI_MODE1_ADDRESS_REG, sel); 424 return; 425 case 2: 426 tag.mode1 = sel; 427 outb(PCI_MODE2_ENABLE_REG, tag.mode2.enable); 428 if (tag.mode2.enable != 0) 429 outb(PCI_MODE2_FORWARD_REG, tag.mode2.forward); 430 return; 431 default: 432 panic("%s: mode %d not configured", __func__, pci_mode); 433 } 434 } 435 436 #ifdef __HAVE_PCI_MSI_MSIX 437 static int 438 pci_has_msi_quirk(pcireg_t id, int type) 439 { 440 int i; 441 442 for (i = 0; i < __arraycount(pci_msi_quirk_tbl); i++) { 443 if (id == pci_msi_quirk_tbl[i].id && 444 type == pci_msi_quirk_tbl[i].type) 445 return 1; 446 } 447 448 return 0; 449 } 450 #endif 451 452 void 453 pci_attach_hook(device_t parent, device_t self, struct pcibus_attach_args *pba) 454 { 455 #ifdef __HAVE_PCI_MSI_MSIX 456 pci_chipset_tag_t pc = pba->pba_pc; 457 pcitag_t tag; 458 pcireg_t id, class; 459 #endif 460 461 if (pba->pba_bus == 0) 462 aprint_normal(": configuration mode %d", pci_mode); 463 #ifdef MPBIOS 464 mpbios_pci_attach_hook(parent, self, pba); 465 #endif 466 #if NACPICA > 0 467 mpacpi_pci_attach_hook(parent, self, pba); 468 #endif 469 #if NACPICA > 0 && !defined(NO_PCI_EXTENDED_CONFIG) 470 acpimcfg_map_bus(self, pba->pba_pc, pba->pba_bus); 471 #endif 472 473 #ifdef __HAVE_PCI_MSI_MSIX 474 /* 475 * In order to decide whether the system supports MSI we look 476 * at the host bridge, which should be device 0 function 0 on 477 * bus 0. It is better to not enable MSI on systems that 478 * support it than the other way around, so be conservative 479 * here. So we don't enable MSI if we don't find a host 480 * bridge there. We also deliberately don't enable MSI on 481 * chipsets from low-end manifacturers like VIA and SiS. 482 */ 483 tag = pci_make_tag(pc, 0, 0, 0); 484 id = pci_conf_read(pc, tag, PCI_ID_REG); 485 class = pci_conf_read(pc, tag, PCI_CLASS_REG); 486 487 if (PCI_CLASS(class) != PCI_CLASS_BRIDGE || 488 PCI_SUBCLASS(class) != PCI_SUBCLASS_BRIDGE_HOST) 489 return; 490 491 /* VMware and KVM use old chipset, but they can use MSI/MSI-X */ 492 if ((cpu_feature[1] & CPUID2_RAZ) 493 && (pci_has_msi_quirk(id, PCI_QUIRK_ENABLE_MSI_VM))) { 494 pba->pba_flags |= PCI_FLAGS_MSI_OKAY; 495 pba->pba_flags |= PCI_FLAGS_MSIX_OKAY; 496 } else if (pci_has_msi_quirk(id, PCI_QUIRK_DISABLE_MSI)) { 497 pba->pba_flags &= ~PCI_FLAGS_MSI_OKAY; 498 pba->pba_flags &= ~PCI_FLAGS_MSIX_OKAY; 499 aprint_verbose("\n"); 500 aprint_verbose_dev(self, 501 "This pci host supports neither MSI nor MSI-X."); 502 } else if (pci_has_msi_quirk(id, PCI_QUIRK_DISABLE_MSIX)) { 503 pba->pba_flags |= PCI_FLAGS_MSI_OKAY; 504 pba->pba_flags &= ~PCI_FLAGS_MSIX_OKAY; 505 aprint_verbose("\n"); 506 aprint_verbose_dev(self, 507 "This pci host does not support MSI-X."); 508 } else { 509 pba->pba_flags |= PCI_FLAGS_MSI_OKAY; 510 pba->pba_flags |= PCI_FLAGS_MSIX_OKAY; 511 } 512 513 /* 514 * Don't enable MSI on a HyperTransport bus. In order to 515 * determine that bus 0 is a HyperTransport bus, we look at 516 * device 24 function 0, which is the HyperTransport 517 * host/primary interface integrated on most 64-bit AMD CPUs. 518 * If that device has a HyperTransport capability, bus 0 must 519 * be a HyperTransport bus and we disable MSI. 520 */ 521 if (24 < pci_bus_maxdevs(pc, 0)) { 522 tag = pci_make_tag(pc, 0, 24, 0); 523 if (pci_get_capability(pc, tag, PCI_CAP_LDT, NULL, NULL)) { 524 pba->pba_flags &= ~PCI_FLAGS_MSI_OKAY; 525 pba->pba_flags &= ~PCI_FLAGS_MSIX_OKAY; 526 } 527 } 528 #endif /* __HAVE_PCI_MSI_MSIX */ 529 } 530 531 int 532 pci_bus_maxdevs(pci_chipset_tag_t pc, int busno) 533 { 534 /* 535 * Bus number is irrelevant. If Configuration Mechanism 2 is in 536 * use, can only have devices 0-15 on any bus. If Configuration 537 * Mechanism 1 is in use, can have devices 0-32 (i.e. the `normal' 538 * range). 539 */ 540 if (pci_mode == 2) 541 return (16); 542 else 543 return (32); 544 } 545 546 pcitag_t 547 pci_make_tag(pci_chipset_tag_t pc, int bus, int device, int function) 548 { 549 pci_chipset_tag_t ipc; 550 pcitag_t tag; 551 552 for (ipc = pc; ipc != NULL; ipc = ipc->pc_super) { 553 if ((ipc->pc_present & PCI_OVERRIDE_MAKE_TAG) == 0) 554 continue; 555 return (*ipc->pc_ov->ov_make_tag)(ipc->pc_ctx, 556 pc, bus, device, function); 557 } 558 559 switch (pci_mode) { 560 case 1: 561 if (bus >= 256 || device >= 32 || function >= 8) 562 panic("%s: bad request(%d, %d, %d)", __func__, 563 bus, device, function); 564 565 tag.mode1 = PCI_MODE1_ENABLE | 566 (bus << 16) | (device << 11) | (function << 8); 567 return tag; 568 case 2: 569 if (bus >= 256 || device >= 16 || function >= 8) 570 panic("%s: bad request(%d, %d, %d)", __func__, 571 bus, device, function); 572 573 tag.mode2.port = 0xc000 | (device << 8); 574 tag.mode2.enable = 0xf0 | (function << 1); 575 tag.mode2.forward = bus; 576 return tag; 577 default: 578 panic("%s: mode %d not configured", __func__, pci_mode); 579 } 580 } 581 582 void 583 pci_decompose_tag(pci_chipset_tag_t pc, pcitag_t tag, 584 int *bp, int *dp, int *fp) 585 { 586 pci_chipset_tag_t ipc; 587 588 for (ipc = pc; ipc != NULL; ipc = ipc->pc_super) { 589 if ((ipc->pc_present & PCI_OVERRIDE_DECOMPOSE_TAG) == 0) 590 continue; 591 (*ipc->pc_ov->ov_decompose_tag)(ipc->pc_ctx, 592 pc, tag, bp, dp, fp); 593 return; 594 } 595 596 switch (pci_mode) { 597 case 1: 598 if (bp != NULL) 599 *bp = (tag.mode1 >> 16) & 0xff; 600 if (dp != NULL) 601 *dp = (tag.mode1 >> 11) & 0x1f; 602 if (fp != NULL) 603 *fp = (tag.mode1 >> 8) & 0x7; 604 return; 605 case 2: 606 if (bp != NULL) 607 *bp = tag.mode2.forward & 0xff; 608 if (dp != NULL) 609 *dp = (tag.mode2.port >> 8) & 0xf; 610 if (fp != NULL) 611 *fp = (tag.mode2.enable >> 1) & 0x7; 612 return; 613 default: 614 panic("%s: mode %d not configured", __func__, pci_mode); 615 } 616 } 617 618 pcireg_t 619 pci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg) 620 { 621 pci_chipset_tag_t ipc; 622 pcireg_t data; 623 struct pci_conf_lock ocl; 624 int dev; 625 626 KASSERT((reg & 0x3) == 0); 627 628 for (ipc = pc; ipc != NULL; ipc = ipc->pc_super) { 629 if ((ipc->pc_present & PCI_OVERRIDE_CONF_READ) == 0) 630 continue; 631 return (*ipc->pc_ov->ov_conf_read)(ipc->pc_ctx, pc, tag, reg); 632 } 633 634 pci_decompose_tag(pc, tag, NULL, &dev, NULL); 635 if (__predict_false(pci_mode == 2 && dev >= 16)) 636 return (pcireg_t) -1; 637 638 if (reg < 0) 639 return (pcireg_t) -1; 640 if (reg >= PCI_CONF_SIZE) { 641 #if NACPICA > 0 && !defined(NO_PCI_EXTENDED_CONFIG) 642 if (reg >= PCI_EXTCONF_SIZE) 643 return (pcireg_t) -1; 644 acpimcfg_conf_read(pc, tag, reg, &data); 645 return data; 646 #else 647 return (pcireg_t) -1; 648 #endif 649 } 650 651 pci_conf_lock(&ocl, pci_conf_selector(tag, reg)); 652 data = inl(pci_conf_port(tag, reg)); 653 pci_conf_unlock(&ocl); 654 return data; 655 } 656 657 void 658 pci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data) 659 { 660 pci_chipset_tag_t ipc; 661 struct pci_conf_lock ocl; 662 int dev; 663 664 KASSERT((reg & 0x3) == 0); 665 666 for (ipc = pc; ipc != NULL; ipc = ipc->pc_super) { 667 if ((ipc->pc_present & PCI_OVERRIDE_CONF_WRITE) == 0) 668 continue; 669 (*ipc->pc_ov->ov_conf_write)(ipc->pc_ctx, pc, tag, reg, 670 data); 671 return; 672 } 673 674 pci_decompose_tag(pc, tag, NULL, &dev, NULL); 675 if (__predict_false(pci_mode == 2 && dev >= 16)) { 676 return; 677 } 678 679 if (reg < 0) 680 return; 681 if (reg >= PCI_CONF_SIZE) { 682 #if NACPICA > 0 && !defined(NO_PCI_EXTENDED_CONFIG) 683 if (reg >= PCI_EXTCONF_SIZE) 684 return; 685 acpimcfg_conf_write(pc, tag, reg, data); 686 #endif 687 return; 688 } 689 690 pci_conf_lock(&ocl, pci_conf_selector(tag, reg)); 691 outl(pci_conf_port(tag, reg), data); 692 pci_conf_unlock(&ocl); 693 } 694 695 void 696 pci_mode_set(int mode) 697 { 698 KASSERT(pci_mode == -1 || pci_mode == mode); 699 700 pci_mode = mode; 701 } 702 703 int 704 pci_mode_detect(void) 705 { 706 uint32_t sav, val; 707 int i; 708 pcireg_t idreg; 709 extern char cpu_brand_string[]; 710 711 if (pci_mode != -1) 712 return pci_mode; 713 714 /* 715 * We try to divine which configuration mode the host bridge wants. 716 */ 717 718 sav = inl(PCI_MODE1_ADDRESS_REG); 719 720 pci_mode = 1; /* assume this for now */ 721 /* 722 * catch some known buggy implementations of mode 1 723 */ 724 for (i = 0; i < __arraycount(pcim1_quirk_tbl); i++) { 725 pcitag_t t; 726 727 if (PCI_VENDOR(pcim1_quirk_tbl[i].id) == PCI_VENDOR_INVALID) 728 continue; 729 t.mode1 = pcim1_quirk_tbl[i].tag.mode1; 730 idreg = pci_conf_read(NULL, t, PCI_ID_REG); /* needs "pci_mode" */ 731 if (idreg == pcim1_quirk_tbl[i].id) { 732 #ifdef DEBUG 733 printf("%s: known mode 1 PCI chipset (%08x)\n", 734 __func__, idreg); 735 #endif 736 return (pci_mode); 737 } 738 } 739 740 const char *reason, *system_vendor, *system_product; 741 if (memcmp(cpu_brand_string, "QEMU", 4) == 0) 742 /* PR 45671, https://bugs.launchpad.net/qemu/+bug/897771 */ 743 reason = "QEMU"; 744 else if ((system_vendor = pmf_get_platform("system-vendor")) != NULL && 745 strcmp(system_vendor, "Xen") == 0 && 746 (system_product = pmf_get_platform("system-product")) != NULL && 747 strcmp(system_product, "HVM domU") == 0) 748 reason = "Xen"; 749 else 750 reason = NULL; 751 752 if (reason) { 753 #ifdef DEBUG 754 printf("%s: forcing PCI mode 1 for %s\n", __func__, reason); 755 #endif 756 return (pci_mode); 757 } 758 759 /* 760 * Strong check for standard compliant mode 1: 761 * 1. bit 31 ("enable") can be set 762 * 2. byte/word access does not affect register 763 */ 764 outl(PCI_MODE1_ADDRESS_REG, PCI_MODE1_ENABLE); 765 outb(PCI_MODE1_ADDRESS_REG + 3, 0); 766 outw(PCI_MODE1_ADDRESS_REG + 2, 0); 767 val = inl(PCI_MODE1_ADDRESS_REG); 768 if ((val & 0x80fffffc) != PCI_MODE1_ENABLE) { 769 #ifdef DEBUG 770 printf("%s: mode 1 enable failed (%x)\n", __func__, val); 771 #endif 772 goto not1; 773 } 774 outl(PCI_MODE1_ADDRESS_REG, 0); 775 val = inl(PCI_MODE1_ADDRESS_REG); 776 if ((val & 0x80fffffc) != 0) 777 goto not1; 778 return (pci_mode); 779 not1: 780 outl(PCI_MODE1_ADDRESS_REG, sav); 781 782 /* 783 * This mode 2 check is quite weak (and known to give false 784 * positives on some Compaq machines). 785 * However, this doesn't matter, because this is the 786 * last test, and simply no PCI devices will be found if 787 * this happens. 788 */ 789 outb(PCI_MODE2_ENABLE_REG, 0); 790 outb(PCI_MODE2_FORWARD_REG, 0); 791 if (inb(PCI_MODE2_ENABLE_REG) != 0 || 792 inb(PCI_MODE2_FORWARD_REG) != 0) 793 goto not2; 794 return (pci_mode = 2); 795 not2: 796 797 return (pci_mode = 0); 798 } 799 800 void 801 pci_device_foreach(pci_chipset_tag_t pc, int maxbus, 802 void (*func)(pci_chipset_tag_t, pcitag_t, void *), void *context) 803 { 804 pci_device_foreach_min(pc, 0, maxbus, func, context); 805 } 806 807 void 808 pci_device_foreach_min(pci_chipset_tag_t pc, int minbus, int maxbus, 809 void (*func)(pci_chipset_tag_t, pcitag_t, void *), void *context) 810 { 811 const struct pci_quirkdata *qd; 812 int bus, device, function, maxdevs, nfuncs; 813 pcireg_t id, bhlcr; 814 pcitag_t tag; 815 816 for (bus = minbus; bus <= maxbus; bus++) { 817 maxdevs = pci_bus_maxdevs(pc, bus); 818 for (device = 0; device < maxdevs; device++) { 819 tag = pci_make_tag(pc, bus, device, 0); 820 id = pci_conf_read(pc, tag, PCI_ID_REG); 821 822 /* Invalid vendor ID value? */ 823 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 824 continue; 825 /* XXX Not invalid, but we've done this ~forever. */ 826 if (PCI_VENDOR(id) == 0) 827 continue; 828 829 qd = pci_lookup_quirkdata(PCI_VENDOR(id), 830 PCI_PRODUCT(id)); 831 832 bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 833 if (PCI_HDRTYPE_MULTIFN(bhlcr) || 834 (qd != NULL && 835 (qd->quirks & PCI_QUIRK_MULTIFUNCTION) != 0)) 836 nfuncs = 8; 837 else 838 nfuncs = 1; 839 840 for (function = 0; function < nfuncs; function++) { 841 tag = pci_make_tag(pc, bus, device, function); 842 id = pci_conf_read(pc, tag, PCI_ID_REG); 843 844 /* Invalid vendor ID value? */ 845 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 846 continue; 847 /* 848 * XXX Not invalid, but we've done this 849 * ~forever. 850 */ 851 if (PCI_VENDOR(id) == 0) 852 continue; 853 (*func)(pc, tag, context); 854 } 855 } 856 } 857 } 858 859 void 860 pci_bridge_foreach(pci_chipset_tag_t pc, int minbus, int maxbus, 861 void (*func)(pci_chipset_tag_t, pcitag_t, void *), void *ctx) 862 { 863 struct pci_bridge_hook_arg bridge_hook; 864 865 bridge_hook.func = func; 866 bridge_hook.arg = ctx; 867 868 pci_device_foreach_min(pc, minbus, maxbus, pci_bridge_hook, 869 &bridge_hook); 870 } 871 872 static void 873 pci_bridge_hook(pci_chipset_tag_t pc, pcitag_t tag, void *ctx) 874 { 875 struct pci_bridge_hook_arg *bridge_hook = (void *)ctx; 876 pcireg_t reg; 877 878 reg = pci_conf_read(pc, tag, PCI_CLASS_REG); 879 if (PCI_CLASS(reg) == PCI_CLASS_BRIDGE && 880 (PCI_SUBCLASS(reg) == PCI_SUBCLASS_BRIDGE_PCI || 881 PCI_SUBCLASS(reg) == PCI_SUBCLASS_BRIDGE_CARDBUS)) { 882 (*bridge_hook->func)(pc, tag, bridge_hook->arg); 883 } 884 } 885 886 static const void * 887 bit_to_function_pointer(const struct pci_overrides *ov, uint64_t bit) 888 { 889 switch (bit) { 890 case PCI_OVERRIDE_CONF_READ: 891 return ov->ov_conf_read; 892 case PCI_OVERRIDE_CONF_WRITE: 893 return ov->ov_conf_write; 894 case PCI_OVERRIDE_INTR_MAP: 895 return ov->ov_intr_map; 896 case PCI_OVERRIDE_INTR_STRING: 897 return ov->ov_intr_string; 898 case PCI_OVERRIDE_INTR_EVCNT: 899 return ov->ov_intr_evcnt; 900 case PCI_OVERRIDE_INTR_ESTABLISH: 901 return ov->ov_intr_establish; 902 case PCI_OVERRIDE_INTR_DISESTABLISH: 903 return ov->ov_intr_disestablish; 904 case PCI_OVERRIDE_MAKE_TAG: 905 return ov->ov_make_tag; 906 case PCI_OVERRIDE_DECOMPOSE_TAG: 907 return ov->ov_decompose_tag; 908 default: 909 return NULL; 910 } 911 } 912 913 void 914 pci_chipset_tag_destroy(pci_chipset_tag_t pc) 915 { 916 kmem_free(pc, sizeof(struct pci_chipset_tag)); 917 } 918 919 int 920 pci_chipset_tag_create(pci_chipset_tag_t opc, const uint64_t present, 921 const struct pci_overrides *ov, void *ctx, pci_chipset_tag_t *pcp) 922 { 923 uint64_t bit, bits, nbits; 924 pci_chipset_tag_t pc; 925 const void *fp; 926 927 if (ov == NULL || present == 0) 928 return EINVAL; 929 930 pc = kmem_alloc(sizeof(struct pci_chipset_tag), KM_SLEEP); 931 pc->pc_super = opc; 932 933 for (bits = present; bits != 0; bits = nbits) { 934 nbits = bits & (bits - 1); 935 bit = nbits ^ bits; 936 if ((fp = bit_to_function_pointer(ov, bit)) == NULL) { 937 #ifdef DEBUG 938 printf("%s: missing bit %" PRIx64 "\n", __func__, bit); 939 #endif 940 goto einval; 941 } 942 } 943 944 pc->pc_ov = ov; 945 pc->pc_present = present; 946 pc->pc_ctx = ctx; 947 948 *pcp = pc; 949 950 return 0; 951 einval: 952 kmem_free(pc, sizeof(struct pci_chipset_tag)); 953 return EINVAL; 954 } 955 956 static void 957 x86_genfb_set_mapreg(void *opaque, int index, int r, int g, int b) 958 { 959 outb(IO_VGA + VGA_DAC_ADDRW, index); 960 outb(IO_VGA + VGA_DAC_PALETTE, (uint8_t)r >> 2); 961 outb(IO_VGA + VGA_DAC_PALETTE, (uint8_t)g >> 2); 962 outb(IO_VGA + VGA_DAC_PALETTE, (uint8_t)b >> 2); 963 } 964 965 static bool 966 x86_genfb_setmode(struct genfb_softc *sc, int newmode) 967 { 968 #if NGENFB > 0 969 # if NACPICA > 0 && defined(VGA_POST) 970 static int curmode = WSDISPLAYIO_MODE_EMUL; 971 # endif 972 973 switch (newmode) { 974 case WSDISPLAYIO_MODE_EMUL: 975 x86_genfb_mtrr_init(sc->sc_fboffset, 976 sc->sc_height * sc->sc_stride); 977 # if NACPICA > 0 && defined(VGA_POST) 978 if (curmode != newmode) { 979 if (vga_posth != NULL && acpi_md_vesa_modenum != 0) { 980 vga_post_set_vbe(vga_posth, 981 acpi_md_vesa_modenum); 982 } 983 } 984 # endif 985 break; 986 } 987 988 # if NACPICA > 0 && defined(VGA_POST) 989 curmode = newmode; 990 # endif 991 #endif 992 return true; 993 } 994 995 static bool 996 x86_genfb_suspend(device_t dev, const pmf_qual_t *qual) 997 { 998 return true; 999 } 1000 1001 static bool 1002 x86_genfb_resume(device_t dev, const pmf_qual_t *qual) 1003 { 1004 #if NGENFB > 0 1005 struct pci_genfb_softc *psc = device_private(dev); 1006 1007 #if NACPICA > 0 && defined(VGA_POST) 1008 if (vga_posth != NULL && acpi_md_vbios_reset == 2) { 1009 vga_post_call(vga_posth); 1010 if (acpi_md_vesa_modenum != 0) 1011 vga_post_set_vbe(vga_posth, acpi_md_vesa_modenum); 1012 } 1013 #endif 1014 genfb_restore_palette(&psc->sc_gen); 1015 #endif 1016 1017 return true; 1018 } 1019 1020 device_t 1021 device_pci_register(device_t dev, void *aux) 1022 { 1023 static bool found_console = false; 1024 device_t parent = device_parent(dev); 1025 1026 device_pci_props_register(dev, aux); 1027 1028 /* 1029 * Handle network interfaces here, the attachment information is 1030 * not available driver-independently later. 1031 * 1032 * For disks, there is nothing useful available at attach time. 1033 */ 1034 if (device_class(dev) == DV_IFNET) { 1035 struct btinfo_netif *bin = lookup_bootinfo(BTINFO_NETIF); 1036 if (bin == NULL) 1037 return NULL; 1038 1039 /* 1040 * We don't check the driver name against the device name 1041 * passed by the boot ROM. The ROM should stay usable if 1042 * the driver becomes obsolete. The physical attachment 1043 * information (checked below) must be sufficient to 1044 * identify the device. 1045 */ 1046 if (bin->bus == BI_BUS_PCI && device_is_a(parent, "pci")) { 1047 struct pci_attach_args *paa = aux; 1048 int b, d, f; 1049 1050 /* 1051 * Calculate BIOS representation of: 1052 * 1053 * <bus,device,function> 1054 * 1055 * and compare. 1056 */ 1057 pci_decompose_tag(paa->pa_pc, paa->pa_tag, &b, &d, &f); 1058 if (bin->addr.tag == ((b << 8) | (d << 3) | f)) 1059 return dev; 1060 1061 #ifndef XEN 1062 /* 1063 * efiboot reports parent ppb bus/device/function. 1064 */ 1065 device_t grand = device_parent(parent); 1066 if (efi_probe() && grand && device_is_a(grand, "ppb")) { 1067 struct ppb_softc *ppb_sc = device_private(grand); 1068 pci_decompose_tag(ppb_sc->sc_pc, ppb_sc->sc_tag, 1069 &b, &d, &f); 1070 if (bin->addr.tag == ((b << 8) | (d << 3) | f)) 1071 return dev; 1072 } 1073 #endif 1074 } 1075 } 1076 if (parent && device_is_a(parent, "pci") && 1077 found_console == false) { 1078 struct btinfo_framebuffer *fbinfo; 1079 struct pci_attach_args *pa = aux; 1080 prop_dictionary_t dict; 1081 1082 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_DISPLAY) { 1083 #if NWSDISPLAY > 0 && NGENFB > 0 1084 extern struct vcons_screen x86_genfb_console_screen; 1085 struct rasops_info *ri; 1086 1087 ri = &x86_genfb_console_screen.scr_ri; 1088 #endif 1089 1090 fbinfo = lookup_bootinfo(BTINFO_FRAMEBUFFER); 1091 dict = device_properties(dev); 1092 /* 1093 * framebuffer drivers other than genfb can work 1094 * without the address property 1095 */ 1096 if (fbinfo != NULL) { 1097 if (fbinfo->physaddr != 0) { 1098 prop_dictionary_set_uint32(dict, "width", 1099 fbinfo->width); 1100 prop_dictionary_set_uint32(dict, "height", 1101 fbinfo->height); 1102 prop_dictionary_set_uint8(dict, "depth", 1103 fbinfo->depth); 1104 prop_dictionary_set_uint16(dict, "linebytes", 1105 fbinfo->stride); 1106 1107 prop_dictionary_set_uint64(dict, "address", 1108 fbinfo->physaddr); 1109 #if NWSDISPLAY > 0 && NGENFB > 0 1110 if (ri->ri_bits != NULL) { 1111 prop_dictionary_set_uint64(dict, 1112 "virtual_address", 1113 ri->ri_hwbits != NULL ? 1114 (vaddr_t)ri->ri_hworigbits : 1115 (vaddr_t)ri->ri_origbits); 1116 } 1117 #endif 1118 } 1119 #if notyet 1120 prop_dictionary_set_bool(dict, "splash", 1121 fbinfo->flags & BI_FB_SPLASH ? 1122 true : false); 1123 #endif 1124 if (fbinfo->depth == 8) { 1125 gfb_cb.gcc_cookie = NULL; 1126 gfb_cb.gcc_set_mapreg = 1127 x86_genfb_set_mapreg; 1128 prop_dictionary_set_uint64(dict, 1129 "cmap_callback", 1130 (uint64_t)(uintptr_t)&gfb_cb); 1131 } 1132 if (fbinfo->physaddr != 0) { 1133 mode_cb.gmc_setmode = x86_genfb_setmode; 1134 prop_dictionary_set_uint64(dict, 1135 "mode_callback", 1136 (uint64_t)(uintptr_t)&mode_cb); 1137 } 1138 1139 #if NWSDISPLAY > 0 && NGENFB > 0 1140 if (device_is_a(dev, "genfb")) { 1141 prop_dictionary_set_bool(dict, 1142 "enable_shadowfb", 1143 ri->ri_hwbits != NULL ? 1144 true : false); 1145 1146 x86_genfb_set_console_dev(dev); 1147 #ifdef DDB 1148 db_trap_callback = 1149 x86_genfb_ddb_trap_callback; 1150 #endif 1151 } 1152 #endif 1153 } 1154 #if 1 && NWSDISPLAY > 0 && NGENFB > 0 1155 /* XXX */ 1156 if (device_is_a(dev, "genfb")) { 1157 prop_dictionary_set_bool(dict, "is_console", 1158 genfb_is_console()); 1159 } else 1160 #endif 1161 prop_dictionary_set_bool(dict, "is_console", true); 1162 1163 prop_dictionary_set_bool(dict, "clear-screen", false); 1164 #if NWSDISPLAY > 0 && NGENFB > 0 1165 prop_dictionary_set_uint16(dict, "cursor-row", 1166 x86_genfb_console_screen.scr_ri.ri_crow); 1167 #endif 1168 #if notyet 1169 prop_dictionary_set_bool(dict, "splash", 1170 fbinfo->flags & BI_FB_SPLASH ? true : false); 1171 #endif 1172 pmf_cb.gpc_suspend = x86_genfb_suspend; 1173 pmf_cb.gpc_resume = x86_genfb_resume; 1174 prop_dictionary_set_uint64(dict, 1175 "pmf_callback", (uint64_t)(uintptr_t)&pmf_cb); 1176 #ifdef VGA_POST 1177 vga_posth = vga_post_init(pa->pa_bus, pa->pa_device, 1178 pa->pa_function); 1179 #endif 1180 found_console = true; 1181 return NULL; 1182 } 1183 } 1184 return NULL; 1185 } 1186 1187 #ifndef PUC_CNBUS 1188 #define PUC_CNBUS 0 1189 #endif 1190 1191 #if NCOM > 0 1192 int 1193 cpu_puc_cnprobe(struct consdev *cn, struct pci_attach_args *pa) 1194 { 1195 pci_mode_detect(); 1196 pa->pa_iot = x86_bus_space_io; 1197 pa->pa_memt = x86_bus_space_mem; 1198 pa->pa_pc = 0; 1199 pa->pa_tag = pci_make_tag(0, PUC_CNBUS, pci_bus_maxdevs(NULL, 0) - 1, 1200 0); 1201 1202 return 0; 1203 } 1204 #endif 1205