1 /* $NetBSD: pci_machdep.c,v 1.83 2018/07/10 06:44:49 maxv Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved. 35 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 1. Redistributions of source code must retain the above copyright 41 * notice, this list of conditions and the following disclaimer. 42 * 2. Redistributions in binary form must reproduce the above copyright 43 * notice, this list of conditions and the following disclaimer in the 44 * documentation and/or other materials provided with the distribution. 45 * 3. All advertising materials mentioning features or use of this software 46 * must display the following acknowledgement: 47 * This product includes software developed by Charles M. Hannum. 48 * 4. The name of the author may not be used to endorse or promote products 49 * derived from this software without specific prior written permission. 50 * 51 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 52 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 53 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 54 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 55 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 56 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 57 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 58 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 59 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 60 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 61 */ 62 63 /* 64 * Machine-specific functions for PCI autoconfiguration. 65 * 66 * On PCs, there are two methods of generating PCI configuration cycles. 67 * We try to detect the appropriate mechanism for this machine and set 68 * up a few function pointers to access the correct method directly. 69 * 70 * The configuration method can be hard-coded in the config file by 71 * using `options PCI_CONF_MODE=N', where `N' is the configuration mode 72 * as defined in section 3.6.4.1, `Generating Configuration Cycles'. 73 */ 74 75 #include <sys/cdefs.h> 76 __KERNEL_RCSID(0, "$NetBSD: pci_machdep.c,v 1.83 2018/07/10 06:44:49 maxv Exp $"); 77 78 #include <sys/types.h> 79 #include <sys/param.h> 80 #include <sys/time.h> 81 #include <sys/systm.h> 82 #include <sys/errno.h> 83 #include <sys/device.h> 84 #include <sys/bus.h> 85 #include <sys/cpu.h> 86 #include <sys/kmem.h> 87 88 #include <uvm/uvm_extern.h> 89 90 #include <machine/bus_private.h> 91 92 #include <machine/pio.h> 93 #include <machine/lock.h> 94 95 #include <dev/isa/isareg.h> 96 #include <dev/isa/isavar.h> 97 #include <dev/pci/pcivar.h> 98 #include <dev/pci/pcireg.h> 99 #include <dev/pci/pccbbreg.h> 100 #include <dev/pci/pcidevs.h> 101 #include <dev/pci/ppbvar.h> 102 #include <dev/pci/genfb_pcivar.h> 103 104 #include <dev/wsfb/genfbvar.h> 105 #include <arch/x86/include/genfb_machdep.h> 106 #include <dev/ic/vgareg.h> 107 108 #include "acpica.h" 109 #include "genfb.h" 110 #include "isa.h" 111 #include "opt_acpi.h" 112 #include "opt_ddb.h" 113 #include "opt_mpbios.h" 114 #include "opt_puc.h" 115 #include "opt_vga.h" 116 #include "pci.h" 117 #include "wsdisplay.h" 118 #include "com.h" 119 120 #ifdef DDB 121 #include <machine/db_machdep.h> 122 #include <ddb/db_sym.h> 123 #include <ddb/db_extern.h> 124 #endif 125 126 #ifdef VGA_POST 127 #include <x86/vga_post.h> 128 #endif 129 130 #include <x86/cpuvar.h> 131 132 #include <machine/autoconf.h> 133 #include <machine/bootinfo.h> 134 135 #ifdef MPBIOS 136 #include <machine/mpbiosvar.h> 137 #endif 138 139 #if NACPICA > 0 140 #include <machine/mpacpi.h> 141 #if !defined(NO_PCI_EXTENDED_CONFIG) 142 #include <dev/acpi/acpivar.h> 143 #include <dev/acpi/acpi_mcfg.h> 144 #endif 145 #endif 146 147 #include <machine/mpconfig.h> 148 149 #if NCOM > 0 150 #include <dev/pci/puccn.h> 151 #endif 152 153 #ifndef XEN 154 #include <x86/efi.h> 155 #endif 156 157 #include "opt_pci_conf_mode.h" 158 159 #ifdef PCI_CONF_MODE 160 #if (PCI_CONF_MODE == 1) || (PCI_CONF_MODE == 2) 161 static int pci_mode = PCI_CONF_MODE; 162 #else 163 #error Invalid PCI configuration mode. 164 #endif 165 #else 166 static int pci_mode = -1; 167 #endif 168 169 struct pci_conf_lock { 170 uint32_t cl_cpuno; /* 0: unlocked 171 * 1 + n: locked by CPU n (0 <= n) 172 */ 173 uint32_t cl_sel; /* the address that's being read. */ 174 }; 175 176 static void pci_conf_unlock(struct pci_conf_lock *); 177 static uint32_t pci_conf_selector(pcitag_t, int); 178 static unsigned int pci_conf_port(pcitag_t, int); 179 static void pci_conf_select(uint32_t); 180 static void pci_conf_lock(struct pci_conf_lock *, uint32_t); 181 static void pci_bridge_hook(pci_chipset_tag_t, pcitag_t, void *); 182 struct pci_bridge_hook_arg { 183 void (*func)(pci_chipset_tag_t, pcitag_t, void *); 184 void *arg; 185 }; 186 187 #define PCI_MODE1_ENABLE 0x80000000UL 188 #define PCI_MODE1_ADDRESS_REG 0x0cf8 189 #define PCI_MODE1_DATA_REG 0x0cfc 190 191 #define PCI_MODE2_ENABLE_REG 0x0cf8 192 #define PCI_MODE2_FORWARD_REG 0x0cfa 193 194 #define _tag(b, d, f) \ 195 {.mode1 = PCI_MODE1_ENABLE | ((b) << 16) | ((d) << 11) | ((f) << 8)} 196 #define _qe(bus, dev, fcn, vend, prod) \ 197 {_tag(bus, dev, fcn), PCI_ID_CODE(vend, prod)} 198 const struct { 199 pcitag_t tag; 200 pcireg_t id; 201 } pcim1_quirk_tbl[] = { 202 _qe(0, 0, 0, PCI_VENDOR_INVALID, 0x0000), /* patchable */ 203 _qe(0, 0, 0, PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_TRIFLEX1), 204 /* XXX Triflex2 not tested */ 205 _qe(0, 0, 0, PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_TRIFLEX2), 206 _qe(0, 0, 0, PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_TRIFLEX4), 207 #if 0 208 /* Triton needed for Connectix Virtual PC */ 209 _qe(0, 0, 0, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82437FX), 210 /* Connectix Virtual PC 5 has a 440BX */ 211 _qe(0, 0, 0, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82443BX_NOAGP), 212 /* Parallels Desktop for Mac */ 213 _qe(0, 2, 0, PCI_VENDOR_PARALLELS, PCI_PRODUCT_PARALLELS_VIDEO), 214 _qe(0, 3, 0, PCI_VENDOR_PARALLELS, PCI_PRODUCT_PARALLELS_TOOLS), 215 /* SIS 740 */ 216 _qe(0, 0, 0, PCI_VENDOR_SIS, PCI_PRODUCT_SIS_740), 217 /* SIS 741 */ 218 _qe(0, 0, 0, PCI_VENDOR_SIS, PCI_PRODUCT_SIS_741), 219 /* VIA Technologies VX900 */ 220 _qe(0, 0, 0, PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VX900_HB) 221 #endif 222 }; 223 #undef _tag 224 #undef _qe 225 226 /* arch/xen does not support MSI/MSI-X yet. */ 227 #ifdef __HAVE_PCI_MSI_MSIX 228 #define PCI_QUIRK_DISABLE_MSI 1 /* Neigher MSI nor MSI-X work */ 229 #define PCI_QUIRK_DISABLE_MSIX 2 /* MSI-X does not work */ 230 #define PCI_QUIRK_ENABLE_MSI_VM 3 /* Older chipset in VM where MSI and MSI-X works */ 231 232 #define _dme(vend, prod) \ 233 { PCI_QUIRK_DISABLE_MSI, PCI_ID_CODE(vend, prod) } 234 #define _dmxe(vend, prod) \ 235 { PCI_QUIRK_DISABLE_MSIX, PCI_ID_CODE(vend, prod) } 236 #define _emve(vend, prod) \ 237 { PCI_QUIRK_ENABLE_MSI_VM, PCI_ID_CODE(vend, prod) } 238 const struct { 239 int type; 240 pcireg_t id; 241 } pci_msi_quirk_tbl[] = { 242 _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PCMC), 243 _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82437FX), 244 _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82437MX), 245 _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82437VX), 246 _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82439HX), 247 _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82439TX), 248 _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82443GX), 249 _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82443GX_AGP), 250 _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82440MX), 251 _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82441FX), 252 _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82443BX), 253 _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82443BX_AGP), 254 _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82443BX_NOAGP), 255 _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82443GX_NOAGP), 256 _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82443LX), 257 _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82443LX_AGP), 258 _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82810_MCH), 259 _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82810E_MCH), 260 _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82815_FULL_HUB), 261 _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82820_MCH), 262 _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82830MP_IO_1), 263 _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82840_HB), 264 _dme(PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE_PCHB), 265 _dme(PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_PCHB), 266 _dme(PCI_VENDOR_AMD, PCI_PRODUCT_AMD_SC751_SC), 267 _dme(PCI_VENDOR_AMD, PCI_PRODUCT_AMD_SC761_SC), 268 _dme(PCI_VENDOR_AMD, PCI_PRODUCT_AMD_SC762_NB), 269 270 _emve(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82441FX), /* QEMU */ 271 _emve(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82443BX), /* VMWare */ 272 }; 273 #undef _dme 274 #undef _dmxe 275 #undef _emve 276 #endif /* __HAVE_PCI_MSI_MSIX */ 277 278 /* 279 * PCI doesn't have any special needs; just use the generic versions 280 * of these functions. 281 */ 282 struct x86_bus_dma_tag pci_bus_dma_tag = { 283 ._tag_needs_free = 0, 284 #if defined(_LP64) || defined(PAE) 285 ._bounce_thresh = PCI32_DMA_BOUNCE_THRESHOLD, 286 ._bounce_alloc_lo = ISA_DMA_BOUNCE_THRESHOLD, 287 ._bounce_alloc_hi = PCI32_DMA_BOUNCE_THRESHOLD, 288 #else 289 ._bounce_thresh = 0, 290 ._bounce_alloc_lo = 0, 291 ._bounce_alloc_hi = 0, 292 #endif 293 ._may_bounce = NULL, 294 }; 295 296 #ifdef _LP64 297 struct x86_bus_dma_tag pci_bus_dma64_tag = { 298 ._tag_needs_free = 0, 299 ._bounce_thresh = 0, 300 ._bounce_alloc_lo = 0, 301 ._bounce_alloc_hi = 0, 302 ._may_bounce = NULL, 303 }; 304 #endif 305 306 static struct pci_conf_lock cl0 = { 307 .cl_cpuno = 0UL 308 , .cl_sel = 0UL 309 }; 310 311 static struct pci_conf_lock * const cl = &cl0; 312 313 #if NGENFB > 0 && NACPICA > 0 && defined(VGA_POST) 314 extern int acpi_md_vbios_reset; 315 extern int acpi_md_vesa_modenum; 316 #endif 317 318 static struct genfb_colormap_callback gfb_cb; 319 static struct genfb_pmf_callback pmf_cb; 320 static struct genfb_mode_callback mode_cb; 321 #ifdef VGA_POST 322 static struct vga_post *vga_posth = NULL; 323 #endif 324 325 static void 326 pci_conf_lock(struct pci_conf_lock *ocl, uint32_t sel) 327 { 328 uint32_t cpuno; 329 330 KASSERT(sel != 0); 331 332 kpreempt_disable(); 333 cpuno = cpu_number() + 1; 334 /* If the kernel enters pci_conf_lock() through an interrupt 335 * handler, then the CPU may already hold the lock. 336 * 337 * If the CPU does not already hold the lock, spin until 338 * we can acquire it. 339 */ 340 if (cpuno == cl->cl_cpuno) { 341 ocl->cl_cpuno = cpuno; 342 } else { 343 #ifdef LOCKDEBUG 344 u_int spins = 0; 345 #endif 346 u_int count; 347 count = SPINLOCK_BACKOFF_MIN; 348 349 ocl->cl_cpuno = 0; 350 351 while (atomic_cas_32(&cl->cl_cpuno, 0, cpuno) != 0) { 352 SPINLOCK_BACKOFF(count); 353 #ifdef LOCKDEBUG 354 if (SPINLOCK_SPINOUT(spins)) { 355 panic("%s: cpu %" PRId32 356 " spun out waiting for cpu %" PRId32, 357 __func__, cpuno, cl->cl_cpuno); 358 } 359 #endif 360 } 361 } 362 363 /* Only one CPU can be here, so an interlocked atomic_swap(3) 364 * is not necessary. 365 * 366 * Evaluating atomic_cas_32_ni()'s argument, cl->cl_sel, 367 * and applying atomic_cas_32_ni() is not an atomic operation, 368 * however, any interrupt that, in the middle of the 369 * operation, modifies cl->cl_sel, will also restore 370 * cl->cl_sel. So cl->cl_sel will have the same value when 371 * we apply atomic_cas_32_ni() as when we evaluated it, 372 * before. 373 */ 374 ocl->cl_sel = atomic_cas_32_ni(&cl->cl_sel, cl->cl_sel, sel); 375 pci_conf_select(sel); 376 } 377 378 static void 379 pci_conf_unlock(struct pci_conf_lock *ocl) 380 { 381 atomic_cas_32_ni(&cl->cl_sel, cl->cl_sel, ocl->cl_sel); 382 pci_conf_select(ocl->cl_sel); 383 if (ocl->cl_cpuno != cl->cl_cpuno) 384 atomic_cas_32(&cl->cl_cpuno, cl->cl_cpuno, ocl->cl_cpuno); 385 kpreempt_enable(); 386 } 387 388 static uint32_t 389 pci_conf_selector(pcitag_t tag, int reg) 390 { 391 static const pcitag_t mode2_mask = { 392 .mode2 = { 393 .enable = 0xff 394 , .forward = 0xff 395 } 396 }; 397 398 switch (pci_mode) { 399 case 1: 400 return tag.mode1 | reg; 401 case 2: 402 return tag.mode1 & mode2_mask.mode1; 403 default: 404 panic("%s: mode %d not configured", __func__, pci_mode); 405 } 406 } 407 408 static unsigned int 409 pci_conf_port(pcitag_t tag, int reg) 410 { 411 switch (pci_mode) { 412 case 1: 413 return PCI_MODE1_DATA_REG; 414 case 2: 415 return tag.mode2.port | reg; 416 default: 417 panic("%s: mode %d not configured", __func__, pci_mode); 418 } 419 } 420 421 static void 422 pci_conf_select(uint32_t sel) 423 { 424 pcitag_t tag; 425 426 switch (pci_mode) { 427 case 1: 428 outl(PCI_MODE1_ADDRESS_REG, sel); 429 return; 430 case 2: 431 tag.mode1 = sel; 432 outb(PCI_MODE2_ENABLE_REG, tag.mode2.enable); 433 if (tag.mode2.enable != 0) 434 outb(PCI_MODE2_FORWARD_REG, tag.mode2.forward); 435 return; 436 default: 437 panic("%s: mode %d not configured", __func__, pci_mode); 438 } 439 } 440 441 static int 442 pci_mode_check(void) 443 { 444 pcireg_t x; 445 pcitag_t t; 446 int device; 447 const int maxdev = pci_bus_maxdevs(NULL, 0); 448 449 for (device = 0; device < maxdev; device++) { 450 t = pci_make_tag(NULL, 0, device, 0); 451 x = pci_conf_read(NULL, t, PCI_CLASS_REG); 452 if (PCI_CLASS(x) == PCI_CLASS_BRIDGE && 453 PCI_SUBCLASS(x) == PCI_SUBCLASS_BRIDGE_HOST) 454 return 0; 455 x = pci_conf_read(NULL, t, PCI_ID_REG); 456 switch (PCI_VENDOR(x)) { 457 case PCI_VENDOR_COMPAQ: 458 case PCI_VENDOR_INTEL: 459 case PCI_VENDOR_VIATECH: 460 return 0; 461 } 462 } 463 return -1; 464 } 465 #ifdef __HAVE_PCI_MSI_MSIX 466 static int 467 pci_has_msi_quirk(pcireg_t id, int type) 468 { 469 int i; 470 471 for (i = 0; i < __arraycount(pci_msi_quirk_tbl); i++) { 472 if (id == pci_msi_quirk_tbl[i].id && 473 type == pci_msi_quirk_tbl[i].type) 474 return 1; 475 } 476 477 return 0; 478 } 479 #endif 480 481 void 482 pci_attach_hook(device_t parent, device_t self, struct pcibus_attach_args *pba) 483 { 484 #ifdef __HAVE_PCI_MSI_MSIX 485 pci_chipset_tag_t pc = pba->pba_pc; 486 pcitag_t tag; 487 pcireg_t id, class; 488 #endif 489 490 if (pba->pba_bus == 0) 491 aprint_normal(": configuration mode %d", pci_mode); 492 #ifdef MPBIOS 493 mpbios_pci_attach_hook(parent, self, pba); 494 #endif 495 #if NACPICA > 0 496 mpacpi_pci_attach_hook(parent, self, pba); 497 #endif 498 #if NACPICA > 0 && !defined(NO_PCI_EXTENDED_CONFIG) 499 acpimcfg_map_bus(self, pba->pba_pc, pba->pba_bus); 500 #endif 501 502 #ifdef __HAVE_PCI_MSI_MSIX 503 /* 504 * In order to decide whether the system supports MSI we look 505 * at the host bridge, which should be device 0 function 0 on 506 * bus 0. It is better to not enable MSI on systems that 507 * support it than the other way around, so be conservative 508 * here. So we don't enable MSI if we don't find a host 509 * bridge there. We also deliberately don't enable MSI on 510 * chipsets from low-end manifacturers like VIA and SiS. 511 */ 512 tag = pci_make_tag(pc, 0, 0, 0); 513 id = pci_conf_read(pc, tag, PCI_ID_REG); 514 class = pci_conf_read(pc, tag, PCI_CLASS_REG); 515 516 if (PCI_CLASS(class) != PCI_CLASS_BRIDGE || 517 PCI_SUBCLASS(class) != PCI_SUBCLASS_BRIDGE_HOST) 518 return; 519 520 /* VMware and KVM use old chipset, but they can use MSI/MSI-X */ 521 if ((cpu_feature[1] & CPUID2_RAZ) 522 && (pci_has_msi_quirk(id, PCI_QUIRK_ENABLE_MSI_VM))) { 523 pba->pba_flags |= PCI_FLAGS_MSI_OKAY; 524 pba->pba_flags |= PCI_FLAGS_MSIX_OKAY; 525 } else if (pci_has_msi_quirk(id, PCI_QUIRK_DISABLE_MSI)) { 526 pba->pba_flags &= ~PCI_FLAGS_MSI_OKAY; 527 pba->pba_flags &= ~PCI_FLAGS_MSIX_OKAY; 528 aprint_verbose("\n"); 529 aprint_verbose_dev(self, 530 "This pci host supports neither MSI nor MSI-X."); 531 } else if (pci_has_msi_quirk(id, PCI_QUIRK_DISABLE_MSIX)) { 532 pba->pba_flags |= PCI_FLAGS_MSI_OKAY; 533 pba->pba_flags &= ~PCI_FLAGS_MSIX_OKAY; 534 aprint_verbose("\n"); 535 aprint_verbose_dev(self, 536 "This pci host does not support MSI-X."); 537 } else { 538 pba->pba_flags |= PCI_FLAGS_MSI_OKAY; 539 pba->pba_flags |= PCI_FLAGS_MSIX_OKAY; 540 } 541 542 /* 543 * Don't enable MSI on a HyperTransport bus. In order to 544 * determine that bus 0 is a HyperTransport bus, we look at 545 * device 24 function 0, which is the HyperTransport 546 * host/primary interface integrated on most 64-bit AMD CPUs. 547 * If that device has a HyperTransport capability, bus 0 must 548 * be a HyperTransport bus and we disable MSI. 549 */ 550 if (24 < pci_bus_maxdevs(pc, 0)) { 551 tag = pci_make_tag(pc, 0, 24, 0); 552 if (pci_get_capability(pc, tag, PCI_CAP_LDT, NULL, NULL)) { 553 pba->pba_flags &= ~PCI_FLAGS_MSI_OKAY; 554 pba->pba_flags &= ~PCI_FLAGS_MSIX_OKAY; 555 } 556 } 557 #endif /* __HAVE_PCI_MSI_MSIX */ 558 } 559 560 int 561 pci_bus_maxdevs(pci_chipset_tag_t pc, int busno) 562 { 563 /* 564 * Bus number is irrelevant. If Configuration Mechanism 2 is in 565 * use, can only have devices 0-15 on any bus. If Configuration 566 * Mechanism 1 is in use, can have devices 0-32 (i.e. the `normal' 567 * range). 568 */ 569 if (pci_mode == 2) 570 return (16); 571 else 572 return (32); 573 } 574 575 pcitag_t 576 pci_make_tag(pci_chipset_tag_t pc, int bus, int device, int function) 577 { 578 pci_chipset_tag_t ipc; 579 pcitag_t tag; 580 581 for (ipc = pc; ipc != NULL; ipc = ipc->pc_super) { 582 if ((ipc->pc_present & PCI_OVERRIDE_MAKE_TAG) == 0) 583 continue; 584 return (*ipc->pc_ov->ov_make_tag)(ipc->pc_ctx, 585 pc, bus, device, function); 586 } 587 588 switch (pci_mode) { 589 case 1: 590 if (bus >= 256 || device >= 32 || function >= 8) 591 panic("%s: bad request(%d, %d, %d)", __func__, 592 bus, device, function); 593 594 tag.mode1 = PCI_MODE1_ENABLE | 595 (bus << 16) | (device << 11) | (function << 8); 596 return tag; 597 case 2: 598 if (bus >= 256 || device >= 16 || function >= 8) 599 panic("%s: bad request(%d, %d, %d)", __func__, 600 bus, device, function); 601 602 tag.mode2.port = 0xc000 | (device << 8); 603 tag.mode2.enable = 0xf0 | (function << 1); 604 tag.mode2.forward = bus; 605 return tag; 606 default: 607 panic("%s: mode %d not configured", __func__, pci_mode); 608 } 609 } 610 611 void 612 pci_decompose_tag(pci_chipset_tag_t pc, pcitag_t tag, 613 int *bp, int *dp, int *fp) 614 { 615 pci_chipset_tag_t ipc; 616 617 for (ipc = pc; ipc != NULL; ipc = ipc->pc_super) { 618 if ((ipc->pc_present & PCI_OVERRIDE_DECOMPOSE_TAG) == 0) 619 continue; 620 (*ipc->pc_ov->ov_decompose_tag)(ipc->pc_ctx, 621 pc, tag, bp, dp, fp); 622 return; 623 } 624 625 switch (pci_mode) { 626 case 1: 627 if (bp != NULL) 628 *bp = (tag.mode1 >> 16) & 0xff; 629 if (dp != NULL) 630 *dp = (tag.mode1 >> 11) & 0x1f; 631 if (fp != NULL) 632 *fp = (tag.mode1 >> 8) & 0x7; 633 return; 634 case 2: 635 if (bp != NULL) 636 *bp = tag.mode2.forward & 0xff; 637 if (dp != NULL) 638 *dp = (tag.mode2.port >> 8) & 0xf; 639 if (fp != NULL) 640 *fp = (tag.mode2.enable >> 1) & 0x7; 641 return; 642 default: 643 panic("%s: mode %d not configured", __func__, pci_mode); 644 } 645 } 646 647 pcireg_t 648 pci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg) 649 { 650 pci_chipset_tag_t ipc; 651 pcireg_t data; 652 struct pci_conf_lock ocl; 653 int dev; 654 655 KASSERT((reg & 0x3) == 0); 656 657 for (ipc = pc; ipc != NULL; ipc = ipc->pc_super) { 658 if ((ipc->pc_present & PCI_OVERRIDE_CONF_READ) == 0) 659 continue; 660 return (*ipc->pc_ov->ov_conf_read)(ipc->pc_ctx, pc, tag, reg); 661 } 662 663 pci_decompose_tag(pc, tag, NULL, &dev, NULL); 664 if (__predict_false(pci_mode == 2 && dev >= 16)) 665 return (pcireg_t) -1; 666 667 if (reg < 0) 668 return (pcireg_t) -1; 669 if (reg >= PCI_CONF_SIZE) { 670 #if NACPICA > 0 && !defined(NO_PCI_EXTENDED_CONFIG) 671 if (reg >= PCI_EXTCONF_SIZE) 672 return (pcireg_t) -1; 673 acpimcfg_conf_read(pc, tag, reg, &data); 674 return data; 675 #else 676 return (pcireg_t) -1; 677 #endif 678 } 679 680 pci_conf_lock(&ocl, pci_conf_selector(tag, reg)); 681 data = inl(pci_conf_port(tag, reg)); 682 pci_conf_unlock(&ocl); 683 return data; 684 } 685 686 void 687 pci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data) 688 { 689 pci_chipset_tag_t ipc; 690 struct pci_conf_lock ocl; 691 int dev; 692 693 KASSERT((reg & 0x3) == 0); 694 695 for (ipc = pc; ipc != NULL; ipc = ipc->pc_super) { 696 if ((ipc->pc_present & PCI_OVERRIDE_CONF_WRITE) == 0) 697 continue; 698 (*ipc->pc_ov->ov_conf_write)(ipc->pc_ctx, pc, tag, reg, 699 data); 700 return; 701 } 702 703 pci_decompose_tag(pc, tag, NULL, &dev, NULL); 704 if (__predict_false(pci_mode == 2 && dev >= 16)) { 705 return; 706 } 707 708 if (reg < 0) 709 return; 710 if (reg >= PCI_CONF_SIZE) { 711 #if NACPICA > 0 && !defined(NO_PCI_EXTENDED_CONFIG) 712 if (reg >= PCI_EXTCONF_SIZE) 713 return; 714 acpimcfg_conf_write(pc, tag, reg, data); 715 #endif 716 return; 717 } 718 719 pci_conf_lock(&ocl, pci_conf_selector(tag, reg)); 720 outl(pci_conf_port(tag, reg), data); 721 pci_conf_unlock(&ocl); 722 } 723 724 void 725 pci_mode_set(int mode) 726 { 727 KASSERT(pci_mode == -1 || pci_mode == mode); 728 729 pci_mode = mode; 730 } 731 732 int 733 pci_mode_detect(void) 734 { 735 uint32_t sav, val; 736 int i; 737 pcireg_t idreg; 738 739 if (pci_mode != -1) 740 return pci_mode; 741 742 /* 743 * We try to divine which configuration mode the host bridge wants. 744 */ 745 746 sav = inl(PCI_MODE1_ADDRESS_REG); 747 748 pci_mode = 1; /* assume this for now */ 749 /* 750 * catch some known buggy implementations of mode 1 751 */ 752 for (i = 0; i < __arraycount(pcim1_quirk_tbl); i++) { 753 pcitag_t t; 754 755 if (PCI_VENDOR(pcim1_quirk_tbl[i].id) == PCI_VENDOR_INVALID) 756 continue; 757 t.mode1 = pcim1_quirk_tbl[i].tag.mode1; 758 idreg = pci_conf_read(NULL, t, PCI_ID_REG); /* needs "pci_mode" */ 759 if (idreg == pcim1_quirk_tbl[i].id) { 760 #ifdef DEBUG 761 printf("%s: known mode 1 PCI chipset (%08x)\n", 762 __func__, idreg); 763 #endif 764 return (pci_mode); 765 } 766 } 767 768 #if 0 769 extern char cpu_brand_string[]; 770 const char *reason, *system_vendor, *system_product; 771 if (memcmp(cpu_brand_string, "QEMU", 4) == 0) 772 /* PR 45671, https://bugs.launchpad.net/qemu/+bug/897771 */ 773 reason = "QEMU"; 774 else if ((system_vendor = pmf_get_platform("system-vendor")) != NULL && 775 strcmp(system_vendor, "Xen") == 0 && 776 (system_product = pmf_get_platform("system-product")) != NULL && 777 strcmp(system_product, "HVM domU") == 0) 778 reason = "Xen"; 779 else 780 reason = NULL; 781 782 if (reason) { 783 #ifdef DEBUG 784 printf("%s: forcing PCI mode 1 for %s\n", __func__, reason); 785 #endif 786 return (pci_mode); 787 } 788 #endif 789 /* 790 * Strong check for standard compliant mode 1: 791 * 1. bit 31 ("enable") can be set 792 * 2. byte/word access does not affect register 793 */ 794 outl(PCI_MODE1_ADDRESS_REG, PCI_MODE1_ENABLE); 795 outb(PCI_MODE1_ADDRESS_REG + 3, 0); 796 outw(PCI_MODE1_ADDRESS_REG + 2, 0); 797 val = inl(PCI_MODE1_ADDRESS_REG); 798 if ((val & 0x80fffffc) != PCI_MODE1_ENABLE) { 799 #ifdef DEBUG 800 printf("%s: mode 1 enable failed (%x)\n", __func__, val); 801 #endif 802 /* Try out mode 1 to see if we can find a host bridge. */ 803 if (pci_mode_check() == 0) { 804 #ifdef DEBUG 805 printf("%s: mode 1 functional, using\n", __func__); 806 #endif 807 return (pci_mode); 808 } 809 goto not1; 810 } 811 outl(PCI_MODE1_ADDRESS_REG, 0); 812 val = inl(PCI_MODE1_ADDRESS_REG); 813 if ((val & 0x80fffffc) != 0) 814 goto not1; 815 return (pci_mode); 816 not1: 817 outl(PCI_MODE1_ADDRESS_REG, sav); 818 819 /* 820 * This mode 2 check is quite weak (and known to give false 821 * positives on some Compaq machines). 822 * However, this doesn't matter, because this is the 823 * last test, and simply no PCI devices will be found if 824 * this happens. 825 */ 826 outb(PCI_MODE2_ENABLE_REG, 0); 827 outb(PCI_MODE2_FORWARD_REG, 0); 828 if (inb(PCI_MODE2_ENABLE_REG) != 0 || 829 inb(PCI_MODE2_FORWARD_REG) != 0) 830 goto not2; 831 return (pci_mode = 2); 832 not2: 833 834 return (pci_mode = 0); 835 } 836 837 void 838 pci_device_foreach(pci_chipset_tag_t pc, int maxbus, 839 void (*func)(pci_chipset_tag_t, pcitag_t, void *), void *context) 840 { 841 pci_device_foreach_min(pc, 0, maxbus, func, context); 842 } 843 844 void 845 pci_device_foreach_min(pci_chipset_tag_t pc, int minbus, int maxbus, 846 void (*func)(pci_chipset_tag_t, pcitag_t, void *), void *context) 847 { 848 const struct pci_quirkdata *qd; 849 int bus, device, function, maxdevs, nfuncs; 850 pcireg_t id, bhlcr; 851 pcitag_t tag; 852 853 for (bus = minbus; bus <= maxbus; bus++) { 854 maxdevs = pci_bus_maxdevs(pc, bus); 855 for (device = 0; device < maxdevs; device++) { 856 tag = pci_make_tag(pc, bus, device, 0); 857 id = pci_conf_read(pc, tag, PCI_ID_REG); 858 859 /* Invalid vendor ID value? */ 860 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 861 continue; 862 /* XXX Not invalid, but we've done this ~forever. */ 863 if (PCI_VENDOR(id) == 0) 864 continue; 865 866 qd = pci_lookup_quirkdata(PCI_VENDOR(id), 867 PCI_PRODUCT(id)); 868 869 bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 870 if (PCI_HDRTYPE_MULTIFN(bhlcr) || 871 (qd != NULL && 872 (qd->quirks & PCI_QUIRK_MULTIFUNCTION) != 0)) 873 nfuncs = 8; 874 else 875 nfuncs = 1; 876 877 for (function = 0; function < nfuncs; function++) { 878 tag = pci_make_tag(pc, bus, device, function); 879 id = pci_conf_read(pc, tag, PCI_ID_REG); 880 881 /* Invalid vendor ID value? */ 882 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 883 continue; 884 /* 885 * XXX Not invalid, but we've done this 886 * ~forever. 887 */ 888 if (PCI_VENDOR(id) == 0) 889 continue; 890 (*func)(pc, tag, context); 891 } 892 } 893 } 894 } 895 896 void 897 pci_bridge_foreach(pci_chipset_tag_t pc, int minbus, int maxbus, 898 void (*func)(pci_chipset_tag_t, pcitag_t, void *), void *ctx) 899 { 900 struct pci_bridge_hook_arg bridge_hook; 901 902 bridge_hook.func = func; 903 bridge_hook.arg = ctx; 904 905 pci_device_foreach_min(pc, minbus, maxbus, pci_bridge_hook, 906 &bridge_hook); 907 } 908 909 static void 910 pci_bridge_hook(pci_chipset_tag_t pc, pcitag_t tag, void *ctx) 911 { 912 struct pci_bridge_hook_arg *bridge_hook = (void *)ctx; 913 pcireg_t reg; 914 915 reg = pci_conf_read(pc, tag, PCI_CLASS_REG); 916 if (PCI_CLASS(reg) == PCI_CLASS_BRIDGE && 917 (PCI_SUBCLASS(reg) == PCI_SUBCLASS_BRIDGE_PCI || 918 PCI_SUBCLASS(reg) == PCI_SUBCLASS_BRIDGE_CARDBUS)) { 919 (*bridge_hook->func)(pc, tag, bridge_hook->arg); 920 } 921 } 922 923 static const void * 924 bit_to_function_pointer(const struct pci_overrides *ov, uint64_t bit) 925 { 926 switch (bit) { 927 case PCI_OVERRIDE_CONF_READ: 928 return ov->ov_conf_read; 929 case PCI_OVERRIDE_CONF_WRITE: 930 return ov->ov_conf_write; 931 case PCI_OVERRIDE_INTR_MAP: 932 return ov->ov_intr_map; 933 case PCI_OVERRIDE_INTR_STRING: 934 return ov->ov_intr_string; 935 case PCI_OVERRIDE_INTR_EVCNT: 936 return ov->ov_intr_evcnt; 937 case PCI_OVERRIDE_INTR_ESTABLISH: 938 return ov->ov_intr_establish; 939 case PCI_OVERRIDE_INTR_DISESTABLISH: 940 return ov->ov_intr_disestablish; 941 case PCI_OVERRIDE_MAKE_TAG: 942 return ov->ov_make_tag; 943 case PCI_OVERRIDE_DECOMPOSE_TAG: 944 return ov->ov_decompose_tag; 945 default: 946 return NULL; 947 } 948 } 949 950 void 951 pci_chipset_tag_destroy(pci_chipset_tag_t pc) 952 { 953 kmem_free(pc, sizeof(struct pci_chipset_tag)); 954 } 955 956 int 957 pci_chipset_tag_create(pci_chipset_tag_t opc, const uint64_t present, 958 const struct pci_overrides *ov, void *ctx, pci_chipset_tag_t *pcp) 959 { 960 uint64_t bit, bits, nbits; 961 pci_chipset_tag_t pc; 962 const void *fp; 963 964 if (ov == NULL || present == 0) 965 return EINVAL; 966 967 pc = kmem_alloc(sizeof(struct pci_chipset_tag), KM_SLEEP); 968 pc->pc_super = opc; 969 970 for (bits = present; bits != 0; bits = nbits) { 971 nbits = bits & (bits - 1); 972 bit = nbits ^ bits; 973 if ((fp = bit_to_function_pointer(ov, bit)) == NULL) { 974 #ifdef DEBUG 975 printf("%s: missing bit %" PRIx64 "\n", __func__, bit); 976 #endif 977 goto einval; 978 } 979 } 980 981 pc->pc_ov = ov; 982 pc->pc_present = present; 983 pc->pc_ctx = ctx; 984 985 *pcp = pc; 986 987 return 0; 988 einval: 989 kmem_free(pc, sizeof(struct pci_chipset_tag)); 990 return EINVAL; 991 } 992 993 static void 994 x86_genfb_set_mapreg(void *opaque, int index, int r, int g, int b) 995 { 996 outb(IO_VGA + VGA_DAC_ADDRW, index); 997 outb(IO_VGA + VGA_DAC_PALETTE, (uint8_t)r >> 2); 998 outb(IO_VGA + VGA_DAC_PALETTE, (uint8_t)g >> 2); 999 outb(IO_VGA + VGA_DAC_PALETTE, (uint8_t)b >> 2); 1000 } 1001 1002 static bool 1003 x86_genfb_setmode(struct genfb_softc *sc, int newmode) 1004 { 1005 #if NGENFB > 0 1006 # if NACPICA > 0 && defined(VGA_POST) 1007 static int curmode = WSDISPLAYIO_MODE_EMUL; 1008 # endif 1009 1010 switch (newmode) { 1011 case WSDISPLAYIO_MODE_EMUL: 1012 x86_genfb_mtrr_init(sc->sc_fboffset, 1013 sc->sc_height * sc->sc_stride); 1014 # if NACPICA > 0 && defined(VGA_POST) 1015 if (curmode != newmode) { 1016 if (vga_posth != NULL && acpi_md_vesa_modenum != 0) { 1017 vga_post_set_vbe(vga_posth, 1018 acpi_md_vesa_modenum); 1019 } 1020 } 1021 # endif 1022 break; 1023 } 1024 1025 # if NACPICA > 0 && defined(VGA_POST) 1026 curmode = newmode; 1027 # endif 1028 #endif 1029 return true; 1030 } 1031 1032 static bool 1033 x86_genfb_suspend(device_t dev, const pmf_qual_t *qual) 1034 { 1035 return true; 1036 } 1037 1038 static bool 1039 x86_genfb_resume(device_t dev, const pmf_qual_t *qual) 1040 { 1041 #if NGENFB > 0 1042 struct pci_genfb_softc *psc = device_private(dev); 1043 1044 #if NACPICA > 0 && defined(VGA_POST) 1045 if (vga_posth != NULL && acpi_md_vbios_reset == 2) { 1046 vga_post_call(vga_posth); 1047 if (acpi_md_vesa_modenum != 0) 1048 vga_post_set_vbe(vga_posth, acpi_md_vesa_modenum); 1049 } 1050 #endif 1051 genfb_restore_palette(&psc->sc_gen); 1052 #endif 1053 1054 return true; 1055 } 1056 1057 device_t 1058 device_pci_register(device_t dev, void *aux) 1059 { 1060 static bool found_console = false; 1061 device_t parent = device_parent(dev); 1062 1063 device_pci_props_register(dev, aux); 1064 1065 /* 1066 * Handle network interfaces here, the attachment information is 1067 * not available driver-independently later. 1068 * 1069 * For disks, there is nothing useful available at attach time. 1070 */ 1071 if (device_class(dev) == DV_IFNET) { 1072 struct btinfo_netif *bin = lookup_bootinfo(BTINFO_NETIF); 1073 if (bin == NULL) 1074 return NULL; 1075 1076 /* 1077 * We don't check the driver name against the device name 1078 * passed by the boot ROM. The ROM should stay usable if 1079 * the driver becomes obsolete. The physical attachment 1080 * information (checked below) must be sufficient to 1081 * identify the device. 1082 */ 1083 if (bin->bus == BI_BUS_PCI && device_is_a(parent, "pci")) { 1084 struct pci_attach_args *paa = aux; 1085 int b, d, f; 1086 1087 /* 1088 * Calculate BIOS representation of: 1089 * 1090 * <bus,device,function> 1091 * 1092 * and compare. 1093 */ 1094 pci_decompose_tag(paa->pa_pc, paa->pa_tag, &b, &d, &f); 1095 if (bin->addr.tag == ((b << 8) | (d << 3) | f)) 1096 return dev; 1097 1098 #ifndef XEN 1099 /* 1100 * efiboot reports parent ppb bus/device/function. 1101 */ 1102 device_t grand = device_parent(parent); 1103 if (efi_probe() && grand && device_is_a(grand, "ppb")) { 1104 struct ppb_softc *ppb_sc = device_private(grand); 1105 pci_decompose_tag(ppb_sc->sc_pc, ppb_sc->sc_tag, 1106 &b, &d, &f); 1107 if (bin->addr.tag == ((b << 8) | (d << 3) | f)) 1108 return dev; 1109 } 1110 #endif 1111 } 1112 } 1113 if (parent && device_is_a(parent, "pci") && 1114 found_console == false) { 1115 struct btinfo_framebuffer *fbinfo; 1116 struct pci_attach_args *pa = aux; 1117 prop_dictionary_t dict; 1118 1119 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_DISPLAY) { 1120 #if NWSDISPLAY > 0 && NGENFB > 0 1121 extern struct vcons_screen x86_genfb_console_screen; 1122 struct rasops_info *ri; 1123 1124 ri = &x86_genfb_console_screen.scr_ri; 1125 #endif 1126 1127 fbinfo = lookup_bootinfo(BTINFO_FRAMEBUFFER); 1128 dict = device_properties(dev); 1129 /* 1130 * framebuffer drivers other than genfb can work 1131 * without the address property 1132 */ 1133 if (fbinfo != NULL) { 1134 if (fbinfo->physaddr != 0) { 1135 prop_dictionary_set_uint32(dict, "width", 1136 fbinfo->width); 1137 prop_dictionary_set_uint32(dict, "height", 1138 fbinfo->height); 1139 prop_dictionary_set_uint8(dict, "depth", 1140 fbinfo->depth); 1141 prop_dictionary_set_uint16(dict, "linebytes", 1142 fbinfo->stride); 1143 1144 prop_dictionary_set_uint64(dict, "address", 1145 fbinfo->physaddr); 1146 #if NWSDISPLAY > 0 && NGENFB > 0 1147 if (ri->ri_bits != NULL) { 1148 prop_dictionary_set_uint64(dict, 1149 "virtual_address", 1150 ri->ri_hwbits != NULL ? 1151 (vaddr_t)ri->ri_hworigbits : 1152 (vaddr_t)ri->ri_origbits); 1153 } 1154 #endif 1155 } 1156 #if notyet 1157 prop_dictionary_set_bool(dict, "splash", 1158 fbinfo->flags & BI_FB_SPLASH ? 1159 true : false); 1160 #endif 1161 if (fbinfo->depth == 8) { 1162 gfb_cb.gcc_cookie = NULL; 1163 gfb_cb.gcc_set_mapreg = 1164 x86_genfb_set_mapreg; 1165 prop_dictionary_set_uint64(dict, 1166 "cmap_callback", 1167 (uint64_t)(uintptr_t)&gfb_cb); 1168 } 1169 if (fbinfo->physaddr != 0) { 1170 mode_cb.gmc_setmode = x86_genfb_setmode; 1171 prop_dictionary_set_uint64(dict, 1172 "mode_callback", 1173 (uint64_t)(uintptr_t)&mode_cb); 1174 } 1175 1176 #if NWSDISPLAY > 0 && NGENFB > 0 1177 if (device_is_a(dev, "genfb")) { 1178 prop_dictionary_set_bool(dict, 1179 "enable_shadowfb", 1180 ri->ri_hwbits != NULL ? 1181 true : false); 1182 1183 x86_genfb_set_console_dev(dev); 1184 #ifdef DDB 1185 db_trap_callback = 1186 x86_genfb_ddb_trap_callback; 1187 #endif 1188 } 1189 #endif 1190 } 1191 #if 1 && NWSDISPLAY > 0 && NGENFB > 0 1192 /* XXX */ 1193 if (device_is_a(dev, "genfb")) { 1194 prop_dictionary_set_bool(dict, "is_console", 1195 genfb_is_console()); 1196 } else 1197 #endif 1198 prop_dictionary_set_bool(dict, "is_console", true); 1199 1200 prop_dictionary_set_bool(dict, "clear-screen", false); 1201 #if NWSDISPLAY > 0 && NGENFB > 0 1202 prop_dictionary_set_uint16(dict, "cursor-row", 1203 x86_genfb_console_screen.scr_ri.ri_crow); 1204 #endif 1205 #if notyet 1206 prop_dictionary_set_bool(dict, "splash", 1207 fbinfo->flags & BI_FB_SPLASH ? true : false); 1208 #endif 1209 pmf_cb.gpc_suspend = x86_genfb_suspend; 1210 pmf_cb.gpc_resume = x86_genfb_resume; 1211 prop_dictionary_set_uint64(dict, 1212 "pmf_callback", (uint64_t)(uintptr_t)&pmf_cb); 1213 #ifdef VGA_POST 1214 vga_posth = vga_post_init(pa->pa_bus, pa->pa_device, 1215 pa->pa_function); 1216 #endif 1217 found_console = true; 1218 return NULL; 1219 } 1220 } 1221 return NULL; 1222 } 1223 1224 #ifndef PUC_CNBUS 1225 #define PUC_CNBUS 0 1226 #endif 1227 1228 #if NCOM > 0 1229 int 1230 cpu_puc_cnprobe(struct consdev *cn, struct pci_attach_args *pa) 1231 { 1232 pci_mode_detect(); 1233 pa->pa_iot = x86_bus_space_io; 1234 pa->pa_memt = x86_bus_space_mem; 1235 pa->pa_pc = 0; 1236 pa->pa_tag = pci_make_tag(0, PUC_CNBUS, pci_bus_maxdevs(NULL, 0) - 1, 1237 0); 1238 1239 return 0; 1240 } 1241 #endif 1242