1 /* $NetBSD: pci_machdep.c,v 1.63 2013/12/25 17:24:39 jakllsch Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved. 35 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 1. Redistributions of source code must retain the above copyright 41 * notice, this list of conditions and the following disclaimer. 42 * 2. Redistributions in binary form must reproduce the above copyright 43 * notice, this list of conditions and the following disclaimer in the 44 * documentation and/or other materials provided with the distribution. 45 * 3. All advertising materials mentioning features or use of this software 46 * must display the following acknowledgement: 47 * This product includes software developed by Charles M. Hannum. 48 * 4. The name of the author may not be used to endorse or promote products 49 * derived from this software without specific prior written permission. 50 * 51 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 52 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 53 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 54 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 55 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 56 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 57 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 58 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 59 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 60 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 61 */ 62 63 /* 64 * Machine-specific functions for PCI autoconfiguration. 65 * 66 * On PCs, there are two methods of generating PCI configuration cycles. 67 * We try to detect the appropriate mechanism for this machine and set 68 * up a few function pointers to access the correct method directly. 69 * 70 * The configuration method can be hard-coded in the config file by 71 * using `options PCI_CONF_MODE=N', where `N' is the configuration mode 72 * as defined in section 3.6.4.1, `Generating Configuration Cycles'. 73 */ 74 75 #include <sys/cdefs.h> 76 __KERNEL_RCSID(0, "$NetBSD: pci_machdep.c,v 1.63 2013/12/25 17:24:39 jakllsch Exp $"); 77 78 #include <sys/types.h> 79 #include <sys/param.h> 80 #include <sys/time.h> 81 #include <sys/systm.h> 82 #include <sys/errno.h> 83 #include <sys/device.h> 84 #include <sys/bus.h> 85 #include <sys/cpu.h> 86 #include <sys/kmem.h> 87 88 #include <uvm/uvm_extern.h> 89 90 #include <machine/bus_private.h> 91 92 #include <machine/pio.h> 93 #include <machine/lock.h> 94 95 #include <dev/isa/isareg.h> 96 #include <dev/isa/isavar.h> 97 #include <dev/pci/pcivar.h> 98 #include <dev/pci/pcireg.h> 99 #include <dev/pci/pccbbreg.h> 100 #include <dev/pci/pcidevs.h> 101 #include <dev/pci/genfb_pcivar.h> 102 103 #include <dev/wsfb/genfbvar.h> 104 #include <arch/x86/include/genfb_machdep.h> 105 #include <dev/ic/vgareg.h> 106 107 #include "acpica.h" 108 #include "genfb.h" 109 #include "isa.h" 110 #include "opt_acpi.h" 111 #include "opt_ddb.h" 112 #include "opt_mpbios.h" 113 #include "opt_vga.h" 114 #include "pci.h" 115 #include "wsdisplay.h" 116 #include "com.h" 117 118 #ifdef DDB 119 #include <machine/db_machdep.h> 120 #include <ddb/db_sym.h> 121 #include <ddb/db_extern.h> 122 #endif 123 124 #ifdef VGA_POST 125 #include <x86/vga_post.h> 126 #endif 127 128 #include <machine/autoconf.h> 129 #include <machine/bootinfo.h> 130 131 #ifdef MPBIOS 132 #include <machine/mpbiosvar.h> 133 #endif 134 135 #if NACPICA > 0 136 #include <machine/mpacpi.h> 137 #endif 138 139 #include <machine/mpconfig.h> 140 141 #if NCOM > 0 142 #include <dev/pci/puccn.h> 143 #endif 144 145 #include "opt_pci_conf_mode.h" 146 147 #ifdef PCI_CONF_MODE 148 #if (PCI_CONF_MODE == 1) || (PCI_CONF_MODE == 2) 149 static int pci_mode = PCI_CONF_MODE; 150 #else 151 #error Invalid PCI configuration mode. 152 #endif 153 #else 154 static int pci_mode = -1; 155 #endif 156 157 struct pci_conf_lock { 158 uint32_t cl_cpuno; /* 0: unlocked 159 * 1 + n: locked by CPU n (0 <= n) 160 */ 161 uint32_t cl_sel; /* the address that's being read. */ 162 }; 163 164 static void pci_conf_unlock(struct pci_conf_lock *); 165 static uint32_t pci_conf_selector(pcitag_t, int); 166 static unsigned int pci_conf_port(pcitag_t, int); 167 static void pci_conf_select(uint32_t); 168 static void pci_conf_lock(struct pci_conf_lock *, uint32_t); 169 static void pci_bridge_hook(pci_chipset_tag_t, pcitag_t, void *); 170 struct pci_bridge_hook_arg { 171 void (*func)(pci_chipset_tag_t, pcitag_t, void *); 172 void *arg; 173 }; 174 175 #define PCI_MODE1_ENABLE 0x80000000UL 176 #define PCI_MODE1_ADDRESS_REG 0x0cf8 177 #define PCI_MODE1_DATA_REG 0x0cfc 178 179 #define PCI_MODE2_ENABLE_REG 0x0cf8 180 #define PCI_MODE2_FORWARD_REG 0x0cfa 181 182 #define _tag(b, d, f) \ 183 {.mode1 = PCI_MODE1_ENABLE | ((b) << 16) | ((d) << 11) | ((f) << 8)} 184 #define _qe(bus, dev, fcn, vend, prod) \ 185 {_tag(bus, dev, fcn), PCI_ID_CODE(vend, prod)} 186 const struct { 187 pcitag_t tag; 188 pcireg_t id; 189 } pcim1_quirk_tbl[] = { 190 _qe(0, 0, 0, PCI_VENDOR_INVALID, 0x0000), /* patchable */ 191 _qe(0, 0, 0, PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_TRIFLEX1), 192 /* XXX Triflex2 not tested */ 193 _qe(0, 0, 0, PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_TRIFLEX2), 194 _qe(0, 0, 0, PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_TRIFLEX4), 195 /* Triton needed for Connectix Virtual PC */ 196 _qe(0, 0, 0, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82437FX), 197 /* Connectix Virtual PC 5 has a 440BX */ 198 _qe(0, 0, 0, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82443BX_NOAGP), 199 /* Parallels Desktop for Mac */ 200 _qe(0, 2, 0, PCI_VENDOR_PARALLELS, PCI_PRODUCT_PARALLELS_VIDEO), 201 _qe(0, 3, 0, PCI_VENDOR_PARALLELS, PCI_PRODUCT_PARALLELS_TOOLS), 202 /* SIS 740 */ 203 _qe(0, 0, 0, PCI_VENDOR_SIS, PCI_PRODUCT_SIS_740), 204 /* SIS 741 */ 205 _qe(0, 0, 0, PCI_VENDOR_SIS, PCI_PRODUCT_SIS_741), 206 /* VIA Technologies VX900 */ 207 _qe(0, 0, 0, PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VX900_HB) 208 }; 209 #undef _tag 210 #undef _qe 211 212 /* 213 * PCI doesn't have any special needs; just use the generic versions 214 * of these functions. 215 */ 216 struct x86_bus_dma_tag pci_bus_dma_tag = { 217 ._tag_needs_free = 0, 218 #if defined(_LP64) || defined(PAE) 219 ._bounce_thresh = PCI32_DMA_BOUNCE_THRESHOLD, 220 ._bounce_alloc_lo = ISA_DMA_BOUNCE_THRESHOLD, 221 ._bounce_alloc_hi = PCI32_DMA_BOUNCE_THRESHOLD, 222 #else 223 ._bounce_thresh = 0, 224 ._bounce_alloc_lo = 0, 225 ._bounce_alloc_hi = 0, 226 #endif 227 ._may_bounce = NULL, 228 }; 229 230 #ifdef _LP64 231 struct x86_bus_dma_tag pci_bus_dma64_tag = { 232 ._tag_needs_free = 0, 233 ._bounce_thresh = 0, 234 ._bounce_alloc_lo = 0, 235 ._bounce_alloc_hi = 0, 236 ._may_bounce = NULL, 237 }; 238 #endif 239 240 static struct pci_conf_lock cl0 = { 241 .cl_cpuno = 0UL 242 , .cl_sel = 0UL 243 }; 244 245 static struct pci_conf_lock * const cl = &cl0; 246 247 #if NGENFB > 0 && NACPICA > 0 && defined(VGA_POST) 248 extern int acpi_md_vbios_reset; 249 extern int acpi_md_vesa_modenum; 250 #endif 251 252 static struct genfb_colormap_callback gfb_cb; 253 static struct genfb_pmf_callback pmf_cb; 254 static struct genfb_mode_callback mode_cb; 255 #ifdef VGA_POST 256 static struct vga_post *vga_posth = NULL; 257 #endif 258 259 static void 260 pci_conf_lock(struct pci_conf_lock *ocl, uint32_t sel) 261 { 262 uint32_t cpuno; 263 264 KASSERT(sel != 0); 265 266 kpreempt_disable(); 267 cpuno = cpu_number() + 1; 268 /* If the kernel enters pci_conf_lock() through an interrupt 269 * handler, then the CPU may already hold the lock. 270 * 271 * If the CPU does not already hold the lock, spin until 272 * we can acquire it. 273 */ 274 if (cpuno == cl->cl_cpuno) { 275 ocl->cl_cpuno = cpuno; 276 } else { 277 u_int spins; 278 279 ocl->cl_cpuno = 0; 280 281 spins = SPINLOCK_BACKOFF_MIN; 282 while (atomic_cas_32(&cl->cl_cpuno, 0, cpuno) != 0) { 283 SPINLOCK_BACKOFF(spins); 284 #ifdef LOCKDEBUG 285 if (SPINLOCK_SPINOUT(spins)) { 286 panic("%s: cpu %" PRId32 287 " spun out waiting for cpu %" PRId32, 288 __func__, cpuno, cl->cl_cpuno); 289 } 290 #endif /* LOCKDEBUG */ 291 } 292 } 293 294 /* Only one CPU can be here, so an interlocked atomic_swap(3) 295 * is not necessary. 296 * 297 * Evaluating atomic_cas_32_ni()'s argument, cl->cl_sel, 298 * and applying atomic_cas_32_ni() is not an atomic operation, 299 * however, any interrupt that, in the middle of the 300 * operation, modifies cl->cl_sel, will also restore 301 * cl->cl_sel. So cl->cl_sel will have the same value when 302 * we apply atomic_cas_32_ni() as when we evaluated it, 303 * before. 304 */ 305 ocl->cl_sel = atomic_cas_32_ni(&cl->cl_sel, cl->cl_sel, sel); 306 pci_conf_select(sel); 307 } 308 309 static void 310 pci_conf_unlock(struct pci_conf_lock *ocl) 311 { 312 atomic_cas_32_ni(&cl->cl_sel, cl->cl_sel, ocl->cl_sel); 313 pci_conf_select(ocl->cl_sel); 314 if (ocl->cl_cpuno != cl->cl_cpuno) 315 atomic_cas_32(&cl->cl_cpuno, cl->cl_cpuno, ocl->cl_cpuno); 316 kpreempt_enable(); 317 } 318 319 static uint32_t 320 pci_conf_selector(pcitag_t tag, int reg) 321 { 322 static const pcitag_t mode2_mask = { 323 .mode2 = { 324 .enable = 0xff 325 , .forward = 0xff 326 } 327 }; 328 329 switch (pci_mode) { 330 case 1: 331 return tag.mode1 | reg; 332 case 2: 333 return tag.mode1 & mode2_mask.mode1; 334 default: 335 panic("%s: mode not configured", __func__); 336 } 337 } 338 339 static unsigned int 340 pci_conf_port(pcitag_t tag, int reg) 341 { 342 switch (pci_mode) { 343 case 1: 344 return PCI_MODE1_DATA_REG; 345 case 2: 346 return tag.mode2.port | reg; 347 default: 348 panic("%s: mode not configured", __func__); 349 } 350 } 351 352 static void 353 pci_conf_select(uint32_t sel) 354 { 355 pcitag_t tag; 356 357 switch (pci_mode) { 358 case 1: 359 outl(PCI_MODE1_ADDRESS_REG, sel); 360 return; 361 case 2: 362 tag.mode1 = sel; 363 outb(PCI_MODE2_ENABLE_REG, tag.mode2.enable); 364 if (tag.mode2.enable != 0) 365 outb(PCI_MODE2_FORWARD_REG, tag.mode2.forward); 366 return; 367 default: 368 panic("%s: mode not configured", __func__); 369 } 370 } 371 372 void 373 pci_attach_hook(device_t parent, device_t self, struct pcibus_attach_args *pba) 374 { 375 376 if (pba->pba_bus == 0) 377 aprint_normal(": configuration mode %d", pci_mode); 378 #ifdef MPBIOS 379 mpbios_pci_attach_hook(parent, self, pba); 380 #endif 381 #if NACPICA > 0 382 mpacpi_pci_attach_hook(parent, self, pba); 383 #endif 384 } 385 386 int 387 pci_bus_maxdevs(pci_chipset_tag_t pc, int busno) 388 { 389 /* 390 * Bus number is irrelevant. If Configuration Mechanism 2 is in 391 * use, can only have devices 0-15 on any bus. If Configuration 392 * Mechanism 1 is in use, can have devices 0-32 (i.e. the `normal' 393 * range). 394 */ 395 if (pci_mode == 2) 396 return (16); 397 else 398 return (32); 399 } 400 401 pcitag_t 402 pci_make_tag(pci_chipset_tag_t pc, int bus, int device, int function) 403 { 404 pci_chipset_tag_t ipc; 405 pcitag_t tag; 406 407 for (ipc = pc; ipc != NULL; ipc = ipc->pc_super) { 408 if ((ipc->pc_present & PCI_OVERRIDE_MAKE_TAG) == 0) 409 continue; 410 return (*ipc->pc_ov->ov_make_tag)(ipc->pc_ctx, 411 pc, bus, device, function); 412 } 413 414 switch (pci_mode) { 415 case 1: 416 if (bus >= 256 || device >= 32 || function >= 8) 417 panic("%s: bad request", __func__); 418 419 tag.mode1 = PCI_MODE1_ENABLE | 420 (bus << 16) | (device << 11) | (function << 8); 421 return tag; 422 case 2: 423 if (bus >= 256 || device >= 16 || function >= 8) 424 panic("%s: bad request", __func__); 425 426 tag.mode2.port = 0xc000 | (device << 8); 427 tag.mode2.enable = 0xf0 | (function << 1); 428 tag.mode2.forward = bus; 429 return tag; 430 default: 431 panic("%s: mode not configured", __func__); 432 } 433 } 434 435 void 436 pci_decompose_tag(pci_chipset_tag_t pc, pcitag_t tag, 437 int *bp, int *dp, int *fp) 438 { 439 pci_chipset_tag_t ipc; 440 441 for (ipc = pc; ipc != NULL; ipc = ipc->pc_super) { 442 if ((ipc->pc_present & PCI_OVERRIDE_DECOMPOSE_TAG) == 0) 443 continue; 444 (*ipc->pc_ov->ov_decompose_tag)(ipc->pc_ctx, 445 pc, tag, bp, dp, fp); 446 return; 447 } 448 449 switch (pci_mode) { 450 case 1: 451 if (bp != NULL) 452 *bp = (tag.mode1 >> 16) & 0xff; 453 if (dp != NULL) 454 *dp = (tag.mode1 >> 11) & 0x1f; 455 if (fp != NULL) 456 *fp = (tag.mode1 >> 8) & 0x7; 457 return; 458 case 2: 459 if (bp != NULL) 460 *bp = tag.mode2.forward & 0xff; 461 if (dp != NULL) 462 *dp = (tag.mode2.port >> 8) & 0xf; 463 if (fp != NULL) 464 *fp = (tag.mode2.enable >> 1) & 0x7; 465 return; 466 default: 467 panic("%s: mode not configured", __func__); 468 } 469 } 470 471 pcireg_t 472 pci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg) 473 { 474 pci_chipset_tag_t ipc; 475 pcireg_t data; 476 struct pci_conf_lock ocl; 477 478 KASSERT((reg & 0x3) == 0); 479 480 for (ipc = pc; ipc != NULL; ipc = ipc->pc_super) { 481 if ((ipc->pc_present & PCI_OVERRIDE_CONF_READ) == 0) 482 continue; 483 return (*ipc->pc_ov->ov_conf_read)(ipc->pc_ctx, pc, tag, reg); 484 } 485 486 pci_conf_lock(&ocl, pci_conf_selector(tag, reg)); 487 data = inl(pci_conf_port(tag, reg)); 488 pci_conf_unlock(&ocl); 489 return data; 490 } 491 492 void 493 pci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data) 494 { 495 pci_chipset_tag_t ipc; 496 struct pci_conf_lock ocl; 497 498 KASSERT((reg & 0x3) == 0); 499 500 for (ipc = pc; ipc != NULL; ipc = ipc->pc_super) { 501 if ((ipc->pc_present & PCI_OVERRIDE_CONF_WRITE) == 0) 502 continue; 503 (*ipc->pc_ov->ov_conf_write)(ipc->pc_ctx, pc, tag, reg, 504 data); 505 return; 506 } 507 508 pci_conf_lock(&ocl, pci_conf_selector(tag, reg)); 509 outl(pci_conf_port(tag, reg), data); 510 pci_conf_unlock(&ocl); 511 } 512 513 void 514 pci_mode_set(int mode) 515 { 516 KASSERT(pci_mode == -1 || pci_mode == mode); 517 518 pci_mode = mode; 519 } 520 521 int 522 pci_mode_detect(void) 523 { 524 uint32_t sav, val; 525 int i; 526 pcireg_t idreg; 527 extern char cpu_brand_string[]; 528 529 if (pci_mode != -1) 530 return pci_mode; 531 532 /* 533 * We try to divine which configuration mode the host bridge wants. 534 */ 535 536 sav = inl(PCI_MODE1_ADDRESS_REG); 537 538 pci_mode = 1; /* assume this for now */ 539 /* 540 * catch some known buggy implementations of mode 1 541 */ 542 for (i = 0; i < __arraycount(pcim1_quirk_tbl); i++) { 543 pcitag_t t; 544 545 if (PCI_VENDOR(pcim1_quirk_tbl[i].id) == PCI_VENDOR_INVALID) 546 continue; 547 t.mode1 = pcim1_quirk_tbl[i].tag.mode1; 548 idreg = pci_conf_read(NULL, t, PCI_ID_REG); /* needs "pci_mode" */ 549 if (idreg == pcim1_quirk_tbl[i].id) { 550 #ifdef DEBUG 551 printf("known mode 1 PCI chipset (%08x)\n", 552 idreg); 553 #endif 554 return (pci_mode); 555 } 556 } 557 if (memcmp(cpu_brand_string, "QEMU", 4) == 0) { 558 /* PR 45671, https://bugs.launchpad.net/qemu/+bug/897771 */ 559 #ifdef DEBUG 560 printf("forcing PCI mode 1 for QEMU\n"); 561 #endif 562 return (pci_mode); 563 } 564 565 /* 566 * Strong check for standard compliant mode 1: 567 * 1. bit 31 ("enable") can be set 568 * 2. byte/word access does not affect register 569 */ 570 outl(PCI_MODE1_ADDRESS_REG, PCI_MODE1_ENABLE); 571 outb(PCI_MODE1_ADDRESS_REG + 3, 0); 572 outw(PCI_MODE1_ADDRESS_REG + 2, 0); 573 val = inl(PCI_MODE1_ADDRESS_REG); 574 if ((val & 0x80fffffc) != PCI_MODE1_ENABLE) { 575 #ifdef DEBUG 576 printf("pci_mode_detect: mode 1 enable failed (%x)\n", 577 val); 578 #endif 579 goto not1; 580 } 581 outl(PCI_MODE1_ADDRESS_REG, 0); 582 val = inl(PCI_MODE1_ADDRESS_REG); 583 if ((val & 0x80fffffc) != 0) 584 goto not1; 585 return (pci_mode); 586 not1: 587 outl(PCI_MODE1_ADDRESS_REG, sav); 588 589 /* 590 * This mode 2 check is quite weak (and known to give false 591 * positives on some Compaq machines). 592 * However, this doesn't matter, because this is the 593 * last test, and simply no PCI devices will be found if 594 * this happens. 595 */ 596 outb(PCI_MODE2_ENABLE_REG, 0); 597 outb(PCI_MODE2_FORWARD_REG, 0); 598 if (inb(PCI_MODE2_ENABLE_REG) != 0 || 599 inb(PCI_MODE2_FORWARD_REG) != 0) 600 goto not2; 601 return (pci_mode = 2); 602 not2: 603 604 return (pci_mode = 0); 605 } 606 607 void 608 pci_device_foreach(pci_chipset_tag_t pc, int maxbus, 609 void (*func)(pci_chipset_tag_t, pcitag_t, void *), void *context) 610 { 611 pci_device_foreach_min(pc, 0, maxbus, func, context); 612 } 613 614 void 615 pci_device_foreach_min(pci_chipset_tag_t pc, int minbus, int maxbus, 616 void (*func)(pci_chipset_tag_t, pcitag_t, void *), void *context) 617 { 618 const struct pci_quirkdata *qd; 619 int bus, device, function, maxdevs, nfuncs; 620 pcireg_t id, bhlcr; 621 pcitag_t tag; 622 623 for (bus = minbus; bus <= maxbus; bus++) { 624 maxdevs = pci_bus_maxdevs(pc, bus); 625 for (device = 0; device < maxdevs; device++) { 626 tag = pci_make_tag(pc, bus, device, 0); 627 id = pci_conf_read(pc, tag, PCI_ID_REG); 628 629 /* Invalid vendor ID value? */ 630 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 631 continue; 632 /* XXX Not invalid, but we've done this ~forever. */ 633 if (PCI_VENDOR(id) == 0) 634 continue; 635 636 qd = pci_lookup_quirkdata(PCI_VENDOR(id), 637 PCI_PRODUCT(id)); 638 639 bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 640 if (PCI_HDRTYPE_MULTIFN(bhlcr) || 641 (qd != NULL && 642 (qd->quirks & PCI_QUIRK_MULTIFUNCTION) != 0)) 643 nfuncs = 8; 644 else 645 nfuncs = 1; 646 647 for (function = 0; function < nfuncs; function++) { 648 tag = pci_make_tag(pc, bus, device, function); 649 id = pci_conf_read(pc, tag, PCI_ID_REG); 650 651 /* Invalid vendor ID value? */ 652 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 653 continue; 654 /* 655 * XXX Not invalid, but we've done this 656 * ~forever. 657 */ 658 if (PCI_VENDOR(id) == 0) 659 continue; 660 (*func)(pc, tag, context); 661 } 662 } 663 } 664 } 665 666 void 667 pci_bridge_foreach(pci_chipset_tag_t pc, int minbus, int maxbus, 668 void (*func)(pci_chipset_tag_t, pcitag_t, void *), void *ctx) 669 { 670 struct pci_bridge_hook_arg bridge_hook; 671 672 bridge_hook.func = func; 673 bridge_hook.arg = ctx; 674 675 pci_device_foreach_min(pc, minbus, maxbus, pci_bridge_hook, 676 &bridge_hook); 677 } 678 679 static void 680 pci_bridge_hook(pci_chipset_tag_t pc, pcitag_t tag, void *ctx) 681 { 682 struct pci_bridge_hook_arg *bridge_hook = (void *)ctx; 683 pcireg_t reg; 684 685 reg = pci_conf_read(pc, tag, PCI_CLASS_REG); 686 if (PCI_CLASS(reg) == PCI_CLASS_BRIDGE && 687 (PCI_SUBCLASS(reg) == PCI_SUBCLASS_BRIDGE_PCI || 688 PCI_SUBCLASS(reg) == PCI_SUBCLASS_BRIDGE_CARDBUS)) { 689 (*bridge_hook->func)(pc, tag, bridge_hook->arg); 690 } 691 } 692 693 static const void * 694 bit_to_function_pointer(const struct pci_overrides *ov, uint64_t bit) 695 { 696 switch (bit) { 697 case PCI_OVERRIDE_CONF_READ: 698 return ov->ov_conf_read; 699 case PCI_OVERRIDE_CONF_WRITE: 700 return ov->ov_conf_write; 701 case PCI_OVERRIDE_INTR_MAP: 702 return ov->ov_intr_map; 703 case PCI_OVERRIDE_INTR_STRING: 704 return ov->ov_intr_string; 705 case PCI_OVERRIDE_INTR_EVCNT: 706 return ov->ov_intr_evcnt; 707 case PCI_OVERRIDE_INTR_ESTABLISH: 708 return ov->ov_intr_establish; 709 case PCI_OVERRIDE_INTR_DISESTABLISH: 710 return ov->ov_intr_disestablish; 711 case PCI_OVERRIDE_MAKE_TAG: 712 return ov->ov_make_tag; 713 case PCI_OVERRIDE_DECOMPOSE_TAG: 714 return ov->ov_decompose_tag; 715 default: 716 return NULL; 717 } 718 } 719 720 void 721 pci_chipset_tag_destroy(pci_chipset_tag_t pc) 722 { 723 kmem_free(pc, sizeof(struct pci_chipset_tag)); 724 } 725 726 int 727 pci_chipset_tag_create(pci_chipset_tag_t opc, const uint64_t present, 728 const struct pci_overrides *ov, void *ctx, pci_chipset_tag_t *pcp) 729 { 730 uint64_t bit, bits, nbits; 731 pci_chipset_tag_t pc; 732 const void *fp; 733 734 if (ov == NULL || present == 0) 735 return EINVAL; 736 737 pc = kmem_alloc(sizeof(struct pci_chipset_tag), KM_SLEEP); 738 739 if (pc == NULL) 740 return ENOMEM; 741 742 pc->pc_super = opc; 743 744 for (bits = present; bits != 0; bits = nbits) { 745 nbits = bits & (bits - 1); 746 bit = nbits ^ bits; 747 if ((fp = bit_to_function_pointer(ov, bit)) == NULL) { 748 #ifdef DEBUG 749 printf("%s: missing bit %" PRIx64 "\n", __func__, bit); 750 #endif 751 goto einval; 752 } 753 } 754 755 pc->pc_ov = ov; 756 pc->pc_present = present; 757 pc->pc_ctx = ctx; 758 759 *pcp = pc; 760 761 return 0; 762 einval: 763 kmem_free(pc, sizeof(struct pci_chipset_tag)); 764 return EINVAL; 765 } 766 767 static void 768 x86_genfb_set_mapreg(void *opaque, int index, int r, int g, int b) 769 { 770 outb(IO_VGA + VGA_DAC_ADDRW, index); 771 outb(IO_VGA + VGA_DAC_PALETTE, (uint8_t)r >> 2); 772 outb(IO_VGA + VGA_DAC_PALETTE, (uint8_t)g >> 2); 773 outb(IO_VGA + VGA_DAC_PALETTE, (uint8_t)b >> 2); 774 } 775 776 static bool 777 x86_genfb_setmode(struct genfb_softc *sc, int newmode) 778 { 779 #if NGENFB > 0 780 static int curmode = WSDISPLAYIO_MODE_EMUL; 781 782 switch (newmode) { 783 case WSDISPLAYIO_MODE_EMUL: 784 x86_genfb_mtrr_init(sc->sc_fboffset, 785 sc->sc_height * sc->sc_stride); 786 #if NACPICA > 0 && defined(VGA_POST) 787 if (curmode != newmode) { 788 if (vga_posth != NULL && acpi_md_vesa_modenum != 0) { 789 vga_post_set_vbe(vga_posth, 790 acpi_md_vesa_modenum); 791 } 792 } 793 #endif 794 break; 795 } 796 797 curmode = newmode; 798 #endif 799 return true; 800 } 801 802 static bool 803 x86_genfb_suspend(device_t dev, const pmf_qual_t *qual) 804 { 805 return true; 806 } 807 808 static bool 809 x86_genfb_resume(device_t dev, const pmf_qual_t *qual) 810 { 811 #if NGENFB > 0 812 struct pci_genfb_softc *psc = device_private(dev); 813 814 #if NACPICA > 0 && defined(VGA_POST) 815 if (vga_posth != NULL && acpi_md_vbios_reset == 2) { 816 vga_post_call(vga_posth); 817 if (acpi_md_vesa_modenum != 0) 818 vga_post_set_vbe(vga_posth, acpi_md_vesa_modenum); 819 } 820 #endif 821 genfb_restore_palette(&psc->sc_gen); 822 #endif 823 824 return true; 825 } 826 827 device_t 828 device_pci_register(device_t dev, void *aux) 829 { 830 static bool found_console = false; 831 832 device_pci_props_register(dev, aux); 833 834 /* 835 * Handle network interfaces here, the attachment information is 836 * not available driver-independently later. 837 * 838 * For disks, there is nothing useful available at attach time. 839 */ 840 if (device_class(dev) == DV_IFNET) { 841 struct btinfo_netif *bin = lookup_bootinfo(BTINFO_NETIF); 842 if (bin == NULL) 843 return NULL; 844 845 /* 846 * We don't check the driver name against the device name 847 * passed by the boot ROM. The ROM should stay usable if 848 * the driver becomes obsolete. The physical attachment 849 * information (checked below) must be sufficient to 850 * identify the device. 851 */ 852 if (bin->bus == BI_BUS_PCI && 853 device_is_a(device_parent(dev), "pci")) { 854 struct pci_attach_args *paa = aux; 855 int b, d, f; 856 857 /* 858 * Calculate BIOS representation of: 859 * 860 * <bus,device,function> 861 * 862 * and compare. 863 */ 864 pci_decompose_tag(paa->pa_pc, paa->pa_tag, &b, &d, &f); 865 if (bin->addr.tag == ((b << 8) | (d << 3) | f)) 866 return dev; 867 } 868 } 869 if (device_parent(dev) && device_is_a(device_parent(dev), "pci") && 870 found_console == false) { 871 struct btinfo_framebuffer *fbinfo; 872 struct pci_attach_args *pa = aux; 873 prop_dictionary_t dict; 874 875 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_DISPLAY) { 876 #if NWSDISPLAY > 0 && NGENFB > 0 877 extern struct vcons_screen x86_genfb_console_screen; 878 struct rasops_info *ri; 879 880 ri = &x86_genfb_console_screen.scr_ri; 881 #endif 882 883 fbinfo = lookup_bootinfo(BTINFO_FRAMEBUFFER); 884 dict = device_properties(dev); 885 /* 886 * framebuffer drivers other than genfb can work 887 * without the address property 888 */ 889 if (fbinfo != NULL) { 890 if (fbinfo->physaddr != 0) { 891 prop_dictionary_set_uint32(dict, "width", 892 fbinfo->width); 893 prop_dictionary_set_uint32(dict, "height", 894 fbinfo->height); 895 prop_dictionary_set_uint8(dict, "depth", 896 fbinfo->depth); 897 prop_dictionary_set_uint16(dict, "linebytes", 898 fbinfo->stride); 899 900 prop_dictionary_set_uint64(dict, "address", 901 fbinfo->physaddr); 902 #if NWSDISPLAY > 0 && NGENFB > 0 903 if (ri->ri_bits != NULL) { 904 prop_dictionary_set_uint64(dict, 905 "virtual_address", 906 (vaddr_t)ri->ri_origbits); 907 } 908 #endif 909 } 910 #if notyet 911 prop_dictionary_set_bool(dict, "splash", 912 fbinfo->flags & BI_FB_SPLASH ? 913 true : false); 914 #endif 915 if (fbinfo->depth == 8) { 916 gfb_cb.gcc_cookie = NULL; 917 gfb_cb.gcc_set_mapreg = 918 x86_genfb_set_mapreg; 919 prop_dictionary_set_uint64(dict, 920 "cmap_callback", 921 (uint64_t)(uintptr_t)&gfb_cb); 922 } 923 if (fbinfo->physaddr != 0) { 924 mode_cb.gmc_setmode = x86_genfb_setmode; 925 prop_dictionary_set_uint64(dict, 926 "mode_callback", 927 (uint64_t)(uintptr_t)&mode_cb); 928 } 929 930 #if NWSDISPLAY > 0 && NGENFB > 0 931 if (device_is_a(dev, "genfb")) { 932 x86_genfb_set_console_dev(dev); 933 #ifdef DDB 934 db_trap_callback = 935 x86_genfb_ddb_trap_callback; 936 #endif 937 } 938 #endif 939 } 940 prop_dictionary_set_bool(dict, "is_console", true); 941 942 prop_dictionary_set_bool(dict, "clear-screen", false); 943 #if NWSDISPLAY > 0 && NGENFB > 0 944 prop_dictionary_set_uint16(dict, "cursor-row", 945 x86_genfb_console_screen.scr_ri.ri_crow); 946 #endif 947 #if notyet 948 prop_dictionary_set_bool(dict, "splash", 949 fbinfo->flags & BI_FB_SPLASH ? true : false); 950 #endif 951 pmf_cb.gpc_suspend = x86_genfb_suspend; 952 pmf_cb.gpc_resume = x86_genfb_resume; 953 prop_dictionary_set_uint64(dict, 954 "pmf_callback", (uint64_t)(uintptr_t)&pmf_cb); 955 #ifdef VGA_POST 956 vga_posth = vga_post_init(pa->pa_bus, pa->pa_device, 957 pa->pa_function); 958 #endif 959 found_console = true; 960 return NULL; 961 } 962 } 963 return NULL; 964 } 965 966 #if NCOM > 0 967 int 968 cpu_comcnprobe(struct consdev *cn, struct pci_attach_args *pa) 969 { 970 pci_mode_detect(); 971 pa->pa_iot = x86_bus_space_io; 972 pa->pa_pc = 0; 973 pa->pa_tag = pci_make_tag(0, 0, pci_bus_maxdevs(NULL, 0) - 1, 0); 974 return 0; 975 } 976 #endif 977