1 /* $NetBSD: pci_machdep.c,v 1.65 2014/01/27 23:11:50 jakllsch Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved. 35 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 1. Redistributions of source code must retain the above copyright 41 * notice, this list of conditions and the following disclaimer. 42 * 2. Redistributions in binary form must reproduce the above copyright 43 * notice, this list of conditions and the following disclaimer in the 44 * documentation and/or other materials provided with the distribution. 45 * 3. All advertising materials mentioning features or use of this software 46 * must display the following acknowledgement: 47 * This product includes software developed by Charles M. Hannum. 48 * 4. The name of the author may not be used to endorse or promote products 49 * derived from this software without specific prior written permission. 50 * 51 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 52 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 53 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 54 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 55 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 56 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 57 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 58 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 59 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 60 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 61 */ 62 63 /* 64 * Machine-specific functions for PCI autoconfiguration. 65 * 66 * On PCs, there are two methods of generating PCI configuration cycles. 67 * We try to detect the appropriate mechanism for this machine and set 68 * up a few function pointers to access the correct method directly. 69 * 70 * The configuration method can be hard-coded in the config file by 71 * using `options PCI_CONF_MODE=N', where `N' is the configuration mode 72 * as defined in section 3.6.4.1, `Generating Configuration Cycles'. 73 */ 74 75 #include <sys/cdefs.h> 76 __KERNEL_RCSID(0, "$NetBSD: pci_machdep.c,v 1.65 2014/01/27 23:11:50 jakllsch Exp $"); 77 78 #include <sys/types.h> 79 #include <sys/param.h> 80 #include <sys/time.h> 81 #include <sys/systm.h> 82 #include <sys/errno.h> 83 #include <sys/device.h> 84 #include <sys/bus.h> 85 #include <sys/cpu.h> 86 #include <sys/kmem.h> 87 88 #include <uvm/uvm_extern.h> 89 90 #include <machine/bus_private.h> 91 92 #include <machine/pio.h> 93 #include <machine/lock.h> 94 95 #include <dev/isa/isareg.h> 96 #include <dev/isa/isavar.h> 97 #include <dev/pci/pcivar.h> 98 #include <dev/pci/pcireg.h> 99 #include <dev/pci/pccbbreg.h> 100 #include <dev/pci/pcidevs.h> 101 #include <dev/pci/genfb_pcivar.h> 102 103 #include <dev/wsfb/genfbvar.h> 104 #include <arch/x86/include/genfb_machdep.h> 105 #include <dev/ic/vgareg.h> 106 107 #include "acpica.h" 108 #include "genfb.h" 109 #include "isa.h" 110 #include "opt_acpi.h" 111 #include "opt_ddb.h" 112 #include "opt_mpbios.h" 113 #include "opt_puc.h" 114 #include "opt_vga.h" 115 #include "pci.h" 116 #include "wsdisplay.h" 117 #include "com.h" 118 119 #ifdef DDB 120 #include <machine/db_machdep.h> 121 #include <ddb/db_sym.h> 122 #include <ddb/db_extern.h> 123 #endif 124 125 #ifdef VGA_POST 126 #include <x86/vga_post.h> 127 #endif 128 129 #include <machine/autoconf.h> 130 #include <machine/bootinfo.h> 131 132 #ifdef MPBIOS 133 #include <machine/mpbiosvar.h> 134 #endif 135 136 #if NACPICA > 0 137 #include <machine/mpacpi.h> 138 #endif 139 140 #include <machine/mpconfig.h> 141 142 #if NCOM > 0 143 #include <dev/pci/puccn.h> 144 #endif 145 146 #include "opt_pci_conf_mode.h" 147 148 #ifdef PCI_CONF_MODE 149 #if (PCI_CONF_MODE == 1) || (PCI_CONF_MODE == 2) 150 static int pci_mode = PCI_CONF_MODE; 151 #else 152 #error Invalid PCI configuration mode. 153 #endif 154 #else 155 static int pci_mode = -1; 156 #endif 157 158 struct pci_conf_lock { 159 uint32_t cl_cpuno; /* 0: unlocked 160 * 1 + n: locked by CPU n (0 <= n) 161 */ 162 uint32_t cl_sel; /* the address that's being read. */ 163 }; 164 165 static void pci_conf_unlock(struct pci_conf_lock *); 166 static uint32_t pci_conf_selector(pcitag_t, int); 167 static unsigned int pci_conf_port(pcitag_t, int); 168 static void pci_conf_select(uint32_t); 169 static void pci_conf_lock(struct pci_conf_lock *, uint32_t); 170 static void pci_bridge_hook(pci_chipset_tag_t, pcitag_t, void *); 171 struct pci_bridge_hook_arg { 172 void (*func)(pci_chipset_tag_t, pcitag_t, void *); 173 void *arg; 174 }; 175 176 #define PCI_MODE1_ENABLE 0x80000000UL 177 #define PCI_MODE1_ADDRESS_REG 0x0cf8 178 #define PCI_MODE1_DATA_REG 0x0cfc 179 180 #define PCI_MODE2_ENABLE_REG 0x0cf8 181 #define PCI_MODE2_FORWARD_REG 0x0cfa 182 183 #define _tag(b, d, f) \ 184 {.mode1 = PCI_MODE1_ENABLE | ((b) << 16) | ((d) << 11) | ((f) << 8)} 185 #define _qe(bus, dev, fcn, vend, prod) \ 186 {_tag(bus, dev, fcn), PCI_ID_CODE(vend, prod)} 187 const struct { 188 pcitag_t tag; 189 pcireg_t id; 190 } pcim1_quirk_tbl[] = { 191 _qe(0, 0, 0, PCI_VENDOR_INVALID, 0x0000), /* patchable */ 192 _qe(0, 0, 0, PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_TRIFLEX1), 193 /* XXX Triflex2 not tested */ 194 _qe(0, 0, 0, PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_TRIFLEX2), 195 _qe(0, 0, 0, PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_TRIFLEX4), 196 /* Triton needed for Connectix Virtual PC */ 197 _qe(0, 0, 0, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82437FX), 198 /* Connectix Virtual PC 5 has a 440BX */ 199 _qe(0, 0, 0, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82443BX_NOAGP), 200 /* Parallels Desktop for Mac */ 201 _qe(0, 2, 0, PCI_VENDOR_PARALLELS, PCI_PRODUCT_PARALLELS_VIDEO), 202 _qe(0, 3, 0, PCI_VENDOR_PARALLELS, PCI_PRODUCT_PARALLELS_TOOLS), 203 /* SIS 740 */ 204 _qe(0, 0, 0, PCI_VENDOR_SIS, PCI_PRODUCT_SIS_740), 205 /* SIS 741 */ 206 _qe(0, 0, 0, PCI_VENDOR_SIS, PCI_PRODUCT_SIS_741), 207 /* VIA Technologies VX900 */ 208 _qe(0, 0, 0, PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VX900_HB) 209 }; 210 #undef _tag 211 #undef _qe 212 213 /* 214 * PCI doesn't have any special needs; just use the generic versions 215 * of these functions. 216 */ 217 struct x86_bus_dma_tag pci_bus_dma_tag = { 218 ._tag_needs_free = 0, 219 #if defined(_LP64) || defined(PAE) 220 ._bounce_thresh = PCI32_DMA_BOUNCE_THRESHOLD, 221 ._bounce_alloc_lo = ISA_DMA_BOUNCE_THRESHOLD, 222 ._bounce_alloc_hi = PCI32_DMA_BOUNCE_THRESHOLD, 223 #else 224 ._bounce_thresh = 0, 225 ._bounce_alloc_lo = 0, 226 ._bounce_alloc_hi = 0, 227 #endif 228 ._may_bounce = NULL, 229 }; 230 231 #ifdef _LP64 232 struct x86_bus_dma_tag pci_bus_dma64_tag = { 233 ._tag_needs_free = 0, 234 ._bounce_thresh = 0, 235 ._bounce_alloc_lo = 0, 236 ._bounce_alloc_hi = 0, 237 ._may_bounce = NULL, 238 }; 239 #endif 240 241 static struct pci_conf_lock cl0 = { 242 .cl_cpuno = 0UL 243 , .cl_sel = 0UL 244 }; 245 246 static struct pci_conf_lock * const cl = &cl0; 247 248 #if NGENFB > 0 && NACPICA > 0 && defined(VGA_POST) 249 extern int acpi_md_vbios_reset; 250 extern int acpi_md_vesa_modenum; 251 #endif 252 253 static struct genfb_colormap_callback gfb_cb; 254 static struct genfb_pmf_callback pmf_cb; 255 static struct genfb_mode_callback mode_cb; 256 #ifdef VGA_POST 257 static struct vga_post *vga_posth = NULL; 258 #endif 259 260 static void 261 pci_conf_lock(struct pci_conf_lock *ocl, uint32_t sel) 262 { 263 uint32_t cpuno; 264 265 KASSERT(sel != 0); 266 267 kpreempt_disable(); 268 cpuno = cpu_number() + 1; 269 /* If the kernel enters pci_conf_lock() through an interrupt 270 * handler, then the CPU may already hold the lock. 271 * 272 * If the CPU does not already hold the lock, spin until 273 * we can acquire it. 274 */ 275 if (cpuno == cl->cl_cpuno) { 276 ocl->cl_cpuno = cpuno; 277 } else { 278 u_int spins; 279 280 ocl->cl_cpuno = 0; 281 282 spins = SPINLOCK_BACKOFF_MIN; 283 while (atomic_cas_32(&cl->cl_cpuno, 0, cpuno) != 0) { 284 SPINLOCK_BACKOFF(spins); 285 #ifdef LOCKDEBUG 286 if (SPINLOCK_SPINOUT(spins)) { 287 panic("%s: cpu %" PRId32 288 " spun out waiting for cpu %" PRId32, 289 __func__, cpuno, cl->cl_cpuno); 290 } 291 #endif /* LOCKDEBUG */ 292 } 293 } 294 295 /* Only one CPU can be here, so an interlocked atomic_swap(3) 296 * is not necessary. 297 * 298 * Evaluating atomic_cas_32_ni()'s argument, cl->cl_sel, 299 * and applying atomic_cas_32_ni() is not an atomic operation, 300 * however, any interrupt that, in the middle of the 301 * operation, modifies cl->cl_sel, will also restore 302 * cl->cl_sel. So cl->cl_sel will have the same value when 303 * we apply atomic_cas_32_ni() as when we evaluated it, 304 * before. 305 */ 306 ocl->cl_sel = atomic_cas_32_ni(&cl->cl_sel, cl->cl_sel, sel); 307 pci_conf_select(sel); 308 } 309 310 static void 311 pci_conf_unlock(struct pci_conf_lock *ocl) 312 { 313 atomic_cas_32_ni(&cl->cl_sel, cl->cl_sel, ocl->cl_sel); 314 pci_conf_select(ocl->cl_sel); 315 if (ocl->cl_cpuno != cl->cl_cpuno) 316 atomic_cas_32(&cl->cl_cpuno, cl->cl_cpuno, ocl->cl_cpuno); 317 kpreempt_enable(); 318 } 319 320 static uint32_t 321 pci_conf_selector(pcitag_t tag, int reg) 322 { 323 static const pcitag_t mode2_mask = { 324 .mode2 = { 325 .enable = 0xff 326 , .forward = 0xff 327 } 328 }; 329 330 switch (pci_mode) { 331 case 1: 332 return tag.mode1 | reg; 333 case 2: 334 return tag.mode1 & mode2_mask.mode1; 335 default: 336 panic("%s: mode not configured", __func__); 337 } 338 } 339 340 static unsigned int 341 pci_conf_port(pcitag_t tag, int reg) 342 { 343 switch (pci_mode) { 344 case 1: 345 return PCI_MODE1_DATA_REG; 346 case 2: 347 return tag.mode2.port | reg; 348 default: 349 panic("%s: mode not configured", __func__); 350 } 351 } 352 353 static void 354 pci_conf_select(uint32_t sel) 355 { 356 pcitag_t tag; 357 358 switch (pci_mode) { 359 case 1: 360 outl(PCI_MODE1_ADDRESS_REG, sel); 361 return; 362 case 2: 363 tag.mode1 = sel; 364 outb(PCI_MODE2_ENABLE_REG, tag.mode2.enable); 365 if (tag.mode2.enable != 0) 366 outb(PCI_MODE2_FORWARD_REG, tag.mode2.forward); 367 return; 368 default: 369 panic("%s: mode not configured", __func__); 370 } 371 } 372 373 void 374 pci_attach_hook(device_t parent, device_t self, struct pcibus_attach_args *pba) 375 { 376 377 if (pba->pba_bus == 0) 378 aprint_normal(": configuration mode %d", pci_mode); 379 #ifdef MPBIOS 380 mpbios_pci_attach_hook(parent, self, pba); 381 #endif 382 #if NACPICA > 0 383 mpacpi_pci_attach_hook(parent, self, pba); 384 #endif 385 } 386 387 int 388 pci_bus_maxdevs(pci_chipset_tag_t pc, int busno) 389 { 390 /* 391 * Bus number is irrelevant. If Configuration Mechanism 2 is in 392 * use, can only have devices 0-15 on any bus. If Configuration 393 * Mechanism 1 is in use, can have devices 0-32 (i.e. the `normal' 394 * range). 395 */ 396 if (pci_mode == 2) 397 return (16); 398 else 399 return (32); 400 } 401 402 pcitag_t 403 pci_make_tag(pci_chipset_tag_t pc, int bus, int device, int function) 404 { 405 pci_chipset_tag_t ipc; 406 pcitag_t tag; 407 408 for (ipc = pc; ipc != NULL; ipc = ipc->pc_super) { 409 if ((ipc->pc_present & PCI_OVERRIDE_MAKE_TAG) == 0) 410 continue; 411 return (*ipc->pc_ov->ov_make_tag)(ipc->pc_ctx, 412 pc, bus, device, function); 413 } 414 415 switch (pci_mode) { 416 case 1: 417 if (bus >= 256 || device >= 32 || function >= 8) 418 panic("%s: bad request", __func__); 419 420 tag.mode1 = PCI_MODE1_ENABLE | 421 (bus << 16) | (device << 11) | (function << 8); 422 return tag; 423 case 2: 424 if (bus >= 256 || device >= 16 || function >= 8) 425 panic("%s: bad request", __func__); 426 427 tag.mode2.port = 0xc000 | (device << 8); 428 tag.mode2.enable = 0xf0 | (function << 1); 429 tag.mode2.forward = bus; 430 return tag; 431 default: 432 panic("%s: mode not configured", __func__); 433 } 434 } 435 436 void 437 pci_decompose_tag(pci_chipset_tag_t pc, pcitag_t tag, 438 int *bp, int *dp, int *fp) 439 { 440 pci_chipset_tag_t ipc; 441 442 for (ipc = pc; ipc != NULL; ipc = ipc->pc_super) { 443 if ((ipc->pc_present & PCI_OVERRIDE_DECOMPOSE_TAG) == 0) 444 continue; 445 (*ipc->pc_ov->ov_decompose_tag)(ipc->pc_ctx, 446 pc, tag, bp, dp, fp); 447 return; 448 } 449 450 switch (pci_mode) { 451 case 1: 452 if (bp != NULL) 453 *bp = (tag.mode1 >> 16) & 0xff; 454 if (dp != NULL) 455 *dp = (tag.mode1 >> 11) & 0x1f; 456 if (fp != NULL) 457 *fp = (tag.mode1 >> 8) & 0x7; 458 return; 459 case 2: 460 if (bp != NULL) 461 *bp = tag.mode2.forward & 0xff; 462 if (dp != NULL) 463 *dp = (tag.mode2.port >> 8) & 0xf; 464 if (fp != NULL) 465 *fp = (tag.mode2.enable >> 1) & 0x7; 466 return; 467 default: 468 panic("%s: mode not configured", __func__); 469 } 470 } 471 472 pcireg_t 473 pci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg) 474 { 475 pci_chipset_tag_t ipc; 476 pcireg_t data; 477 struct pci_conf_lock ocl; 478 479 KASSERT((reg & 0x3) == 0); 480 481 for (ipc = pc; ipc != NULL; ipc = ipc->pc_super) { 482 if ((ipc->pc_present & PCI_OVERRIDE_CONF_READ) == 0) 483 continue; 484 return (*ipc->pc_ov->ov_conf_read)(ipc->pc_ctx, pc, tag, reg); 485 } 486 487 pci_conf_lock(&ocl, pci_conf_selector(tag, reg)); 488 data = inl(pci_conf_port(tag, reg)); 489 pci_conf_unlock(&ocl); 490 return data; 491 } 492 493 void 494 pci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data) 495 { 496 pci_chipset_tag_t ipc; 497 struct pci_conf_lock ocl; 498 499 KASSERT((reg & 0x3) == 0); 500 501 for (ipc = pc; ipc != NULL; ipc = ipc->pc_super) { 502 if ((ipc->pc_present & PCI_OVERRIDE_CONF_WRITE) == 0) 503 continue; 504 (*ipc->pc_ov->ov_conf_write)(ipc->pc_ctx, pc, tag, reg, 505 data); 506 return; 507 } 508 509 pci_conf_lock(&ocl, pci_conf_selector(tag, reg)); 510 outl(pci_conf_port(tag, reg), data); 511 pci_conf_unlock(&ocl); 512 } 513 514 void 515 pci_mode_set(int mode) 516 { 517 KASSERT(pci_mode == -1 || pci_mode == mode); 518 519 pci_mode = mode; 520 } 521 522 int 523 pci_mode_detect(void) 524 { 525 uint32_t sav, val; 526 int i; 527 pcireg_t idreg; 528 extern char cpu_brand_string[]; 529 530 if (pci_mode != -1) 531 return pci_mode; 532 533 /* 534 * We try to divine which configuration mode the host bridge wants. 535 */ 536 537 sav = inl(PCI_MODE1_ADDRESS_REG); 538 539 pci_mode = 1; /* assume this for now */ 540 /* 541 * catch some known buggy implementations of mode 1 542 */ 543 for (i = 0; i < __arraycount(pcim1_quirk_tbl); i++) { 544 pcitag_t t; 545 546 if (PCI_VENDOR(pcim1_quirk_tbl[i].id) == PCI_VENDOR_INVALID) 547 continue; 548 t.mode1 = pcim1_quirk_tbl[i].tag.mode1; 549 idreg = pci_conf_read(NULL, t, PCI_ID_REG); /* needs "pci_mode" */ 550 if (idreg == pcim1_quirk_tbl[i].id) { 551 #ifdef DEBUG 552 printf("known mode 1 PCI chipset (%08x)\n", 553 idreg); 554 #endif 555 return (pci_mode); 556 } 557 } 558 if (memcmp(cpu_brand_string, "QEMU", 4) == 0) { 559 /* PR 45671, https://bugs.launchpad.net/qemu/+bug/897771 */ 560 #ifdef DEBUG 561 printf("forcing PCI mode 1 for QEMU\n"); 562 #endif 563 return (pci_mode); 564 } 565 566 /* 567 * Strong check for standard compliant mode 1: 568 * 1. bit 31 ("enable") can be set 569 * 2. byte/word access does not affect register 570 */ 571 outl(PCI_MODE1_ADDRESS_REG, PCI_MODE1_ENABLE); 572 outb(PCI_MODE1_ADDRESS_REG + 3, 0); 573 outw(PCI_MODE1_ADDRESS_REG + 2, 0); 574 val = inl(PCI_MODE1_ADDRESS_REG); 575 if ((val & 0x80fffffc) != PCI_MODE1_ENABLE) { 576 #ifdef DEBUG 577 printf("pci_mode_detect: mode 1 enable failed (%x)\n", 578 val); 579 #endif 580 goto not1; 581 } 582 outl(PCI_MODE1_ADDRESS_REG, 0); 583 val = inl(PCI_MODE1_ADDRESS_REG); 584 if ((val & 0x80fffffc) != 0) 585 goto not1; 586 return (pci_mode); 587 not1: 588 outl(PCI_MODE1_ADDRESS_REG, sav); 589 590 /* 591 * This mode 2 check is quite weak (and known to give false 592 * positives on some Compaq machines). 593 * However, this doesn't matter, because this is the 594 * last test, and simply no PCI devices will be found if 595 * this happens. 596 */ 597 outb(PCI_MODE2_ENABLE_REG, 0); 598 outb(PCI_MODE2_FORWARD_REG, 0); 599 if (inb(PCI_MODE2_ENABLE_REG) != 0 || 600 inb(PCI_MODE2_FORWARD_REG) != 0) 601 goto not2; 602 return (pci_mode = 2); 603 not2: 604 605 return (pci_mode = 0); 606 } 607 608 void 609 pci_device_foreach(pci_chipset_tag_t pc, int maxbus, 610 void (*func)(pci_chipset_tag_t, pcitag_t, void *), void *context) 611 { 612 pci_device_foreach_min(pc, 0, maxbus, func, context); 613 } 614 615 void 616 pci_device_foreach_min(pci_chipset_tag_t pc, int minbus, int maxbus, 617 void (*func)(pci_chipset_tag_t, pcitag_t, void *), void *context) 618 { 619 const struct pci_quirkdata *qd; 620 int bus, device, function, maxdevs, nfuncs; 621 pcireg_t id, bhlcr; 622 pcitag_t tag; 623 624 for (bus = minbus; bus <= maxbus; bus++) { 625 maxdevs = pci_bus_maxdevs(pc, bus); 626 for (device = 0; device < maxdevs; device++) { 627 tag = pci_make_tag(pc, bus, device, 0); 628 id = pci_conf_read(pc, tag, PCI_ID_REG); 629 630 /* Invalid vendor ID value? */ 631 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 632 continue; 633 /* XXX Not invalid, but we've done this ~forever. */ 634 if (PCI_VENDOR(id) == 0) 635 continue; 636 637 qd = pci_lookup_quirkdata(PCI_VENDOR(id), 638 PCI_PRODUCT(id)); 639 640 bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 641 if (PCI_HDRTYPE_MULTIFN(bhlcr) || 642 (qd != NULL && 643 (qd->quirks & PCI_QUIRK_MULTIFUNCTION) != 0)) 644 nfuncs = 8; 645 else 646 nfuncs = 1; 647 648 for (function = 0; function < nfuncs; function++) { 649 tag = pci_make_tag(pc, bus, device, function); 650 id = pci_conf_read(pc, tag, PCI_ID_REG); 651 652 /* Invalid vendor ID value? */ 653 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 654 continue; 655 /* 656 * XXX Not invalid, but we've done this 657 * ~forever. 658 */ 659 if (PCI_VENDOR(id) == 0) 660 continue; 661 (*func)(pc, tag, context); 662 } 663 } 664 } 665 } 666 667 void 668 pci_bridge_foreach(pci_chipset_tag_t pc, int minbus, int maxbus, 669 void (*func)(pci_chipset_tag_t, pcitag_t, void *), void *ctx) 670 { 671 struct pci_bridge_hook_arg bridge_hook; 672 673 bridge_hook.func = func; 674 bridge_hook.arg = ctx; 675 676 pci_device_foreach_min(pc, minbus, maxbus, pci_bridge_hook, 677 &bridge_hook); 678 } 679 680 static void 681 pci_bridge_hook(pci_chipset_tag_t pc, pcitag_t tag, void *ctx) 682 { 683 struct pci_bridge_hook_arg *bridge_hook = (void *)ctx; 684 pcireg_t reg; 685 686 reg = pci_conf_read(pc, tag, PCI_CLASS_REG); 687 if (PCI_CLASS(reg) == PCI_CLASS_BRIDGE && 688 (PCI_SUBCLASS(reg) == PCI_SUBCLASS_BRIDGE_PCI || 689 PCI_SUBCLASS(reg) == PCI_SUBCLASS_BRIDGE_CARDBUS)) { 690 (*bridge_hook->func)(pc, tag, bridge_hook->arg); 691 } 692 } 693 694 static const void * 695 bit_to_function_pointer(const struct pci_overrides *ov, uint64_t bit) 696 { 697 switch (bit) { 698 case PCI_OVERRIDE_CONF_READ: 699 return ov->ov_conf_read; 700 case PCI_OVERRIDE_CONF_WRITE: 701 return ov->ov_conf_write; 702 case PCI_OVERRIDE_INTR_MAP: 703 return ov->ov_intr_map; 704 case PCI_OVERRIDE_INTR_STRING: 705 return ov->ov_intr_string; 706 case PCI_OVERRIDE_INTR_EVCNT: 707 return ov->ov_intr_evcnt; 708 case PCI_OVERRIDE_INTR_ESTABLISH: 709 return ov->ov_intr_establish; 710 case PCI_OVERRIDE_INTR_DISESTABLISH: 711 return ov->ov_intr_disestablish; 712 case PCI_OVERRIDE_MAKE_TAG: 713 return ov->ov_make_tag; 714 case PCI_OVERRIDE_DECOMPOSE_TAG: 715 return ov->ov_decompose_tag; 716 default: 717 return NULL; 718 } 719 } 720 721 void 722 pci_chipset_tag_destroy(pci_chipset_tag_t pc) 723 { 724 kmem_free(pc, sizeof(struct pci_chipset_tag)); 725 } 726 727 int 728 pci_chipset_tag_create(pci_chipset_tag_t opc, const uint64_t present, 729 const struct pci_overrides *ov, void *ctx, pci_chipset_tag_t *pcp) 730 { 731 uint64_t bit, bits, nbits; 732 pci_chipset_tag_t pc; 733 const void *fp; 734 735 if (ov == NULL || present == 0) 736 return EINVAL; 737 738 pc = kmem_alloc(sizeof(struct pci_chipset_tag), KM_SLEEP); 739 740 if (pc == NULL) 741 return ENOMEM; 742 743 pc->pc_super = opc; 744 745 for (bits = present; bits != 0; bits = nbits) { 746 nbits = bits & (bits - 1); 747 bit = nbits ^ bits; 748 if ((fp = bit_to_function_pointer(ov, bit)) == NULL) { 749 #ifdef DEBUG 750 printf("%s: missing bit %" PRIx64 "\n", __func__, bit); 751 #endif 752 goto einval; 753 } 754 } 755 756 pc->pc_ov = ov; 757 pc->pc_present = present; 758 pc->pc_ctx = ctx; 759 760 *pcp = pc; 761 762 return 0; 763 einval: 764 kmem_free(pc, sizeof(struct pci_chipset_tag)); 765 return EINVAL; 766 } 767 768 static void 769 x86_genfb_set_mapreg(void *opaque, int index, int r, int g, int b) 770 { 771 outb(IO_VGA + VGA_DAC_ADDRW, index); 772 outb(IO_VGA + VGA_DAC_PALETTE, (uint8_t)r >> 2); 773 outb(IO_VGA + VGA_DAC_PALETTE, (uint8_t)g >> 2); 774 outb(IO_VGA + VGA_DAC_PALETTE, (uint8_t)b >> 2); 775 } 776 777 static bool 778 x86_genfb_setmode(struct genfb_softc *sc, int newmode) 779 { 780 #if NGENFB > 0 781 static int curmode = WSDISPLAYIO_MODE_EMUL; 782 783 switch (newmode) { 784 case WSDISPLAYIO_MODE_EMUL: 785 x86_genfb_mtrr_init(sc->sc_fboffset, 786 sc->sc_height * sc->sc_stride); 787 #if NACPICA > 0 && defined(VGA_POST) 788 if (curmode != newmode) { 789 if (vga_posth != NULL && acpi_md_vesa_modenum != 0) { 790 vga_post_set_vbe(vga_posth, 791 acpi_md_vesa_modenum); 792 } 793 } 794 #endif 795 break; 796 } 797 798 curmode = newmode; 799 #endif 800 return true; 801 } 802 803 static bool 804 x86_genfb_suspend(device_t dev, const pmf_qual_t *qual) 805 { 806 return true; 807 } 808 809 static bool 810 x86_genfb_resume(device_t dev, const pmf_qual_t *qual) 811 { 812 #if NGENFB > 0 813 struct pci_genfb_softc *psc = device_private(dev); 814 815 #if NACPICA > 0 && defined(VGA_POST) 816 if (vga_posth != NULL && acpi_md_vbios_reset == 2) { 817 vga_post_call(vga_posth); 818 if (acpi_md_vesa_modenum != 0) 819 vga_post_set_vbe(vga_posth, acpi_md_vesa_modenum); 820 } 821 #endif 822 genfb_restore_palette(&psc->sc_gen); 823 #endif 824 825 return true; 826 } 827 828 device_t 829 device_pci_register(device_t dev, void *aux) 830 { 831 static bool found_console = false; 832 833 device_pci_props_register(dev, aux); 834 835 /* 836 * Handle network interfaces here, the attachment information is 837 * not available driver-independently later. 838 * 839 * For disks, there is nothing useful available at attach time. 840 */ 841 if (device_class(dev) == DV_IFNET) { 842 struct btinfo_netif *bin = lookup_bootinfo(BTINFO_NETIF); 843 if (bin == NULL) 844 return NULL; 845 846 /* 847 * We don't check the driver name against the device name 848 * passed by the boot ROM. The ROM should stay usable if 849 * the driver becomes obsolete. The physical attachment 850 * information (checked below) must be sufficient to 851 * identify the device. 852 */ 853 if (bin->bus == BI_BUS_PCI && 854 device_is_a(device_parent(dev), "pci")) { 855 struct pci_attach_args *paa = aux; 856 int b, d, f; 857 858 /* 859 * Calculate BIOS representation of: 860 * 861 * <bus,device,function> 862 * 863 * and compare. 864 */ 865 pci_decompose_tag(paa->pa_pc, paa->pa_tag, &b, &d, &f); 866 if (bin->addr.tag == ((b << 8) | (d << 3) | f)) 867 return dev; 868 } 869 } 870 if (device_parent(dev) && device_is_a(device_parent(dev), "pci") && 871 found_console == false) { 872 struct btinfo_framebuffer *fbinfo; 873 struct pci_attach_args *pa = aux; 874 prop_dictionary_t dict; 875 876 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_DISPLAY) { 877 #if NWSDISPLAY > 0 && NGENFB > 0 878 extern struct vcons_screen x86_genfb_console_screen; 879 struct rasops_info *ri; 880 881 ri = &x86_genfb_console_screen.scr_ri; 882 #endif 883 884 fbinfo = lookup_bootinfo(BTINFO_FRAMEBUFFER); 885 dict = device_properties(dev); 886 /* 887 * framebuffer drivers other than genfb can work 888 * without the address property 889 */ 890 if (fbinfo != NULL) { 891 if (fbinfo->physaddr != 0) { 892 prop_dictionary_set_uint32(dict, "width", 893 fbinfo->width); 894 prop_dictionary_set_uint32(dict, "height", 895 fbinfo->height); 896 prop_dictionary_set_uint8(dict, "depth", 897 fbinfo->depth); 898 prop_dictionary_set_uint16(dict, "linebytes", 899 fbinfo->stride); 900 901 prop_dictionary_set_uint64(dict, "address", 902 fbinfo->physaddr); 903 #if NWSDISPLAY > 0 && NGENFB > 0 904 if (ri->ri_bits != NULL) { 905 prop_dictionary_set_uint64(dict, 906 "virtual_address", 907 (vaddr_t)ri->ri_origbits); 908 } 909 #endif 910 } 911 #if notyet 912 prop_dictionary_set_bool(dict, "splash", 913 fbinfo->flags & BI_FB_SPLASH ? 914 true : false); 915 #endif 916 if (fbinfo->depth == 8) { 917 gfb_cb.gcc_cookie = NULL; 918 gfb_cb.gcc_set_mapreg = 919 x86_genfb_set_mapreg; 920 prop_dictionary_set_uint64(dict, 921 "cmap_callback", 922 (uint64_t)(uintptr_t)&gfb_cb); 923 } 924 if (fbinfo->physaddr != 0) { 925 mode_cb.gmc_setmode = x86_genfb_setmode; 926 prop_dictionary_set_uint64(dict, 927 "mode_callback", 928 (uint64_t)(uintptr_t)&mode_cb); 929 } 930 931 #if NWSDISPLAY > 0 && NGENFB > 0 932 if (device_is_a(dev, "genfb")) { 933 x86_genfb_set_console_dev(dev); 934 #ifdef DDB 935 db_trap_callback = 936 x86_genfb_ddb_trap_callback; 937 #endif 938 } 939 #endif 940 } 941 #if 1 && NWSDISPLAY > 0 && NGENFB > 0 942 /* XXX */ 943 if (device_is_a(dev, "genfb")) { 944 prop_dictionary_set_bool(dict, "is_console", 945 genfb_is_console()); 946 } else 947 #endif 948 prop_dictionary_set_bool(dict, "is_console", true); 949 950 prop_dictionary_set_bool(dict, "clear-screen", false); 951 #if NWSDISPLAY > 0 && NGENFB > 0 952 prop_dictionary_set_uint16(dict, "cursor-row", 953 x86_genfb_console_screen.scr_ri.ri_crow); 954 #endif 955 #if notyet 956 prop_dictionary_set_bool(dict, "splash", 957 fbinfo->flags & BI_FB_SPLASH ? true : false); 958 #endif 959 pmf_cb.gpc_suspend = x86_genfb_suspend; 960 pmf_cb.gpc_resume = x86_genfb_resume; 961 prop_dictionary_set_uint64(dict, 962 "pmf_callback", (uint64_t)(uintptr_t)&pmf_cb); 963 #ifdef VGA_POST 964 vga_posth = vga_post_init(pa->pa_bus, pa->pa_device, 965 pa->pa_function); 966 #endif 967 found_console = true; 968 return NULL; 969 } 970 } 971 return NULL; 972 } 973 974 #ifndef PUC_CNBUS 975 #define PUC_CNBUS 0 976 #endif 977 978 #if NCOM > 0 979 int 980 cpu_puc_cnprobe(struct consdev *cn, struct pci_attach_args *pa) 981 { 982 pci_mode_detect(); 983 pa->pa_iot = x86_bus_space_io; 984 pa->pa_memt = x86_bus_space_mem; 985 pa->pa_pc = 0; 986 pa->pa_tag = pci_make_tag(0, PUC_CNBUS, pci_bus_maxdevs(NULL, 0) - 1, 987 0); 988 989 return 0; 990 } 991 #endif 992