1 /* $NetBSD: pci_intr_machdep.c,v 1.50 2019/06/17 06:38:29 msaitoh Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998, 2009 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved. 35 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 1. Redistributions of source code must retain the above copyright 41 * notice, this list of conditions and the following disclaimer. 42 * 2. Redistributions in binary form must reproduce the above copyright 43 * notice, this list of conditions and the following disclaimer in the 44 * documentation and/or other materials provided with the distribution. 45 * 3. All advertising materials mentioning features or use of this software 46 * must display the following acknowledgement: 47 * This product includes software developed by Charles M. Hannum. 48 * 4. The name of the author may not be used to endorse or promote products 49 * derived from this software without specific prior written permission. 50 * 51 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 52 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 53 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 54 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 55 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 56 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 57 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 58 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 59 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 60 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 61 */ 62 63 /* 64 * Machine-specific functions for PCI autoconfiguration. 65 * 66 * On PCs, there are two methods of generating PCI configuration cycles. 67 * We try to detect the appropriate mechanism for this machine and set 68 * up a few function pointers to access the correct method directly. 69 * 70 * The configuration method can be hard-coded in the config file by 71 * using `options PCI_CONF_MODE=N', where `N' is the configuration mode 72 * as defined section 3.6.4.1, `Generating Configuration Cycles'. 73 */ 74 75 #include <sys/cdefs.h> 76 __KERNEL_RCSID(0, "$NetBSD: pci_intr_machdep.c,v 1.50 2019/06/17 06:38:29 msaitoh Exp $"); 77 78 #include <sys/types.h> 79 #include <sys/param.h> 80 #include <sys/time.h> 81 #include <sys/systm.h> 82 #include <sys/cpu.h> 83 #include <sys/errno.h> 84 #include <sys/device.h> 85 #include <sys/intr.h> 86 #include <sys/kmem.h> 87 88 #include <dev/pci/pcivar.h> 89 90 #include "ioapic.h" 91 #include "eisa.h" 92 #include "acpica.h" 93 #include "opt_mpbios.h" 94 #include "opt_acpi.h" 95 96 #include <machine/i82489reg.h> 97 98 #if NIOAPIC > 0 || NACPICA > 0 99 #include <machine/i82093reg.h> 100 #include <machine/i82093var.h> 101 #include <machine/mpconfig.h> 102 #include <machine/mpbiosvar.h> 103 #include <machine/pic.h> 104 #include <x86/pci/pci_msi_machdep.h> 105 #else 106 #include <machine/i82093var.h> 107 #endif 108 109 #ifdef MPBIOS 110 #include <machine/mpbiosvar.h> 111 #endif 112 113 #if NACPICA > 0 114 #include <machine/mpacpi.h> 115 #endif 116 117 int 118 pci_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp) 119 { 120 pci_intr_pin_t pin = pa->pa_intrpin; 121 pci_intr_line_t line = pa->pa_intrline; 122 pci_chipset_tag_t ipc, pc = pa->pa_pc; 123 #if NIOAPIC > 0 || NACPICA > 0 124 pci_intr_pin_t rawpin = pa->pa_rawintrpin; 125 int bus, dev, func; 126 #endif 127 128 for (ipc = pc; ipc != NULL; ipc = ipc->pc_super) { 129 if ((ipc->pc_present & PCI_OVERRIDE_INTR_MAP) == 0) 130 continue; 131 return (*ipc->pc_ov->ov_intr_map)(ipc->pc_ctx, pa, ihp); 132 } 133 134 if (pin == 0) { 135 /* No IRQ used. */ 136 goto bad; 137 } 138 139 *ihp = 0; 140 141 if (pin > PCI_INTERRUPT_PIN_MAX) { 142 aprint_normal("pci_intr_map: bad interrupt pin %d\n", pin); 143 goto bad; 144 } 145 146 #if NIOAPIC > 0 || NACPICA > 0 147 KASSERT(rawpin >= PCI_INTERRUPT_PIN_A); 148 KASSERT(rawpin <= PCI_INTERRUPT_PIN_D); 149 pci_decompose_tag(pc, pa->pa_tag, &bus, &dev, &func); 150 if (mp_busses != NULL) { 151 /* 152 * Note: PCI_INTERRUPT_PIN_A == 1 where intr_find_mpmapping 153 * wants pci bus_pin encoding which uses INT_A == 0. 154 */ 155 if (intr_find_mpmapping(bus, 156 (dev << 2) | (rawpin - PCI_INTERRUPT_PIN_A), ihp) == 0) { 157 if (APIC_IRQ_LEGACY_IRQ(*ihp) == 0) 158 *ihp |= line; 159 return 0; 160 } 161 /* 162 * No explicit PCI mapping found. This is not fatal, 163 * we'll try the ISA (or possibly EISA) mappings next. 164 */ 165 } 166 #endif 167 168 /* 169 * Section 6.2.4, `Miscellaneous Functions', says that 255 means 170 * `unknown' or `no connection' on a PC. We assume that a device with 171 * `no connection' either doesn't have an interrupt (in which case the 172 * pin number should be 0, and would have been noticed above), or 173 * wasn't configured by the BIOS (in which case we punt, since there's 174 * no real way we can know how the interrupt lines are mapped in the 175 * hardware). 176 * 177 * XXX 178 * Since IRQ 0 is only used by the clock, and we can't actually be sure 179 * that the BIOS did its job, we also recognize that as meaning that 180 * the BIOS has not configured the device. 181 */ 182 if (line == 0 || line == X86_PCI_INTERRUPT_LINE_NO_CONNECTION) { 183 aprint_normal("pci_intr_map: no mapping for pin %c (line=%02x)\n", 184 '@' + pin, line); 185 goto bad; 186 } else { 187 if (line >= NUM_LEGACY_IRQS) { 188 aprint_normal("pci_intr_map: bad interrupt line %d\n", line); 189 goto bad; 190 } 191 if (line == 2) { 192 aprint_normal("pci_intr_map: changed line 2 to line 9\n"); 193 line = 9; 194 } 195 } 196 #if NIOAPIC > 0 || NACPICA > 0 197 if (mp_busses != NULL) { 198 if (intr_find_mpmapping(mp_isa_bus, line, ihp) == 0) { 199 if ((*ihp & 0xff) == 0) 200 *ihp |= line; 201 return 0; 202 } 203 #if NEISA > 0 204 if (intr_find_mpmapping(mp_eisa_bus, line, ihp) == 0) { 205 if ((*ihp & 0xff) == 0) 206 *ihp |= line; 207 return 0; 208 } 209 #endif 210 aprint_normal("pci_intr_map: bus %d dev %d func %d pin %d; line %d\n", 211 bus, dev, func, pin, line); 212 aprint_normal("pci_intr_map: no MP mapping found\n"); 213 } 214 #endif 215 216 *ihp = line; 217 return 0; 218 219 bad: 220 *ihp = -1; 221 return 1; 222 } 223 224 const char * 225 pci_intr_string(pci_chipset_tag_t pc, pci_intr_handle_t ih, char *buf, 226 size_t len) 227 { 228 pci_chipset_tag_t ipc; 229 230 for (ipc = pc; ipc != NULL; ipc = ipc->pc_super) { 231 if ((ipc->pc_present & PCI_OVERRIDE_INTR_STRING) == 0) 232 continue; 233 return (*ipc->pc_ov->ov_intr_string)(ipc->pc_ctx, pc, ih, 234 buf, len); 235 } 236 237 #if defined(__HAVE_PCI_MSI_MSIX) 238 if (INT_VIA_MSI(ih)) 239 return x86_pci_msi_string(pc, ih, buf, len); 240 #endif 241 242 return intr_string(ih & ~MPSAFE_MASK, buf, len); 243 } 244 245 246 const struct evcnt * 247 pci_intr_evcnt(pci_chipset_tag_t pc, pci_intr_handle_t ih) 248 { 249 pci_chipset_tag_t ipc; 250 251 for (ipc = pc; ipc != NULL; ipc = ipc->pc_super) { 252 if ((ipc->pc_present & PCI_OVERRIDE_INTR_EVCNT) == 0) 253 continue; 254 return (*ipc->pc_ov->ov_intr_evcnt)(ipc->pc_ctx, pc, ih); 255 } 256 257 /* XXX for now, no evcnt parent reported */ 258 return NULL; 259 } 260 261 int 262 pci_intr_setattr(pci_chipset_tag_t pc, pci_intr_handle_t *ih, 263 int attr, uint64_t data) 264 { 265 266 switch (attr) { 267 case PCI_INTR_MPSAFE: 268 if (data) { 269 *ih |= MPSAFE_MASK; 270 } else { 271 *ih &= ~MPSAFE_MASK; 272 } 273 /* XXX Set live if already mapped. */ 274 return 0; 275 default: 276 return ENODEV; 277 } 278 } 279 280 static int 281 pci_intr_find_intx_irq(pci_intr_handle_t ih, int *irq, struct pic **pic, 282 int *pin) 283 { 284 285 KASSERT(irq != NULL); 286 KASSERT(pic != NULL); 287 KASSERT(pin != NULL); 288 289 *pic = &i8259_pic; 290 *pin = *irq = APIC_IRQ_LEGACY_IRQ(ih); 291 292 #if NIOAPIC > 0 293 if (ih & APIC_INT_VIA_APIC) { 294 struct ioapic_softc *ioapic; 295 296 ioapic = ioapic_find(APIC_IRQ_APIC(ih)); 297 if (ioapic == NULL) 298 return ENOENT; 299 *pic = &ioapic->sc_pic; 300 *pin = APIC_IRQ_PIN(ih); 301 *irq = APIC_IRQ_LEGACY_IRQ(ih); 302 if (*irq < 0 || *irq >= NUM_LEGACY_IRQS) 303 *irq = -1; 304 } 305 #endif 306 307 return 0; 308 } 309 310 static void * 311 pci_intr_establish_xname_internal(pci_chipset_tag_t pc, pci_intr_handle_t ih, 312 int level, int (*func)(void *), void *arg, const char *xname) 313 { 314 int pin, irq; 315 struct pic *pic; 316 bool mpsafe; 317 pci_chipset_tag_t ipc; 318 319 for (ipc = pc; ipc != NULL; ipc = ipc->pc_super) { 320 if ((ipc->pc_present & PCI_OVERRIDE_INTR_ESTABLISH) == 0) 321 continue; 322 return (*ipc->pc_ov->ov_intr_establish)(ipc->pc_ctx, 323 pc, ih, level, func, arg); 324 } 325 326 327 #ifdef __HAVE_PCI_MSI_MSIX 328 if (INT_VIA_MSI(ih)) { 329 if (MSI_INT_IS_MSIX(ih)) 330 return x86_pci_msix_establish(pc, ih, level, func, arg, 331 xname); 332 else 333 return x86_pci_msi_establish(pc, ih, level, func, arg, 334 xname); 335 } 336 #endif 337 if (pci_intr_find_intx_irq(ih, &irq, &pic, &pin)) { 338 aprint_normal("%s: bad pic %d\n", __func__, 339 APIC_IRQ_APIC(ih)); 340 return NULL; 341 } 342 343 mpsafe = ((ih & MPSAFE_MASK) != 0); 344 345 return intr_establish_xname(irq, pic, pin, IST_LEVEL, level, func, arg, 346 mpsafe, xname); 347 } 348 349 void * 350 pci_intr_establish(pci_chipset_tag_t pc, pci_intr_handle_t ih, 351 int level, int (*func)(void *), void *arg) 352 { 353 354 return pci_intr_establish_xname_internal(pc, ih, level, func, arg, "unknown"); 355 } 356 357 void * 358 pci_intr_establish_xname(pci_chipset_tag_t pc, pci_intr_handle_t ih, 359 int level, int (*func)(void *), void *arg, const char *xname) 360 { 361 362 return pci_intr_establish_xname_internal(pc, ih, level, func, arg, xname); 363 } 364 365 366 void 367 pci_intr_disestablish(pci_chipset_tag_t pc, void *cookie) 368 { 369 pci_chipset_tag_t ipc; 370 371 for (ipc = pc; ipc != NULL; ipc = ipc->pc_super) { 372 if ((ipc->pc_present & PCI_OVERRIDE_INTR_DISESTABLISH) == 0) 373 continue; 374 (*ipc->pc_ov->ov_intr_disestablish)(ipc->pc_ctx, pc, cookie); 375 return; 376 } 377 378 /* MSI/MSI-X processing is switched in intr_disestablish(). */ 379 intr_disestablish(cookie); 380 } 381 382 #if NIOAPIC > 0 383 #ifdef __HAVE_PCI_MSI_MSIX 384 pci_intr_type_t 385 pci_intr_type(pci_chipset_tag_t pc, pci_intr_handle_t ih) 386 { 387 388 if (INT_VIA_MSI(ih)) { 389 if (MSI_INT_IS_MSIX(ih)) 390 return PCI_INTR_TYPE_MSIX; 391 else 392 return PCI_INTR_TYPE_MSI; 393 } else { 394 return PCI_INTR_TYPE_INTX; 395 } 396 } 397 398 static const char * 399 x86_pci_intx_create_intrid(pci_chipset_tag_t pc, pci_intr_handle_t ih, char *buf, 400 size_t len) 401 { 402 #if !defined(XENPV) 403 int pin, irq; 404 struct pic *pic; 405 406 KASSERT(!INT_VIA_MSI(ih)); 407 408 pic = &i8259_pic; 409 pin = irq = APIC_IRQ_LEGACY_IRQ(ih); 410 411 if (pci_intr_find_intx_irq(ih, &irq, &pic, &pin)) { 412 aprint_normal("%s: bad pic %d\n", __func__, 413 APIC_IRQ_APIC(ih)); 414 return NULL; 415 } 416 417 return intr_create_intrid(irq, pic, pin, buf, len); 418 #else 419 return pci_intr_string(pc, ih, buf, len); 420 #endif /* !XENPV */ 421 } 422 423 static void 424 x86_pci_intx_release(pci_chipset_tag_t pc, pci_intr_handle_t *pih) 425 { 426 char intrstr_buf[INTRIDBUF]; 427 const char *intrstr; 428 429 intrstr = pci_intr_string(NULL, *pih, intrstr_buf, sizeof(intrstr_buf)); 430 mutex_enter(&cpu_lock); 431 intr_free_io_intrsource(intrstr); 432 mutex_exit(&cpu_lock); 433 434 kmem_free(pih, sizeof(*pih)); 435 } 436 437 int 438 pci_intx_alloc(const struct pci_attach_args *pa, pci_intr_handle_t **pih) 439 { 440 struct intrsource *isp; 441 pci_intr_handle_t *handle; 442 int error; 443 char intrstr_buf[INTRIDBUF]; 444 const char *intrstr; 445 446 handle = kmem_zalloc(sizeof(*handle), KM_SLEEP); 447 if (pci_intr_map(pa, handle) != 0) { 448 aprint_normal("cannot set up pci_intr_handle_t\n"); 449 error = EINVAL; 450 goto error; 451 } 452 453 /* 454 * must be the same intrstr as intr_establish_xname() 455 */ 456 intrstr = x86_pci_intx_create_intrid(pa->pa_pc, *handle, intrstr_buf, 457 sizeof(intrstr_buf)); 458 mutex_enter(&cpu_lock); 459 isp = intr_allocate_io_intrsource(intrstr); 460 mutex_exit(&cpu_lock); 461 if (isp == NULL) { 462 aprint_normal("can't allocate io_intersource\n"); 463 error = ENOMEM; 464 goto error; 465 } 466 467 *pih = handle; 468 return 0; 469 470 error: 471 kmem_free(handle, sizeof(*handle)); 472 return error; 473 } 474 475 /* 476 * Interrupt handler allocation utility. This function calls each allocation 477 * function as specified by arguments. 478 * Currently callee functions are pci_intx_alloc(), pci_msi_alloc_exact(), 479 * and pci_msix_alloc_exact(). 480 * pa : pci_attach_args 481 * ihps : interrupt handlers 482 * counts : The array of number of required interrupt handlers. 483 * It is overwritten by allocated the number of handlers. 484 * CAUTION: The size of counts[] must be PCI_INTR_TYPE_SIZE. 485 * max_type : "max" type of using interrupts. See below. 486 * e.g. 487 * If you want to use 5 MSI-X, 1 MSI, or INTx, you use "counts" as 488 * int counts[PCI_INTR_TYPE_SIZE]; 489 * counts[PCI_INTR_TYPE_MSIX] = 5; 490 * counts[PCI_INTR_TYPE_MSI] = 1; 491 * counts[PCI_INTR_TYPE_INTX] = 1; 492 * error = pci_intr_alloc(pa, ihps, counts, PCI_INTR_TYPE_MSIX); 493 * 494 * If you want to use hardware max number MSI-X or 1 MSI, 495 * and not to use INTx, you use "counts" as 496 * int counts[PCI_INTR_TYPE_SIZE]; 497 * counts[PCI_INTR_TYPE_MSIX] = -1; 498 * counts[PCI_INTR_TYPE_MSI] = 1; 499 * counts[PCI_INTR_TYPE_INTX] = 0; 500 * error = pci_intr_alloc(pa, ihps, counts, PCI_INTR_TYPE_MSIX); 501 * 502 * If you want to use 3 MSI or INTx, you can use "counts" as 503 * int counts[PCI_INTR_TYPE_SIZE]; 504 * counts[PCI_INTR_TYPE_MSI] = 3; 505 * counts[PCI_INTR_TYPE_INTX] = 1; 506 * error = pci_intr_alloc(pa, ihps, counts, PCI_INTR_TYPE_MSI); 507 * 508 * If you want to use 1 MSI or INTx (probably most general usage), 509 * you can simply use this API like 510 * below 511 * error = pci_intr_alloc(pa, ihps, NULL, 0); 512 * ^ ignored 513 */ 514 int 515 pci_intr_alloc(const struct pci_attach_args *pa, pci_intr_handle_t **ihps, 516 int *counts, pci_intr_type_t max_type) 517 { 518 int error; 519 int intx_count, msi_count, msix_count; 520 521 intx_count = msi_count = msix_count = 0; 522 if (counts == NULL) { /* simple pattern */ 523 msix_count = 1; 524 msi_count = 1; 525 intx_count = 1; 526 } else { 527 switch (max_type) { 528 case PCI_INTR_TYPE_MSIX: 529 msix_count = counts[PCI_INTR_TYPE_MSIX]; 530 /* FALLTHROUGH */ 531 case PCI_INTR_TYPE_MSI: 532 msi_count = counts[PCI_INTR_TYPE_MSI]; 533 /* FALLTHROUGH */ 534 case PCI_INTR_TYPE_INTX: 535 intx_count = counts[PCI_INTR_TYPE_INTX]; 536 break; 537 default: 538 return EINVAL; 539 } 540 } 541 542 if (counts != NULL) 543 memset(counts, 0, sizeof(counts[0]) * PCI_INTR_TYPE_SIZE); 544 error = EINVAL; 545 546 /* try MSI-X */ 547 if (msix_count == -1) /* use hardware max */ 548 msix_count = pci_msix_count(pa->pa_pc, pa->pa_tag); 549 if (msix_count > 0) { 550 error = pci_msix_alloc_exact(pa, ihps, msix_count); 551 if (error == 0) { 552 if (counts != NULL) 553 counts[PCI_INTR_TYPE_MSIX] = msix_count; 554 goto out; 555 } 556 } 557 558 /* try MSI */ 559 if (msi_count == -1) /* use hardware max */ 560 msi_count = pci_msi_count(pa->pa_pc, pa->pa_tag); 561 if (msi_count > 0) { 562 error = pci_msi_alloc_exact(pa, ihps, msi_count); 563 if (error == 0) { 564 if (counts != NULL) 565 counts[PCI_INTR_TYPE_MSI] = msi_count; 566 goto out; 567 } 568 } 569 570 /* try INTx */ 571 if (intx_count != 0) { /* The number of INTx is always 1. */ 572 error = pci_intx_alloc(pa, ihps); 573 if (error == 0) { 574 if (counts != NULL) 575 counts[PCI_INTR_TYPE_INTX] = 1; 576 } 577 } 578 579 out: 580 return error; 581 } 582 583 void 584 pci_intr_release(pci_chipset_tag_t pc, pci_intr_handle_t *pih, int count) 585 { 586 if (pih == NULL) 587 return; 588 589 if (INT_VIA_MSI(*pih)) { 590 if (MSI_INT_IS_MSIX(*pih)) 591 return x86_pci_msix_release(pc, pih, count); 592 else 593 return x86_pci_msi_release(pc, pih, count); 594 } else { 595 KASSERT(count == 1); 596 return x86_pci_intx_release(pc, pih); 597 } 598 599 } 600 #endif /* __HAVE_PCI_MSI_MSIX */ 601 #endif /* NIOAPIC > 0 */ 602