1 /* $NetBSD: pci_intr_machdep.c,v 1.18 2010/12/20 00:25:46 matt Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998, 2009 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved. 35 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 1. Redistributions of source code must retain the above copyright 41 * notice, this list of conditions and the following disclaimer. 42 * 2. Redistributions in binary form must reproduce the above copyright 43 * notice, this list of conditions and the following disclaimer in the 44 * documentation and/or other materials provided with the distribution. 45 * 3. All advertising materials mentioning features or use of this software 46 * must display the following acknowledgement: 47 * This product includes software developed by Charles M. Hannum. 48 * 4. The name of the author may not be used to endorse or promote products 49 * derived from this software without specific prior written permission. 50 * 51 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 52 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 53 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 54 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 55 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 56 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 57 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 58 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 59 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 60 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 61 */ 62 63 /* 64 * Machine-specific functions for PCI autoconfiguration. 65 * 66 * On PCs, there are two methods of generating PCI configuration cycles. 67 * We try to detect the appropriate mechanism for this machine and set 68 * up a few function pointers to access the correct method directly. 69 * 70 * The configuration method can be hard-coded in the config file by 71 * using `options PCI_CONF_MODE=N', where `N' is the configuration mode 72 * as defined section 3.6.4.1, `Generating Configuration Cycles'. 73 */ 74 75 #include <sys/cdefs.h> 76 __KERNEL_RCSID(0, "$NetBSD: pci_intr_machdep.c,v 1.18 2010/12/20 00:25:46 matt Exp $"); 77 78 #include <sys/types.h> 79 #include <sys/param.h> 80 #include <sys/time.h> 81 #include <sys/systm.h> 82 #include <sys/errno.h> 83 #include <sys/device.h> 84 #include <sys/intr.h> 85 86 #include <dev/pci/pcivar.h> 87 88 #include "ioapic.h" 89 #include "eisa.h" 90 #include "acpica.h" 91 #include "opt_mpbios.h" 92 #include "opt_acpi.h" 93 94 #if NIOAPIC > 0 || NACPICA > 0 95 #include <machine/i82093var.h> 96 #include <machine/mpconfig.h> 97 #include <machine/mpbiosvar.h> 98 #include <machine/pic.h> 99 #endif 100 101 #ifdef MPBIOS 102 #include <machine/mpbiosvar.h> 103 #endif 104 105 #if NACPICA > 0 106 #include <machine/mpacpi.h> 107 #endif 108 109 #define MPSAFE_MASK 0x80000000 110 111 int 112 pci_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *ihp) 113 { 114 int pin = pa->pa_intrpin; 115 int line = pa->pa_intrline; 116 pci_chipset_tag_t pc; 117 #if NIOAPIC > 0 || NACPICA > 0 118 int rawpin = pa->pa_rawintrpin; 119 int bus, dev, func; 120 #endif 121 122 if ((pc = pa->pa_pc) != NULL) { 123 if ((pc->pc_present & PCI_OVERRIDE_INTR_MAP) != 0) 124 return (*pc->pc_ov->ov_intr_map)(pc->pc_ctx, pa, ihp); 125 if (pc->pc_super != NULL) { 126 struct pci_attach_args paclone = *pa; 127 paclone.pa_pc = pc->pc_super; 128 return pci_intr_map(&paclone, ihp); 129 } 130 } 131 132 if (pin == 0) { 133 /* No IRQ used. */ 134 goto bad; 135 } 136 137 *ihp = 0; 138 139 if (pin > PCI_INTERRUPT_PIN_MAX) { 140 aprint_normal("pci_intr_map: bad interrupt pin %d\n", pin); 141 goto bad; 142 } 143 144 #if NIOAPIC > 0 || NACPICA > 0 145 pci_decompose_tag(pc, pa->pa_tag, &bus, &dev, &func); 146 if (mp_busses != NULL) { 147 if (intr_find_mpmapping(bus, (dev<<2)|(rawpin-1), ihp) == 0) { 148 if ((*ihp & 0xff) == 0) 149 *ihp |= line; 150 return 0; 151 } 152 /* 153 * No explicit PCI mapping found. This is not fatal, 154 * we'll try the ISA (or possibly EISA) mappings next. 155 */ 156 } 157 #endif 158 159 /* 160 * Section 6.2.4, `Miscellaneous Functions', says that 255 means 161 * `unknown' or `no connection' on a PC. We assume that a device with 162 * `no connection' either doesn't have an interrupt (in which case the 163 * pin number should be 0, and would have been noticed above), or 164 * wasn't configured by the BIOS (in which case we punt, since there's 165 * no real way we can know how the interrupt lines are mapped in the 166 * hardware). 167 * 168 * XXX 169 * Since IRQ 0 is only used by the clock, and we can't actually be sure 170 * that the BIOS did its job, we also recognize that as meaning that 171 * the BIOS has not configured the device. 172 */ 173 if (line == 0 || line == X86_PCI_INTERRUPT_LINE_NO_CONNECTION) { 174 aprint_normal("pci_intr_map: no mapping for pin %c (line=%02x)\n", 175 '@' + pin, line); 176 goto bad; 177 } else { 178 if (line >= NUM_LEGACY_IRQS) { 179 aprint_normal("pci_intr_map: bad interrupt line %d\n", line); 180 goto bad; 181 } 182 if (line == 2) { 183 aprint_normal("pci_intr_map: changed line 2 to line 9\n"); 184 line = 9; 185 } 186 } 187 #if NIOAPIC > 0 || NACPICA > 0 188 if (mp_busses != NULL) { 189 if (intr_find_mpmapping(mp_isa_bus, line, ihp) == 0) { 190 if ((*ihp & 0xff) == 0) 191 *ihp |= line; 192 return 0; 193 } 194 #if NEISA > 0 195 if (intr_find_mpmapping(mp_eisa_bus, line, ihp) == 0) { 196 if ((*ihp & 0xff) == 0) 197 *ihp |= line; 198 return 0; 199 } 200 #endif 201 aprint_normal("pci_intr_map: bus %d dev %d func %d pin %d; line %d\n", 202 bus, dev, func, pin, line); 203 aprint_normal("pci_intr_map: no MP mapping found\n"); 204 } 205 #endif 206 207 *ihp = line; 208 return 0; 209 210 bad: 211 *ihp = -1; 212 return 1; 213 } 214 215 const char * 216 pci_intr_string(pci_chipset_tag_t pc, pci_intr_handle_t ih) 217 { 218 219 if (pc != NULL) { 220 if ((pc->pc_present & PCI_OVERRIDE_INTR_STRING) != 0) 221 return (*pc->pc_ov->ov_intr_string)(pc->pc_ctx, pc, ih); 222 if (pc->pc_super != NULL) 223 return pci_intr_string(pc->pc_super, ih); 224 } 225 226 return intr_string(ih & ~MPSAFE_MASK); 227 } 228 229 230 const struct evcnt * 231 pci_intr_evcnt(pci_chipset_tag_t pc, pci_intr_handle_t ih) 232 { 233 234 if (pc != NULL) { 235 if ((pc->pc_present & PCI_OVERRIDE_INTR_EVCNT) != 0) 236 return (*pc->pc_ov->ov_intr_evcnt)(pc->pc_ctx, pc, ih); 237 if (pc->pc_super != NULL) 238 return pci_intr_evcnt(pc->pc_super, ih); 239 } 240 241 /* XXX for now, no evcnt parent reported */ 242 return NULL; 243 } 244 245 int 246 pci_intr_setattr(pci_chipset_tag_t pc, pci_intr_handle_t *ih, 247 int attr, uint64_t data) 248 { 249 250 switch (attr) { 251 case PCI_INTR_MPSAFE: 252 if (data) { 253 *ih |= MPSAFE_MASK; 254 } else { 255 *ih &= ~MPSAFE_MASK; 256 } 257 /* XXX Set live if already mapped. */ 258 return 0; 259 default: 260 return ENODEV; 261 } 262 } 263 264 void * 265 pci_intr_establish(pci_chipset_tag_t pc, pci_intr_handle_t ih, 266 int level, int (*func)(void *), void *arg) 267 { 268 int pin, irq; 269 struct pic *pic; 270 #if NIOAPIC > 0 271 struct ioapic_softc *ioapic; 272 #endif 273 bool mpsafe; 274 275 if (pc != NULL) { 276 if ((pc->pc_present & PCI_OVERRIDE_INTR_ESTABLISH) != 0) { 277 return (*pc->pc_ov->ov_intr_establish)(pc->pc_ctx, 278 pc, ih, level, func, arg); 279 } 280 if (pc->pc_super != NULL) { 281 return pci_intr_establish(pc->pc_super, ih, level, func, 282 arg); 283 } 284 } 285 286 pic = &i8259_pic; 287 pin = irq = (ih & ~MPSAFE_MASK); 288 mpsafe = ((ih & MPSAFE_MASK) != 0); 289 290 #if NIOAPIC > 0 291 if (ih & APIC_INT_VIA_APIC) { 292 ioapic = ioapic_find(APIC_IRQ_APIC(ih)); 293 if (ioapic == NULL) { 294 aprint_normal("pci_intr_establish: bad ioapic %d\n", 295 APIC_IRQ_APIC(ih)); 296 return NULL; 297 } 298 pic = &ioapic->sc_pic; 299 pin = APIC_IRQ_PIN(ih); 300 irq = APIC_IRQ_LEGACY_IRQ(ih); 301 if (irq < 0 || irq >= NUM_LEGACY_IRQS) 302 irq = -1; 303 } 304 #endif 305 306 return intr_establish(irq, pic, pin, IST_LEVEL, level, func, arg, 307 mpsafe); 308 } 309 310 void 311 pci_intr_disestablish(pci_chipset_tag_t pc, void *cookie) 312 { 313 314 if (pc != NULL) { 315 if ((pc->pc_present & PCI_OVERRIDE_INTR_ESTABLISH) != 0) { 316 (*pc->pc_ov->ov_intr_disestablish)(pc->pc_ctx, 317 pc, cookie); 318 return; 319 } 320 if (pc->pc_super != NULL) { 321 pci_intr_disestablish(pc->pc_super, cookie); 322 return; 323 } 324 } 325 326 intr_disestablish(cookie); 327 } 328