1 /* $NetBSD: pci_intr_machdep.c,v 1.17 2010/04/28 21:27:14 dyoung Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998, 2009 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved. 35 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 1. Redistributions of source code must retain the above copyright 41 * notice, this list of conditions and the following disclaimer. 42 * 2. Redistributions in binary form must reproduce the above copyright 43 * notice, this list of conditions and the following disclaimer in the 44 * documentation and/or other materials provided with the distribution. 45 * 3. All advertising materials mentioning features or use of this software 46 * must display the following acknowledgement: 47 * This product includes software developed by Charles M. Hannum. 48 * 4. The name of the author may not be used to endorse or promote products 49 * derived from this software without specific prior written permission. 50 * 51 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 52 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 53 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 54 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 55 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 56 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 57 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 58 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 59 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 60 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 61 */ 62 63 /* 64 * Machine-specific functions for PCI autoconfiguration. 65 * 66 * On PCs, there are two methods of generating PCI configuration cycles. 67 * We try to detect the appropriate mechanism for this machine and set 68 * up a few function pointers to access the correct method directly. 69 * 70 * The configuration method can be hard-coded in the config file by 71 * using `options PCI_CONF_MODE=N', where `N' is the configuration mode 72 * as defined section 3.6.4.1, `Generating Configuration Cycles'. 73 */ 74 75 #include <sys/cdefs.h> 76 __KERNEL_RCSID(0, "$NetBSD: pci_intr_machdep.c,v 1.17 2010/04/28 21:27:14 dyoung Exp $"); 77 78 #include <sys/types.h> 79 #include <sys/param.h> 80 #include <sys/time.h> 81 #include <sys/systm.h> 82 #include <sys/errno.h> 83 #include <sys/device.h> 84 #include <sys/intr.h> 85 86 #include <uvm/uvm_extern.h> 87 88 #include <dev/pci/pcivar.h> 89 90 #include "ioapic.h" 91 #include "eisa.h" 92 #include "acpica.h" 93 #include "opt_mpbios.h" 94 #include "opt_acpi.h" 95 96 #if NIOAPIC > 0 || NACPICA > 0 97 #include <machine/i82093var.h> 98 #include <machine/mpconfig.h> 99 #include <machine/mpbiosvar.h> 100 #include <machine/pic.h> 101 #endif 102 103 #ifdef MPBIOS 104 #include <machine/mpbiosvar.h> 105 #endif 106 107 #if NACPICA > 0 108 #include <machine/mpacpi.h> 109 #endif 110 111 #define MPSAFE_MASK 0x80000000 112 113 int 114 pci_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *ihp) 115 { 116 int pin = pa->pa_intrpin; 117 int line = pa->pa_intrline; 118 pci_chipset_tag_t pc; 119 #if NIOAPIC > 0 || NACPICA > 0 120 int rawpin = pa->pa_rawintrpin; 121 int bus, dev, func; 122 #endif 123 124 if ((pc = pa->pa_pc) != NULL) { 125 if ((pc->pc_present & PCI_OVERRIDE_INTR_MAP) != 0) 126 return (*pc->pc_ov->ov_intr_map)(pc->pc_ctx, pa, ihp); 127 if (pc->pc_super != NULL) { 128 struct pci_attach_args paclone = *pa; 129 paclone.pa_pc = pc->pc_super; 130 return pci_intr_map(&paclone, ihp); 131 } 132 } 133 134 if (pin == 0) { 135 /* No IRQ used. */ 136 goto bad; 137 } 138 139 *ihp = 0; 140 141 if (pin > PCI_INTERRUPT_PIN_MAX) { 142 aprint_normal("pci_intr_map: bad interrupt pin %d\n", pin); 143 goto bad; 144 } 145 146 #if NIOAPIC > 0 || NACPICA > 0 147 pci_decompose_tag(pc, pa->pa_tag, &bus, &dev, &func); 148 if (mp_busses != NULL) { 149 if (intr_find_mpmapping(bus, (dev<<2)|(rawpin-1), ihp) == 0) { 150 if ((*ihp & 0xff) == 0) 151 *ihp |= line; 152 return 0; 153 } 154 /* 155 * No explicit PCI mapping found. This is not fatal, 156 * we'll try the ISA (or possibly EISA) mappings next. 157 */ 158 } 159 #endif 160 161 /* 162 * Section 6.2.4, `Miscellaneous Functions', says that 255 means 163 * `unknown' or `no connection' on a PC. We assume that a device with 164 * `no connection' either doesn't have an interrupt (in which case the 165 * pin number should be 0, and would have been noticed above), or 166 * wasn't configured by the BIOS (in which case we punt, since there's 167 * no real way we can know how the interrupt lines are mapped in the 168 * hardware). 169 * 170 * XXX 171 * Since IRQ 0 is only used by the clock, and we can't actually be sure 172 * that the BIOS did its job, we also recognize that as meaning that 173 * the BIOS has not configured the device. 174 */ 175 if (line == 0 || line == X86_PCI_INTERRUPT_LINE_NO_CONNECTION) { 176 aprint_normal("pci_intr_map: no mapping for pin %c (line=%02x)\n", 177 '@' + pin, line); 178 goto bad; 179 } else { 180 if (line >= NUM_LEGACY_IRQS) { 181 aprint_normal("pci_intr_map: bad interrupt line %d\n", line); 182 goto bad; 183 } 184 if (line == 2) { 185 aprint_normal("pci_intr_map: changed line 2 to line 9\n"); 186 line = 9; 187 } 188 } 189 #if NIOAPIC > 0 || NACPICA > 0 190 if (mp_busses != NULL) { 191 if (intr_find_mpmapping(mp_isa_bus, line, ihp) == 0) { 192 if ((*ihp & 0xff) == 0) 193 *ihp |= line; 194 return 0; 195 } 196 #if NEISA > 0 197 if (intr_find_mpmapping(mp_eisa_bus, line, ihp) == 0) { 198 if ((*ihp & 0xff) == 0) 199 *ihp |= line; 200 return 0; 201 } 202 #endif 203 aprint_normal("pci_intr_map: bus %d dev %d func %d pin %d; line %d\n", 204 bus, dev, func, pin, line); 205 aprint_normal("pci_intr_map: no MP mapping found\n"); 206 } 207 #endif 208 209 *ihp = line; 210 return 0; 211 212 bad: 213 *ihp = -1; 214 return 1; 215 } 216 217 const char * 218 pci_intr_string(pci_chipset_tag_t pc, pci_intr_handle_t ih) 219 { 220 221 if (pc != NULL) { 222 if ((pc->pc_present & PCI_OVERRIDE_INTR_STRING) != 0) 223 return (*pc->pc_ov->ov_intr_string)(pc->pc_ctx, pc, ih); 224 if (pc->pc_super != NULL) 225 return pci_intr_string(pc->pc_super, ih); 226 } 227 228 return intr_string(ih & ~MPSAFE_MASK); 229 } 230 231 232 const struct evcnt * 233 pci_intr_evcnt(pci_chipset_tag_t pc, pci_intr_handle_t ih) 234 { 235 236 if (pc != NULL) { 237 if ((pc->pc_present & PCI_OVERRIDE_INTR_EVCNT) != 0) 238 return (*pc->pc_ov->ov_intr_evcnt)(pc->pc_ctx, pc, ih); 239 if (pc->pc_super != NULL) 240 return pci_intr_evcnt(pc->pc_super, ih); 241 } 242 243 /* XXX for now, no evcnt parent reported */ 244 return NULL; 245 } 246 247 int 248 pci_intr_setattr(pci_chipset_tag_t pc, pci_intr_handle_t *ih, 249 int attr, uint64_t data) 250 { 251 252 switch (attr) { 253 case PCI_INTR_MPSAFE: 254 if (data) { 255 *ih |= MPSAFE_MASK; 256 } else { 257 *ih &= ~MPSAFE_MASK; 258 } 259 /* XXX Set live if already mapped. */ 260 return 0; 261 default: 262 return ENODEV; 263 } 264 } 265 266 void * 267 pci_intr_establish(pci_chipset_tag_t pc, pci_intr_handle_t ih, 268 int level, int (*func)(void *), void *arg) 269 { 270 int pin, irq; 271 struct pic *pic; 272 #if NIOAPIC > 0 273 struct ioapic_softc *ioapic; 274 #endif 275 bool mpsafe; 276 277 if (pc != NULL) { 278 if ((pc->pc_present & PCI_OVERRIDE_INTR_ESTABLISH) != 0) { 279 return (*pc->pc_ov->ov_intr_establish)(pc->pc_ctx, 280 pc, ih, level, func, arg); 281 } 282 if (pc->pc_super != NULL) { 283 return pci_intr_establish(pc->pc_super, ih, level, func, 284 arg); 285 } 286 } 287 288 pic = &i8259_pic; 289 pin = irq = (ih & ~MPSAFE_MASK); 290 mpsafe = ((ih & MPSAFE_MASK) != 0); 291 292 #if NIOAPIC > 0 293 if (ih & APIC_INT_VIA_APIC) { 294 ioapic = ioapic_find(APIC_IRQ_APIC(ih)); 295 if (ioapic == NULL) { 296 aprint_normal("pci_intr_establish: bad ioapic %d\n", 297 APIC_IRQ_APIC(ih)); 298 return NULL; 299 } 300 pic = &ioapic->sc_pic; 301 pin = APIC_IRQ_PIN(ih); 302 irq = APIC_IRQ_LEGACY_IRQ(ih); 303 if (irq < 0 || irq >= NUM_LEGACY_IRQS) 304 irq = -1; 305 } 306 #endif 307 308 return intr_establish(irq, pic, pin, IST_LEVEL, level, func, arg, 309 mpsafe); 310 } 311 312 void 313 pci_intr_disestablish(pci_chipset_tag_t pc, void *cookie) 314 { 315 316 if (pc != NULL) { 317 if ((pc->pc_present & PCI_OVERRIDE_INTR_ESTABLISH) != 0) { 318 (*pc->pc_ov->ov_intr_disestablish)(pc->pc_ctx, 319 pc, cookie); 320 return; 321 } 322 if (pc->pc_super != NULL) { 323 pci_intr_disestablish(pc->pc_super, cookie); 324 return; 325 } 326 } 327 328 intr_disestablish(cookie); 329 } 330