1 /* $NetBSD: pci_intr_machdep.c,v 1.23 2011/08/29 22:41:52 dyoung Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998, 2009 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved. 35 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 1. Redistributions of source code must retain the above copyright 41 * notice, this list of conditions and the following disclaimer. 42 * 2. Redistributions in binary form must reproduce the above copyright 43 * notice, this list of conditions and the following disclaimer in the 44 * documentation and/or other materials provided with the distribution. 45 * 3. All advertising materials mentioning features or use of this software 46 * must display the following acknowledgement: 47 * This product includes software developed by Charles M. Hannum. 48 * 4. The name of the author may not be used to endorse or promote products 49 * derived from this software without specific prior written permission. 50 * 51 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 52 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 53 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 54 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 55 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 56 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 57 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 58 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 59 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 60 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 61 */ 62 63 /* 64 * Machine-specific functions for PCI autoconfiguration. 65 * 66 * On PCs, there are two methods of generating PCI configuration cycles. 67 * We try to detect the appropriate mechanism for this machine and set 68 * up a few function pointers to access the correct method directly. 69 * 70 * The configuration method can be hard-coded in the config file by 71 * using `options PCI_CONF_MODE=N', where `N' is the configuration mode 72 * as defined section 3.6.4.1, `Generating Configuration Cycles'. 73 */ 74 75 #include <sys/cdefs.h> 76 __KERNEL_RCSID(0, "$NetBSD: pci_intr_machdep.c,v 1.23 2011/08/29 22:41:52 dyoung Exp $"); 77 78 #include <sys/types.h> 79 #include <sys/param.h> 80 #include <sys/time.h> 81 #include <sys/systm.h> 82 #include <sys/errno.h> 83 #include <sys/device.h> 84 #include <sys/intr.h> 85 #include <sys/malloc.h> 86 87 #include <dev/pci/pcivar.h> 88 89 #include "ioapic.h" 90 #include "eisa.h" 91 #include "acpica.h" 92 #include "opt_mpbios.h" 93 #include "opt_acpi.h" 94 95 #if NIOAPIC > 0 || NACPICA > 0 96 #include <machine/i82093reg.h> 97 #include <machine/i82093var.h> 98 #include <machine/mpconfig.h> 99 #include <machine/mpbiosvar.h> 100 #include <machine/pic.h> 101 #endif 102 103 #ifdef MPBIOS 104 #include <machine/mpbiosvar.h> 105 #endif 106 107 #if NACPICA > 0 108 #include <machine/mpacpi.h> 109 #endif 110 111 #define MPSAFE_MASK 0x80000000 112 113 int 114 pci_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp) 115 { 116 int pin = pa->pa_intrpin; 117 int line = pa->pa_intrline; 118 pci_chipset_tag_t ipc, pc = pa->pa_pc; 119 #if NIOAPIC > 0 || NACPICA > 0 120 int rawpin = pa->pa_rawintrpin; 121 int bus, dev, func; 122 #endif 123 124 for (ipc = pc; ipc != NULL; ipc = ipc->pc_super) { 125 if ((ipc->pc_present & PCI_OVERRIDE_INTR_MAP) == 0) 126 continue; 127 return (*ipc->pc_ov->ov_intr_map)(ipc->pc_ctx, pa, ihp); 128 } 129 130 if (pin == 0) { 131 /* No IRQ used. */ 132 goto bad; 133 } 134 135 *ihp = 0; 136 137 if (pin > PCI_INTERRUPT_PIN_MAX) { 138 aprint_normal("pci_intr_map: bad interrupt pin %d\n", pin); 139 goto bad; 140 } 141 142 #if NIOAPIC > 0 || NACPICA > 0 143 pci_decompose_tag(pc, pa->pa_tag, &bus, &dev, &func); 144 if (mp_busses != NULL) { 145 if (intr_find_mpmapping(bus, (dev<<2)|(rawpin-1), ihp) == 0) { 146 if ((*ihp & 0xff) == 0) 147 *ihp |= line; 148 return 0; 149 } 150 /* 151 * No explicit PCI mapping found. This is not fatal, 152 * we'll try the ISA (or possibly EISA) mappings next. 153 */ 154 } 155 #endif 156 157 /* 158 * Section 6.2.4, `Miscellaneous Functions', says that 255 means 159 * `unknown' or `no connection' on a PC. We assume that a device with 160 * `no connection' either doesn't have an interrupt (in which case the 161 * pin number should be 0, and would have been noticed above), or 162 * wasn't configured by the BIOS (in which case we punt, since there's 163 * no real way we can know how the interrupt lines are mapped in the 164 * hardware). 165 * 166 * XXX 167 * Since IRQ 0 is only used by the clock, and we can't actually be sure 168 * that the BIOS did its job, we also recognize that as meaning that 169 * the BIOS has not configured the device. 170 */ 171 if (line == 0 || line == X86_PCI_INTERRUPT_LINE_NO_CONNECTION) { 172 aprint_normal("pci_intr_map: no mapping for pin %c (line=%02x)\n", 173 '@' + pin, line); 174 goto bad; 175 } else { 176 if (line >= NUM_LEGACY_IRQS) { 177 aprint_normal("pci_intr_map: bad interrupt line %d\n", line); 178 goto bad; 179 } 180 if (line == 2) { 181 aprint_normal("pci_intr_map: changed line 2 to line 9\n"); 182 line = 9; 183 } 184 } 185 #if NIOAPIC > 0 || NACPICA > 0 186 if (mp_busses != NULL) { 187 if (intr_find_mpmapping(mp_isa_bus, line, ihp) == 0) { 188 if ((*ihp & 0xff) == 0) 189 *ihp |= line; 190 return 0; 191 } 192 #if NEISA > 0 193 if (intr_find_mpmapping(mp_eisa_bus, line, ihp) == 0) { 194 if ((*ihp & 0xff) == 0) 195 *ihp |= line; 196 return 0; 197 } 198 #endif 199 aprint_normal("pci_intr_map: bus %d dev %d func %d pin %d; line %d\n", 200 bus, dev, func, pin, line); 201 aprint_normal("pci_intr_map: no MP mapping found\n"); 202 } 203 #endif 204 205 *ihp = line; 206 return 0; 207 208 bad: 209 *ihp = -1; 210 return 1; 211 } 212 213 const char * 214 pci_intr_string(pci_chipset_tag_t pc, pci_intr_handle_t ih) 215 { 216 pci_chipset_tag_t ipc; 217 218 for (ipc = pc; ipc != NULL; ipc = ipc->pc_super) { 219 if ((ipc->pc_present & PCI_OVERRIDE_INTR_STRING) == 0) 220 continue; 221 return (*ipc->pc_ov->ov_intr_string)(ipc->pc_ctx, pc, ih); 222 } 223 224 return intr_string(ih & ~MPSAFE_MASK); 225 } 226 227 228 const struct evcnt * 229 pci_intr_evcnt(pci_chipset_tag_t pc, pci_intr_handle_t ih) 230 { 231 pci_chipset_tag_t ipc; 232 233 for (ipc = pc; ipc != NULL; ipc = ipc->pc_super) { 234 if ((ipc->pc_present & PCI_OVERRIDE_INTR_EVCNT) == 0) 235 continue; 236 return (*ipc->pc_ov->ov_intr_evcnt)(ipc->pc_ctx, pc, ih); 237 } 238 239 /* XXX for now, no evcnt parent reported */ 240 return NULL; 241 } 242 243 int 244 pci_intr_setattr(pci_chipset_tag_t pc, pci_intr_handle_t *ih, 245 int attr, uint64_t data) 246 { 247 248 switch (attr) { 249 case PCI_INTR_MPSAFE: 250 if (data) { 251 *ih |= MPSAFE_MASK; 252 } else { 253 *ih &= ~MPSAFE_MASK; 254 } 255 /* XXX Set live if already mapped. */ 256 return 0; 257 default: 258 return ENODEV; 259 } 260 } 261 262 void * 263 pci_intr_establish(pci_chipset_tag_t pc, pci_intr_handle_t ih, 264 int level, int (*func)(void *), void *arg) 265 { 266 int pin, irq; 267 struct pic *pic; 268 #if NIOAPIC > 0 269 struct ioapic_softc *ioapic; 270 #endif 271 bool mpsafe; 272 pci_chipset_tag_t ipc; 273 274 for (ipc = pc; ipc != NULL; ipc = ipc->pc_super) { 275 if ((ipc->pc_present & PCI_OVERRIDE_INTR_ESTABLISH) == 0) 276 continue; 277 return (*ipc->pc_ov->ov_intr_establish)(ipc->pc_ctx, 278 pc, ih, level, func, arg); 279 } 280 281 pic = &i8259_pic; 282 pin = irq = (ih & ~MPSAFE_MASK); 283 mpsafe = ((ih & MPSAFE_MASK) != 0); 284 285 #if NIOAPIC > 0 286 if (ih & APIC_INT_VIA_APIC) { 287 ioapic = ioapic_find(APIC_IRQ_APIC(ih)); 288 if (ioapic == NULL) { 289 aprint_normal("pci_intr_establish: bad ioapic %d\n", 290 APIC_IRQ_APIC(ih)); 291 return NULL; 292 } 293 pic = &ioapic->sc_pic; 294 pin = APIC_IRQ_PIN(ih); 295 irq = APIC_IRQ_LEGACY_IRQ(ih); 296 if (irq < 0 || irq >= NUM_LEGACY_IRQS) 297 irq = -1; 298 } 299 #endif 300 301 return intr_establish(irq, pic, pin, IST_LEVEL, level, func, arg, 302 mpsafe); 303 } 304 305 void 306 pci_intr_disestablish(pci_chipset_tag_t pc, void *cookie) 307 { 308 pci_chipset_tag_t ipc; 309 310 for (ipc = pc; ipc != NULL; ipc = ipc->pc_super) { 311 if ((ipc->pc_present & PCI_OVERRIDE_INTR_DISESTABLISH) == 0) 312 continue; 313 (*ipc->pc_ov->ov_intr_disestablish)(ipc->pc_ctx, pc, cookie); 314 return; 315 } 316 317 intr_disestablish(cookie); 318 } 319 320 #if NIOAPIC > 0 321 /* 322 * experimental support for MSI, does support a single vector, 323 * no MSI-X, 8-bit APIC IDs 324 * (while it doesn't need the ioapic technically, it borrows 325 * from its kernel support) 326 */ 327 328 /* dummies, needed by common intr_establish code */ 329 static void 330 msipic_hwmask(struct pic *pic, int pin) 331 { 332 } 333 static void 334 msipic_addroute(struct pic *pic, struct cpu_info *ci, 335 int pin, int vec, int type) 336 { 337 } 338 339 static struct pic msi_pic = { 340 .pic_name = "msi", 341 .pic_type = PIC_SOFT, 342 .pic_vecbase = 0, 343 .pic_apicid = 0, 344 .pic_lock = __SIMPLELOCK_UNLOCKED, 345 .pic_hwmask = msipic_hwmask, 346 .pic_hwunmask = msipic_hwmask, 347 .pic_addroute = msipic_addroute, 348 .pic_delroute = msipic_addroute, 349 .pic_edge_stubs = ioapic_edge_stubs, 350 }; 351 352 struct msi_hdl { 353 struct intrhand *ih; 354 pci_chipset_tag_t pc; 355 pcitag_t tag; 356 int co; 357 }; 358 359 void * 360 pci_msi_establish(struct pci_attach_args *pa, int level, 361 int (*func)(void *), void *arg) 362 { 363 int co; 364 struct intrhand *ih; 365 struct msi_hdl *msih; 366 struct cpu_info *ci; 367 struct intrsource *is; 368 pcireg_t reg; 369 370 if (!pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_MSI, &co, 0)) 371 return NULL; 372 373 ih = intr_establish(-1, &msi_pic, -1, IST_EDGE, level, func, arg, 0); 374 if (ih == NULL) 375 return NULL; 376 377 msih = malloc(sizeof(*msih), M_DEVBUF, M_WAITOK); 378 msih->ih = ih; 379 msih->pc = pa->pa_pc; 380 msih->tag = pa->pa_tag; 381 msih->co = co; 382 383 ci = ih->ih_cpu; 384 is = ci->ci_isources[ih->ih_slot]; 385 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, co + PCI_MSI_CTL); 386 pci_conf_write(pa->pa_pc, pa->pa_tag, co + PCI_MSI_MADDR64_LO, 387 IOAPIC_MSIADDR_BASE | 388 __SHIFTIN(ci->ci_cpuid, IOAPIC_MSIADDR_DSTID_MASK)); 389 if (reg & PCI_MSI_CTL_64BIT_ADDR) { 390 pci_conf_write(pa->pa_pc, pa->pa_tag, co + PCI_MSI_MADDR64_HI, 391 0); 392 /* XXX according to the manual, ASSERT is unnecessary if 393 * EDGE 394 */ 395 pci_conf_write(pa->pa_pc, pa->pa_tag, co + PCI_MSI_MDATA64, 396 __SHIFTIN(is->is_idtvec, IOAPIC_MSIDATA_VECTOR_MASK) | 397 IOAPIC_MSIDATA_TRGMODE_EDGE | IOAPIC_MSIDATA_LEVEL_ASSERT | 398 IOAPIC_MSIDATA_DM_FIXED); 399 } else { 400 /* XXX according to the manual, ASSERT is unnecessary if 401 * EDGE 402 */ 403 pci_conf_write(pa->pa_pc, pa->pa_tag, co + PCI_MSI_MDATA, 404 __SHIFTIN(is->is_idtvec, IOAPIC_MSIDATA_VECTOR_MASK) | 405 IOAPIC_MSIDATA_TRGMODE_EDGE | IOAPIC_MSIDATA_LEVEL_ASSERT | 406 IOAPIC_MSIDATA_DM_FIXED); 407 } 408 pci_conf_write(pa->pa_pc, pa->pa_tag, co + PCI_MSI_CTL, 409 PCI_MSI_CTL_MSI_ENABLE); 410 return msih; 411 } 412 413 void 414 pci_msi_disestablish(void *ih) 415 { 416 struct msi_hdl *msih = ih; 417 418 pci_conf_write(msih->pc, msih->tag, msih->co + PCI_MSI_CTL, 0); 419 intr_disestablish(msih->ih); 420 free(msih, M_DEVBUF); 421 } 422 #endif 423