1 /* $NetBSD: pci_intr_machdep.c,v 1.26 2013/01/26 17:37:39 dyoung Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998, 2009 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved. 35 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 1. Redistributions of source code must retain the above copyright 41 * notice, this list of conditions and the following disclaimer. 42 * 2. Redistributions in binary form must reproduce the above copyright 43 * notice, this list of conditions and the following disclaimer in the 44 * documentation and/or other materials provided with the distribution. 45 * 3. All advertising materials mentioning features or use of this software 46 * must display the following acknowledgement: 47 * This product includes software developed by Charles M. Hannum. 48 * 4. The name of the author may not be used to endorse or promote products 49 * derived from this software without specific prior written permission. 50 * 51 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 52 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 53 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 54 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 55 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 56 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 57 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 58 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 59 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 60 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 61 */ 62 63 /* 64 * Machine-specific functions for PCI autoconfiguration. 65 * 66 * On PCs, there are two methods of generating PCI configuration cycles. 67 * We try to detect the appropriate mechanism for this machine and set 68 * up a few function pointers to access the correct method directly. 69 * 70 * The configuration method can be hard-coded in the config file by 71 * using `options PCI_CONF_MODE=N', where `N' is the configuration mode 72 * as defined section 3.6.4.1, `Generating Configuration Cycles'. 73 */ 74 75 #include <sys/cdefs.h> 76 __KERNEL_RCSID(0, "$NetBSD: pci_intr_machdep.c,v 1.26 2013/01/26 17:37:39 dyoung Exp $"); 77 78 #include <sys/types.h> 79 #include <sys/param.h> 80 #include <sys/time.h> 81 #include <sys/systm.h> 82 #include <sys/errno.h> 83 #include <sys/device.h> 84 #include <sys/intr.h> 85 #include <sys/malloc.h> 86 87 #include <dev/pci/pcivar.h> 88 89 #include "ioapic.h" 90 #include "eisa.h" 91 #include "acpica.h" 92 #include "opt_mpbios.h" 93 #include "opt_acpi.h" 94 95 #include <machine/i82489reg.h> 96 97 #if NIOAPIC > 0 || NACPICA > 0 98 #include <machine/i82093reg.h> 99 #include <machine/i82093var.h> 100 #include <machine/mpconfig.h> 101 #include <machine/mpbiosvar.h> 102 #include <machine/pic.h> 103 #endif 104 105 #ifdef MPBIOS 106 #include <machine/mpbiosvar.h> 107 #endif 108 109 #if NACPICA > 0 110 #include <machine/mpacpi.h> 111 #endif 112 113 #define MPSAFE_MASK 0x80000000 114 115 int 116 pci_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp) 117 { 118 int pin = pa->pa_intrpin; 119 int line = pa->pa_intrline; 120 pci_chipset_tag_t ipc, pc = pa->pa_pc; 121 #if NIOAPIC > 0 || NACPICA > 0 122 int rawpin = pa->pa_rawintrpin; 123 int bus, dev, func; 124 #endif 125 126 for (ipc = pc; ipc != NULL; ipc = ipc->pc_super) { 127 if ((ipc->pc_present & PCI_OVERRIDE_INTR_MAP) == 0) 128 continue; 129 return (*ipc->pc_ov->ov_intr_map)(ipc->pc_ctx, pa, ihp); 130 } 131 132 if (pin == 0) { 133 /* No IRQ used. */ 134 goto bad; 135 } 136 137 *ihp = 0; 138 139 if (pin > PCI_INTERRUPT_PIN_MAX) { 140 aprint_normal("pci_intr_map: bad interrupt pin %d\n", pin); 141 goto bad; 142 } 143 144 #if NIOAPIC > 0 || NACPICA > 0 145 KASSERT(rawpin >= PCI_INTERRUPT_PIN_A); 146 KASSERT(rawpin <= PCI_INTERRUPT_PIN_D); 147 pci_decompose_tag(pc, pa->pa_tag, &bus, &dev, &func); 148 if (mp_busses != NULL) { 149 /* 150 * Note: PCI_INTERRUPT_PIN_A == 1 where intr_find_mpmapping 151 * wants pci bus_pin encoding which uses INT_A == 0. 152 */ 153 if (intr_find_mpmapping(bus, 154 (dev << 2) | (rawpin - PCI_INTERRUPT_PIN_A), ihp) == 0) { 155 if (APIC_IRQ_LEGACY_IRQ(*ihp) == 0) 156 *ihp |= line; 157 return 0; 158 } 159 /* 160 * No explicit PCI mapping found. This is not fatal, 161 * we'll try the ISA (or possibly EISA) mappings next. 162 */ 163 } 164 #endif 165 166 /* 167 * Section 6.2.4, `Miscellaneous Functions', says that 255 means 168 * `unknown' or `no connection' on a PC. We assume that a device with 169 * `no connection' either doesn't have an interrupt (in which case the 170 * pin number should be 0, and would have been noticed above), or 171 * wasn't configured by the BIOS (in which case we punt, since there's 172 * no real way we can know how the interrupt lines are mapped in the 173 * hardware). 174 * 175 * XXX 176 * Since IRQ 0 is only used by the clock, and we can't actually be sure 177 * that the BIOS did its job, we also recognize that as meaning that 178 * the BIOS has not configured the device. 179 */ 180 if (line == 0 || line == X86_PCI_INTERRUPT_LINE_NO_CONNECTION) { 181 aprint_normal("pci_intr_map: no mapping for pin %c (line=%02x)\n", 182 '@' + pin, line); 183 goto bad; 184 } else { 185 if (line >= NUM_LEGACY_IRQS) { 186 aprint_normal("pci_intr_map: bad interrupt line %d\n", line); 187 goto bad; 188 } 189 if (line == 2) { 190 aprint_normal("pci_intr_map: changed line 2 to line 9\n"); 191 line = 9; 192 } 193 } 194 #if NIOAPIC > 0 || NACPICA > 0 195 if (mp_busses != NULL) { 196 if (intr_find_mpmapping(mp_isa_bus, line, ihp) == 0) { 197 if ((*ihp & 0xff) == 0) 198 *ihp |= line; 199 return 0; 200 } 201 #if NEISA > 0 202 if (intr_find_mpmapping(mp_eisa_bus, line, ihp) == 0) { 203 if ((*ihp & 0xff) == 0) 204 *ihp |= line; 205 return 0; 206 } 207 #endif 208 aprint_normal("pci_intr_map: bus %d dev %d func %d pin %d; line %d\n", 209 bus, dev, func, pin, line); 210 aprint_normal("pci_intr_map: no MP mapping found\n"); 211 } 212 #endif 213 214 *ihp = line; 215 return 0; 216 217 bad: 218 *ihp = -1; 219 return 1; 220 } 221 222 const char * 223 pci_intr_string(pci_chipset_tag_t pc, pci_intr_handle_t ih) 224 { 225 pci_chipset_tag_t ipc; 226 227 for (ipc = pc; ipc != NULL; ipc = ipc->pc_super) { 228 if ((ipc->pc_present & PCI_OVERRIDE_INTR_STRING) == 0) 229 continue; 230 return (*ipc->pc_ov->ov_intr_string)(ipc->pc_ctx, pc, ih); 231 } 232 233 return intr_string(ih & ~MPSAFE_MASK); 234 } 235 236 237 const struct evcnt * 238 pci_intr_evcnt(pci_chipset_tag_t pc, pci_intr_handle_t ih) 239 { 240 pci_chipset_tag_t ipc; 241 242 for (ipc = pc; ipc != NULL; ipc = ipc->pc_super) { 243 if ((ipc->pc_present & PCI_OVERRIDE_INTR_EVCNT) == 0) 244 continue; 245 return (*ipc->pc_ov->ov_intr_evcnt)(ipc->pc_ctx, pc, ih); 246 } 247 248 /* XXX for now, no evcnt parent reported */ 249 return NULL; 250 } 251 252 int 253 pci_intr_setattr(pci_chipset_tag_t pc, pci_intr_handle_t *ih, 254 int attr, uint64_t data) 255 { 256 257 switch (attr) { 258 case PCI_INTR_MPSAFE: 259 if (data) { 260 *ih |= MPSAFE_MASK; 261 } else { 262 *ih &= ~MPSAFE_MASK; 263 } 264 /* XXX Set live if already mapped. */ 265 return 0; 266 default: 267 return ENODEV; 268 } 269 } 270 271 void * 272 pci_intr_establish(pci_chipset_tag_t pc, pci_intr_handle_t ih, 273 int level, int (*func)(void *), void *arg) 274 { 275 int pin, irq; 276 struct pic *pic; 277 #if NIOAPIC > 0 278 struct ioapic_softc *ioapic; 279 #endif 280 bool mpsafe; 281 pci_chipset_tag_t ipc; 282 283 for (ipc = pc; ipc != NULL; ipc = ipc->pc_super) { 284 if ((ipc->pc_present & PCI_OVERRIDE_INTR_ESTABLISH) == 0) 285 continue; 286 return (*ipc->pc_ov->ov_intr_establish)(ipc->pc_ctx, 287 pc, ih, level, func, arg); 288 } 289 290 pic = &i8259_pic; 291 pin = irq = (ih & ~MPSAFE_MASK); 292 mpsafe = ((ih & MPSAFE_MASK) != 0); 293 294 #if NIOAPIC > 0 295 if (ih & APIC_INT_VIA_APIC) { 296 ioapic = ioapic_find(APIC_IRQ_APIC(ih)); 297 if (ioapic == NULL) { 298 aprint_normal("pci_intr_establish: bad ioapic %d\n", 299 APIC_IRQ_APIC(ih)); 300 return NULL; 301 } 302 pic = &ioapic->sc_pic; 303 pin = APIC_IRQ_PIN(ih); 304 irq = APIC_IRQ_LEGACY_IRQ(ih); 305 if (irq < 0 || irq >= NUM_LEGACY_IRQS) 306 irq = -1; 307 } 308 #endif 309 310 return intr_establish(irq, pic, pin, IST_LEVEL, level, func, arg, 311 mpsafe); 312 } 313 314 void 315 pci_intr_disestablish(pci_chipset_tag_t pc, void *cookie) 316 { 317 pci_chipset_tag_t ipc; 318 319 for (ipc = pc; ipc != NULL; ipc = ipc->pc_super) { 320 if ((ipc->pc_present & PCI_OVERRIDE_INTR_DISESTABLISH) == 0) 321 continue; 322 (*ipc->pc_ov->ov_intr_disestablish)(ipc->pc_ctx, pc, cookie); 323 return; 324 } 325 326 intr_disestablish(cookie); 327 } 328 329 #if NIOAPIC > 0 330 /* 331 * experimental support for MSI, does support a single vector, 332 * no MSI-X, 8-bit APIC IDs 333 * (while it doesn't need the ioapic technically, it borrows 334 * from its kernel support) 335 */ 336 337 /* dummies, needed by common intr_establish code */ 338 static void 339 msipic_hwmask(struct pic *pic, int pin) 340 { 341 } 342 static void 343 msipic_addroute(struct pic *pic, struct cpu_info *ci, 344 int pin, int vec, int type) 345 { 346 } 347 348 static struct pic msi_pic = { 349 .pic_name = "msi", 350 .pic_type = PIC_SOFT, 351 .pic_vecbase = 0, 352 .pic_apicid = 0, 353 .pic_lock = __SIMPLELOCK_UNLOCKED, 354 .pic_hwmask = msipic_hwmask, 355 .pic_hwunmask = msipic_hwmask, 356 .pic_addroute = msipic_addroute, 357 .pic_delroute = msipic_addroute, 358 .pic_edge_stubs = ioapic_edge_stubs, 359 }; 360 361 struct msi_hdl { 362 struct intrhand *ih; 363 pci_chipset_tag_t pc; 364 pcitag_t tag; 365 int co; 366 }; 367 368 void * 369 pci_msi_establish(struct pci_attach_args *pa, int level, 370 int (*func)(void *), void *arg) 371 { 372 int co; 373 struct intrhand *ih; 374 struct msi_hdl *msih; 375 struct cpu_info *ci; 376 struct intrsource *is; 377 pcireg_t reg; 378 379 if (!pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_MSI, &co, 0)) 380 return NULL; 381 382 ih = intr_establish(-1, &msi_pic, -1, IST_EDGE, level, func, arg, 0); 383 if (ih == NULL) 384 return NULL; 385 386 msih = malloc(sizeof(*msih), M_DEVBUF, M_WAITOK); 387 msih->ih = ih; 388 msih->pc = pa->pa_pc; 389 msih->tag = pa->pa_tag; 390 msih->co = co; 391 392 ci = ih->ih_cpu; 393 is = ci->ci_isources[ih->ih_slot]; 394 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, co + PCI_MSI_CTL); 395 pci_conf_write(pa->pa_pc, pa->pa_tag, co + PCI_MSI_MADDR64_LO, 396 LAPIC_MSIADDR_BASE | 397 __SHIFTIN(ci->ci_cpuid, LAPIC_MSIADDR_DSTID_MASK)); 398 if (reg & PCI_MSI_CTL_64BIT_ADDR) { 399 pci_conf_write(pa->pa_pc, pa->pa_tag, co + PCI_MSI_MADDR64_HI, 400 0); 401 /* XXX according to the manual, ASSERT is unnecessary if 402 * EDGE 403 */ 404 pci_conf_write(pa->pa_pc, pa->pa_tag, co + PCI_MSI_MDATA64, 405 __SHIFTIN(is->is_idtvec, LAPIC_MSIDATA_VECTOR_MASK) | 406 LAPIC_MSIDATA_TRGMODE_EDGE | LAPIC_MSIDATA_LEVEL_ASSERT | 407 LAPIC_MSIDATA_DM_FIXED); 408 } else { 409 /* XXX according to the manual, ASSERT is unnecessary if 410 * EDGE 411 */ 412 pci_conf_write(pa->pa_pc, pa->pa_tag, co + PCI_MSI_MDATA, 413 __SHIFTIN(is->is_idtvec, LAPIC_MSIDATA_VECTOR_MASK) | 414 LAPIC_MSIDATA_TRGMODE_EDGE | LAPIC_MSIDATA_LEVEL_ASSERT | 415 LAPIC_MSIDATA_DM_FIXED); 416 } 417 pci_conf_write(pa->pa_pc, pa->pa_tag, co + PCI_MSI_CTL, 418 PCI_MSI_CTL_MSI_ENABLE); 419 return msih; 420 } 421 422 void 423 pci_msi_disestablish(void *ih) 424 { 425 struct msi_hdl *msih = ih; 426 427 pci_conf_write(msih->pc, msih->tag, msih->co + PCI_MSI_CTL, 0); 428 intr_disestablish(msih->ih); 429 free(msih, M_DEVBUF); 430 } 431 #endif 432