1 /* $NetBSD: pci_intr_machdep.c,v 1.15 2010/02/25 20:51:10 dyoung Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998, 2009 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved. 35 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 1. Redistributions of source code must retain the above copyright 41 * notice, this list of conditions and the following disclaimer. 42 * 2. Redistributions in binary form must reproduce the above copyright 43 * notice, this list of conditions and the following disclaimer in the 44 * documentation and/or other materials provided with the distribution. 45 * 3. All advertising materials mentioning features or use of this software 46 * must display the following acknowledgement: 47 * This product includes software developed by Charles M. Hannum. 48 * 4. The name of the author may not be used to endorse or promote products 49 * derived from this software without specific prior written permission. 50 * 51 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 52 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 53 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 54 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 55 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 56 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 57 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 58 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 59 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 60 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 61 */ 62 63 /* 64 * Machine-specific functions for PCI autoconfiguration. 65 * 66 * On PCs, there are two methods of generating PCI configuration cycles. 67 * We try to detect the appropriate mechanism for this machine and set 68 * up a few function pointers to access the correct method directly. 69 * 70 * The configuration method can be hard-coded in the config file by 71 * using `options PCI_CONF_MODE=N', where `N' is the configuration mode 72 * as defined section 3.6.4.1, `Generating Configuration Cycles'. 73 */ 74 75 #include <sys/cdefs.h> 76 __KERNEL_RCSID(0, "$NetBSD: pci_intr_machdep.c,v 1.15 2010/02/25 20:51:10 dyoung Exp $"); 77 78 #include <sys/types.h> 79 #include <sys/param.h> 80 #include <sys/time.h> 81 #include <sys/systm.h> 82 #include <sys/errno.h> 83 #include <sys/device.h> 84 #include <sys/intr.h> 85 86 #include <uvm/uvm_extern.h> 87 88 #include <dev/pci/pcivar.h> 89 90 #include "ioapic.h" 91 #include "eisa.h" 92 #include "acpica.h" 93 #include "opt_mpbios.h" 94 #include "opt_acpi.h" 95 96 #if NIOAPIC > 0 || NACPICA > 0 97 #include <machine/i82093var.h> 98 #include <machine/mpconfig.h> 99 #include <machine/mpbiosvar.h> 100 #include <machine/pic.h> 101 #endif 102 103 #ifdef MPBIOS 104 #include <machine/mpbiosvar.h> 105 #endif 106 107 #if NACPICA > 0 108 #include <machine/mpacpi.h> 109 #endif 110 111 #define MPSAFE_MASK 0x80000000 112 113 int 114 pci_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *ihp) 115 { 116 int pin = pa->pa_intrpin; 117 int line = pa->pa_intrline; 118 pci_chipset_tag_t pc; 119 #if NIOAPIC > 0 || NACPICA > 0 120 int rawpin = pa->pa_rawintrpin; 121 int bus, dev, func; 122 #endif 123 124 if ((pc = pa->pa_pc) != NULL && pc->pc_intr_map != NULL) 125 return (*pc->pc_intr_map)(pa, ihp); 126 127 if (pin == 0) { 128 /* No IRQ used. */ 129 goto bad; 130 } 131 132 *ihp = 0; 133 134 if (pin > PCI_INTERRUPT_PIN_MAX) { 135 aprint_normal("pci_intr_map: bad interrupt pin %d\n", pin); 136 goto bad; 137 } 138 139 #if NIOAPIC > 0 || NACPICA > 0 140 pci_decompose_tag(pc, pa->pa_tag, &bus, &dev, &func); 141 if (mp_busses != NULL) { 142 if (intr_find_mpmapping(bus, (dev<<2)|(rawpin-1), ihp) == 0) { 143 if ((*ihp & 0xff) == 0) 144 *ihp |= line; 145 return 0; 146 } 147 /* 148 * No explicit PCI mapping found. This is not fatal, 149 * we'll try the ISA (or possibly EISA) mappings next. 150 */ 151 } 152 #endif 153 154 /* 155 * Section 6.2.4, `Miscellaneous Functions', says that 255 means 156 * `unknown' or `no connection' on a PC. We assume that a device with 157 * `no connection' either doesn't have an interrupt (in which case the 158 * pin number should be 0, and would have been noticed above), or 159 * wasn't configured by the BIOS (in which case we punt, since there's 160 * no real way we can know how the interrupt lines are mapped in the 161 * hardware). 162 * 163 * XXX 164 * Since IRQ 0 is only used by the clock, and we can't actually be sure 165 * that the BIOS did its job, we also recognize that as meaning that 166 * the BIOS has not configured the device. 167 */ 168 if (line == 0 || line == X86_PCI_INTERRUPT_LINE_NO_CONNECTION) { 169 aprint_normal("pci_intr_map: no mapping for pin %c (line=%02x)\n", 170 '@' + pin, line); 171 goto bad; 172 } else { 173 if (line >= NUM_LEGACY_IRQS) { 174 aprint_normal("pci_intr_map: bad interrupt line %d\n", line); 175 goto bad; 176 } 177 if (line == 2) { 178 aprint_normal("pci_intr_map: changed line 2 to line 9\n"); 179 line = 9; 180 } 181 } 182 #if NIOAPIC > 0 || NACPICA > 0 183 if (mp_busses != NULL) { 184 if (intr_find_mpmapping(mp_isa_bus, line, ihp) == 0) { 185 if ((*ihp & 0xff) == 0) 186 *ihp |= line; 187 return 0; 188 } 189 #if NEISA > 0 190 if (intr_find_mpmapping(mp_eisa_bus, line, ihp) == 0) { 191 if ((*ihp & 0xff) == 0) 192 *ihp |= line; 193 return 0; 194 } 195 #endif 196 aprint_normal("pci_intr_map: bus %d dev %d func %d pin %d; line %d\n", 197 bus, dev, func, pin, line); 198 aprint_normal("pci_intr_map: no MP mapping found\n"); 199 } 200 #endif 201 202 *ihp = line; 203 return 0; 204 205 bad: 206 *ihp = -1; 207 return 1; 208 } 209 210 const char * 211 pci_intr_string(pci_chipset_tag_t pc, pci_intr_handle_t ih) 212 { 213 if (pc != NULL && pc->pc_intr_string != NULL) 214 return (*pc->pc_intr_string)(pc, ih); 215 216 return intr_string(ih & ~MPSAFE_MASK); 217 } 218 219 220 const struct evcnt * 221 pci_intr_evcnt(pci_chipset_tag_t pc, pci_intr_handle_t ih) 222 { 223 224 if (pc != NULL && pc->pc_intr_evcnt != NULL) 225 return (*pc->pc_intr_evcnt)(pc, ih); 226 227 /* XXX for now, no evcnt parent reported */ 228 return NULL; 229 } 230 231 int 232 pci_intr_setattr(pci_chipset_tag_t pc, pci_intr_handle_t *ih, 233 int attr, uint64_t data) 234 { 235 236 switch (attr) { 237 case PCI_INTR_MPSAFE: 238 if (data) { 239 *ih |= MPSAFE_MASK; 240 } else { 241 *ih &= ~MPSAFE_MASK; 242 } 243 /* XXX Set live if already mapped. */ 244 return 0; 245 default: 246 return ENODEV; 247 } 248 } 249 250 void * 251 pci_intr_establish(pci_chipset_tag_t pc, pci_intr_handle_t ih, 252 int level, int (*func)(void *), void *arg) 253 { 254 int pin, irq; 255 struct pic *pic; 256 #if NIOAPIC > 0 257 struct ioapic_softc *ioapic; 258 #endif 259 bool mpsafe; 260 261 if (pc != NULL && pc->pc_intr_establish != NULL) 262 return (*pc->pc_intr_establish)(pc, ih, level, func, arg); 263 264 pic = &i8259_pic; 265 pin = irq = (ih & ~MPSAFE_MASK); 266 mpsafe = ((ih & MPSAFE_MASK) != 0); 267 268 #if NIOAPIC > 0 269 if (ih & APIC_INT_VIA_APIC) { 270 ioapic = ioapic_find(APIC_IRQ_APIC(ih)); 271 if (ioapic == NULL) { 272 aprint_normal("pci_intr_establish: bad ioapic %d\n", 273 APIC_IRQ_APIC(ih)); 274 return NULL; 275 } 276 pic = &ioapic->sc_pic; 277 pin = APIC_IRQ_PIN(ih); 278 irq = APIC_IRQ_LEGACY_IRQ(ih); 279 if (irq < 0 || irq >= NUM_LEGACY_IRQS) 280 irq = -1; 281 } 282 #endif 283 284 return intr_establish(irq, pic, pin, IST_LEVEL, level, func, arg, 285 mpsafe); 286 } 287 288 void 289 pci_intr_disestablish(pci_chipset_tag_t pc, void *cookie) 290 { 291 292 if (pc != NULL && pc->pc_intr_disestablish != NULL) { 293 (*pc->pc_intr_disestablish)(pc, cookie); 294 return; 295 } 296 297 intr_disestablish(cookie); 298 } 299