1 /* $NetBSD: pci_intr_machdep.c,v 1.41 2017/07/28 14:26:50 maxv Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998, 2009 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved. 35 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 1. Redistributions of source code must retain the above copyright 41 * notice, this list of conditions and the following disclaimer. 42 * 2. Redistributions in binary form must reproduce the above copyright 43 * notice, this list of conditions and the following disclaimer in the 44 * documentation and/or other materials provided with the distribution. 45 * 3. All advertising materials mentioning features or use of this software 46 * must display the following acknowledgement: 47 * This product includes software developed by Charles M. Hannum. 48 * 4. The name of the author may not be used to endorse or promote products 49 * derived from this software without specific prior written permission. 50 * 51 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 52 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 53 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 54 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 55 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 56 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 57 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 58 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 59 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 60 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 61 */ 62 63 /* 64 * Machine-specific functions for PCI autoconfiguration. 65 * 66 * On PCs, there are two methods of generating PCI configuration cycles. 67 * We try to detect the appropriate mechanism for this machine and set 68 * up a few function pointers to access the correct method directly. 69 * 70 * The configuration method can be hard-coded in the config file by 71 * using `options PCI_CONF_MODE=N', where `N' is the configuration mode 72 * as defined section 3.6.4.1, `Generating Configuration Cycles'. 73 */ 74 75 #include <sys/cdefs.h> 76 __KERNEL_RCSID(0, "$NetBSD: pci_intr_machdep.c,v 1.41 2017/07/28 14:26:50 maxv Exp $"); 77 78 #include <sys/types.h> 79 #include <sys/param.h> 80 #include <sys/time.h> 81 #include <sys/systm.h> 82 #include <sys/cpu.h> 83 #include <sys/errno.h> 84 #include <sys/device.h> 85 #include <sys/intr.h> 86 #include <sys/kmem.h> 87 88 #include <dev/pci/pcivar.h> 89 90 #include "ioapic.h" 91 #include "eisa.h" 92 #include "acpica.h" 93 #include "opt_mpbios.h" 94 #include "opt_acpi.h" 95 96 #include <machine/i82489reg.h> 97 98 #if NIOAPIC > 0 || NACPICA > 0 99 #include <machine/i82093reg.h> 100 #include <machine/i82093var.h> 101 #include <machine/mpconfig.h> 102 #include <machine/mpbiosvar.h> 103 #include <machine/pic.h> 104 #include <x86/pci/pci_msi_machdep.h> 105 #endif 106 107 #ifdef MPBIOS 108 #include <machine/mpbiosvar.h> 109 #endif 110 111 #if NACPICA > 0 112 #include <machine/mpacpi.h> 113 #endif 114 115 int 116 pci_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp) 117 { 118 pci_intr_pin_t pin = pa->pa_intrpin; 119 pci_intr_line_t line = pa->pa_intrline; 120 pci_chipset_tag_t ipc, pc = pa->pa_pc; 121 #if NIOAPIC > 0 || NACPICA > 0 122 pci_intr_pin_t rawpin = pa->pa_rawintrpin; 123 int bus, dev, func; 124 #endif 125 126 for (ipc = pc; ipc != NULL; ipc = ipc->pc_super) { 127 if ((ipc->pc_present & PCI_OVERRIDE_INTR_MAP) == 0) 128 continue; 129 return (*ipc->pc_ov->ov_intr_map)(ipc->pc_ctx, pa, ihp); 130 } 131 132 if (pin == 0) { 133 /* No IRQ used. */ 134 goto bad; 135 } 136 137 *ihp = 0; 138 139 if (pin > PCI_INTERRUPT_PIN_MAX) { 140 aprint_normal("pci_intr_map: bad interrupt pin %d\n", pin); 141 goto bad; 142 } 143 144 #if NIOAPIC > 0 || NACPICA > 0 145 KASSERT(rawpin >= PCI_INTERRUPT_PIN_A); 146 KASSERT(rawpin <= PCI_INTERRUPT_PIN_D); 147 pci_decompose_tag(pc, pa->pa_tag, &bus, &dev, &func); 148 if (mp_busses != NULL) { 149 /* 150 * Note: PCI_INTERRUPT_PIN_A == 1 where intr_find_mpmapping 151 * wants pci bus_pin encoding which uses INT_A == 0. 152 */ 153 if (intr_find_mpmapping(bus, 154 (dev << 2) | (rawpin - PCI_INTERRUPT_PIN_A), ihp) == 0) { 155 if (APIC_IRQ_LEGACY_IRQ(*ihp) == 0) 156 *ihp |= line; 157 return 0; 158 } 159 /* 160 * No explicit PCI mapping found. This is not fatal, 161 * we'll try the ISA (or possibly EISA) mappings next. 162 */ 163 } 164 #endif 165 166 /* 167 * Section 6.2.4, `Miscellaneous Functions', says that 255 means 168 * `unknown' or `no connection' on a PC. We assume that a device with 169 * `no connection' either doesn't have an interrupt (in which case the 170 * pin number should be 0, and would have been noticed above), or 171 * wasn't configured by the BIOS (in which case we punt, since there's 172 * no real way we can know how the interrupt lines are mapped in the 173 * hardware). 174 * 175 * XXX 176 * Since IRQ 0 is only used by the clock, and we can't actually be sure 177 * that the BIOS did its job, we also recognize that as meaning that 178 * the BIOS has not configured the device. 179 */ 180 if (line == 0 || line == X86_PCI_INTERRUPT_LINE_NO_CONNECTION) { 181 aprint_normal("pci_intr_map: no mapping for pin %c (line=%02x)\n", 182 '@' + pin, line); 183 goto bad; 184 } else { 185 if (line >= NUM_LEGACY_IRQS) { 186 aprint_normal("pci_intr_map: bad interrupt line %d\n", line); 187 goto bad; 188 } 189 if (line == 2) { 190 aprint_normal("pci_intr_map: changed line 2 to line 9\n"); 191 line = 9; 192 } 193 } 194 #if NIOAPIC > 0 || NACPICA > 0 195 if (mp_busses != NULL) { 196 if (intr_find_mpmapping(mp_isa_bus, line, ihp) == 0) { 197 if ((*ihp & 0xff) == 0) 198 *ihp |= line; 199 return 0; 200 } 201 #if NEISA > 0 202 if (intr_find_mpmapping(mp_eisa_bus, line, ihp) == 0) { 203 if ((*ihp & 0xff) == 0) 204 *ihp |= line; 205 return 0; 206 } 207 #endif 208 aprint_normal("pci_intr_map: bus %d dev %d func %d pin %d; line %d\n", 209 bus, dev, func, pin, line); 210 aprint_normal("pci_intr_map: no MP mapping found\n"); 211 } 212 #endif 213 214 *ihp = line; 215 return 0; 216 217 bad: 218 *ihp = -1; 219 return 1; 220 } 221 222 const char * 223 pci_intr_string(pci_chipset_tag_t pc, pci_intr_handle_t ih, char *buf, 224 size_t len) 225 { 226 pci_chipset_tag_t ipc; 227 228 for (ipc = pc; ipc != NULL; ipc = ipc->pc_super) { 229 if ((ipc->pc_present & PCI_OVERRIDE_INTR_STRING) == 0) 230 continue; 231 return (*ipc->pc_ov->ov_intr_string)(ipc->pc_ctx, pc, ih, 232 buf, len); 233 } 234 235 if (INT_VIA_MSI(ih)) 236 return x86_pci_msi_string(pc, ih, buf, len); 237 238 return intr_string(ih & ~MPSAFE_MASK, buf, len); 239 } 240 241 242 const struct evcnt * 243 pci_intr_evcnt(pci_chipset_tag_t pc, pci_intr_handle_t ih) 244 { 245 pci_chipset_tag_t ipc; 246 247 for (ipc = pc; ipc != NULL; ipc = ipc->pc_super) { 248 if ((ipc->pc_present & PCI_OVERRIDE_INTR_EVCNT) == 0) 249 continue; 250 return (*ipc->pc_ov->ov_intr_evcnt)(ipc->pc_ctx, pc, ih); 251 } 252 253 /* XXX for now, no evcnt parent reported */ 254 return NULL; 255 } 256 257 int 258 pci_intr_setattr(pci_chipset_tag_t pc, pci_intr_handle_t *ih, 259 int attr, uint64_t data) 260 { 261 262 switch (attr) { 263 case PCI_INTR_MPSAFE: 264 if (data) { 265 *ih |= MPSAFE_MASK; 266 } else { 267 *ih &= ~MPSAFE_MASK; 268 } 269 /* XXX Set live if already mapped. */ 270 return 0; 271 default: 272 return ENODEV; 273 } 274 } 275 276 static void * 277 pci_intr_establish_xname_internal(pci_chipset_tag_t pc, pci_intr_handle_t ih, 278 int level, int (*func)(void *), void *arg, const char *xname) 279 { 280 int pin, irq; 281 struct pic *pic; 282 #if NIOAPIC > 0 283 struct ioapic_softc *ioapic; 284 #endif 285 bool mpsafe; 286 pci_chipset_tag_t ipc; 287 288 for (ipc = pc; ipc != NULL; ipc = ipc->pc_super) { 289 if ((ipc->pc_present & PCI_OVERRIDE_INTR_ESTABLISH) == 0) 290 continue; 291 return (*ipc->pc_ov->ov_intr_establish)(ipc->pc_ctx, 292 pc, ih, level, func, arg); 293 } 294 295 if (INT_VIA_MSI(ih)) { 296 if (MSI_INT_IS_MSIX(ih)) 297 return x86_pci_msix_establish(pc, ih, level, func, arg, 298 xname); 299 else 300 return x86_pci_msi_establish(pc, ih, level, func, arg, 301 xname); 302 } 303 304 pic = &i8259_pic; 305 pin = irq = APIC_IRQ_LEGACY_IRQ(ih); 306 mpsafe = ((ih & MPSAFE_MASK) != 0); 307 308 #if NIOAPIC > 0 309 if (ih & APIC_INT_VIA_APIC) { 310 ioapic = ioapic_find(APIC_IRQ_APIC(ih)); 311 if (ioapic == NULL) { 312 aprint_normal("pci_intr_establish: bad ioapic %d\n", 313 APIC_IRQ_APIC(ih)); 314 return NULL; 315 } 316 pic = &ioapic->sc_pic; 317 pin = APIC_IRQ_PIN(ih); 318 irq = APIC_IRQ_LEGACY_IRQ(ih); 319 if (irq < 0 || irq >= NUM_LEGACY_IRQS) 320 irq = -1; 321 } 322 #endif 323 324 return intr_establish_xname(irq, pic, pin, IST_LEVEL, level, func, arg, 325 mpsafe, xname); 326 } 327 328 void * 329 pci_intr_establish(pci_chipset_tag_t pc, pci_intr_handle_t ih, 330 int level, int (*func)(void *), void *arg) 331 { 332 333 return pci_intr_establish_xname_internal(pc, ih, level, func, arg, "unknown"); 334 } 335 336 #ifdef __HAVE_PCI_MSI_MSIX 337 void * 338 pci_intr_establish_xname(pci_chipset_tag_t pc, pci_intr_handle_t ih, 339 int level, int (*func)(void *), void *arg, const char *xname) 340 { 341 342 return pci_intr_establish_xname_internal(pc, ih, level, func, arg, xname); 343 } 344 #endif 345 346 347 void 348 pci_intr_disestablish(pci_chipset_tag_t pc, void *cookie) 349 { 350 pci_chipset_tag_t ipc; 351 352 for (ipc = pc; ipc != NULL; ipc = ipc->pc_super) { 353 if ((ipc->pc_present & PCI_OVERRIDE_INTR_DISESTABLISH) == 0) 354 continue; 355 (*ipc->pc_ov->ov_intr_disestablish)(ipc->pc_ctx, pc, cookie); 356 return; 357 } 358 359 /* MSI/MSI-X processing is switched in intr_disestablish(). */ 360 intr_disestablish(cookie); 361 } 362 363 #if NIOAPIC > 0 364 #ifdef __HAVE_PCI_MSI_MSIX 365 pci_intr_type_t 366 pci_intr_type(pci_chipset_tag_t pc, pci_intr_handle_t ih) 367 { 368 369 if (INT_VIA_MSI(ih)) { 370 if (MSI_INT_IS_MSIX(ih)) 371 return PCI_INTR_TYPE_MSIX; 372 else 373 return PCI_INTR_TYPE_MSI; 374 } else { 375 return PCI_INTR_TYPE_INTX; 376 } 377 } 378 379 static void 380 x86_pci_intx_release(pci_chipset_tag_t pc, pci_intr_handle_t *pih) 381 { 382 char intrstr_buf[INTRIDBUF]; 383 const char *intrstr; 384 385 intrstr = pci_intr_string(NULL, *pih, intrstr_buf, sizeof(intrstr_buf)); 386 mutex_enter(&cpu_lock); 387 intr_free_io_intrsource(intrstr); 388 mutex_exit(&cpu_lock); 389 390 kmem_free(pih, sizeof(*pih)); 391 } 392 393 int 394 pci_intx_alloc(const struct pci_attach_args *pa, pci_intr_handle_t **pih) 395 { 396 struct intrsource *isp; 397 pci_intr_handle_t *handle; 398 int error; 399 char intrstr_buf[INTRIDBUF]; 400 const char *intrstr; 401 402 handle = kmem_zalloc(sizeof(*handle), KM_SLEEP); 403 if (pci_intr_map(pa, handle) != 0) { 404 aprint_normal("cannot set up pci_intr_handle_t\n"); 405 error = EINVAL; 406 goto error; 407 } 408 409 intrstr = pci_intr_string(pa->pa_pc, *handle, 410 intrstr_buf, sizeof(intrstr_buf)); 411 mutex_enter(&cpu_lock); 412 isp = intr_allocate_io_intrsource(intrstr); 413 mutex_exit(&cpu_lock); 414 if (isp == NULL) { 415 aprint_normal("can't allocate io_intersource\n"); 416 error = ENOMEM; 417 goto error; 418 } 419 420 *pih = handle; 421 return 0; 422 423 error: 424 kmem_free(handle, sizeof(*handle)); 425 return error; 426 } 427 428 /* 429 * Interrupt handler allocation utility. This function calls each allocation 430 * function as specified by arguments. 431 * Currently callee functions are pci_intx_alloc(), pci_msi_alloc_exact(), 432 * and pci_msix_alloc_exact(). 433 * pa : pci_attach_args 434 * ihps : interrupt handlers 435 * counts : The array of number of required interrupt handlers. 436 * It is overwritten by allocated the number of handlers. 437 * CAUTION: The size of counts[] must be PCI_INTR_TYPE_SIZE. 438 * max_type : "max" type of using interrupts. See below. 439 * e.g. 440 * If you want to use 5 MSI-X, 1 MSI, or INTx, you use "counts" as 441 * int counts[PCI_INTR_TYPE_SIZE]; 442 * counts[PCI_INTR_TYPE_MSIX] = 5; 443 * counts[PCI_INTR_TYPE_MSI] = 1; 444 * counts[PCI_INTR_TYPE_INTX] = 1; 445 * error = pci_intr_alloc(pa, ihps, counts, PCI_INTR_TYPE_MSIX); 446 * 447 * If you want to use hardware max number MSI-X or 1 MSI, 448 * and not to use INTx, you use "counts" as 449 * int counts[PCI_INTR_TYPE_SIZE]; 450 * counts[PCI_INTR_TYPE_MSIX] = -1; 451 * counts[PCI_INTR_TYPE_MSI] = 1; 452 * counts[PCI_INTR_TYPE_INTX] = 0; 453 * error = pci_intr_alloc(pa, ihps, counts, PCI_INTR_TYPE_MSIX); 454 * 455 * If you want to use 3 MSI or INTx, you can use "counts" as 456 * int counts[PCI_INTR_TYPE_SIZE]; 457 * counts[PCI_INTR_TYPE_MSI] = 3; 458 * counts[PCI_INTR_TYPE_INTX] = 1; 459 * error = pci_intr_alloc(pa, ihps, counts, PCI_INTR_TYPE_MSI); 460 * 461 * If you want to use 1 MSI or INTx (probably most general usage), 462 * you can simply use this API like 463 * below 464 * error = pci_intr_alloc(pa, ihps, NULL, 0); 465 * ^ ignored 466 */ 467 int 468 pci_intr_alloc(const struct pci_attach_args *pa, pci_intr_handle_t **ihps, 469 int *counts, pci_intr_type_t max_type) 470 { 471 int error; 472 int intx_count, msi_count, msix_count; 473 474 intx_count = msi_count = msix_count = 0; 475 if (counts == NULL) { /* simple pattern */ 476 msi_count = 1; 477 intx_count = 1; 478 } else { 479 switch(max_type) { 480 case PCI_INTR_TYPE_MSIX: 481 msix_count = counts[PCI_INTR_TYPE_MSIX]; 482 /* FALLTHROUGH */ 483 case PCI_INTR_TYPE_MSI: 484 msi_count = counts[PCI_INTR_TYPE_MSI]; 485 /* FALLTHROUGH */ 486 case PCI_INTR_TYPE_INTX: 487 intx_count = counts[PCI_INTR_TYPE_INTX]; 488 break; 489 default: 490 return EINVAL; 491 } 492 } 493 494 if (counts != NULL) 495 memset(counts, 0, sizeof(counts[0]) * PCI_INTR_TYPE_SIZE); 496 error = EINVAL; 497 498 /* try MSI-X */ 499 if (msix_count == -1) /* use hardware max */ 500 msix_count = pci_msix_count(pa->pa_pc, pa->pa_tag); 501 if (msix_count > 0) { 502 error = pci_msix_alloc_exact(pa, ihps, msix_count); 503 if (error == 0) { 504 KASSERTMSG(counts != NULL, 505 "If MSI-X is used, counts must not be NULL."); 506 counts[PCI_INTR_TYPE_MSIX] = msix_count; 507 goto out; 508 } 509 } 510 511 /* try MSI */ 512 if (msi_count == -1) /* use hardware max */ 513 msi_count = pci_msi_count(pa->pa_pc, pa->pa_tag); 514 if (msi_count > 0) { 515 error = pci_msi_alloc_exact(pa, ihps, msi_count); 516 if (error == 0) { 517 if (counts != NULL) 518 counts[PCI_INTR_TYPE_MSI] = msi_count; 519 goto out; 520 } 521 } 522 523 /* try INTx */ 524 if (intx_count != 0) { /* The number of INTx is always 1. */ 525 error = pci_intx_alloc(pa, ihps); 526 if (error == 0) { 527 if (counts != NULL) 528 counts[PCI_INTR_TYPE_INTX] = 1; 529 } 530 } 531 532 out: 533 return error; 534 } 535 536 void 537 pci_intr_release(pci_chipset_tag_t pc, pci_intr_handle_t *pih, int count) 538 { 539 if (pih == NULL) 540 return; 541 542 if (INT_VIA_MSI(*pih)) { 543 if (MSI_INT_IS_MSIX(*pih)) 544 return x86_pci_msix_release(pc, pih, count); 545 else 546 return x86_pci_msi_release(pc, pih, count); 547 } else { 548 KASSERT(count == 1); 549 return x86_pci_intx_release(pc, pih); 550 } 551 552 } 553 #endif /* __HAVE_PCI_MSI_MSIX */ 554 #endif /* NIOAPIC > 0 */ 555