xref: /netbsd-src/sys/arch/x86/pci/imcsmb/imcsmb_var.h (revision 82ae8dd180cc6a638127f185d3ba129258cd61fc)
1*82ae8dd1Spgoyette /* $NetBSD: imcsmb_var.h,v 1.1 2018/03/01 04:45:06 pgoyette Exp $ */
2*82ae8dd1Spgoyette 
3*82ae8dd1Spgoyette /*-
4*82ae8dd1Spgoyette  * Copyright (c) 2018 The NetBSD Foundation, Inc.
5*82ae8dd1Spgoyette  * All rights reserved.
6*82ae8dd1Spgoyette  *
7*82ae8dd1Spgoyette  * This code is derived from software contributed to The NetBSD Foundation
8*82ae8dd1Spgoyette  * by Paul Goyette
9*82ae8dd1Spgoyette  *
10*82ae8dd1Spgoyette  * Redistribution and use in source and binary forms, with or without
11*82ae8dd1Spgoyette  * modification, are permitted provided that the following conditions
12*82ae8dd1Spgoyette  * are met:
13*82ae8dd1Spgoyette  * 1. Redistributions of source code must retain the above copyright
14*82ae8dd1Spgoyette  *    notice, this list of conditions and the following disclaimer.
15*82ae8dd1Spgoyette  * 2. Redistributions in binary form must reproduce the above copyright
16*82ae8dd1Spgoyette  *    notice, this list of conditions and the following disclaimer in the
17*82ae8dd1Spgoyette  *    documentation and/or other materials provided with the distribution.
18*82ae8dd1Spgoyette  *
19*82ae8dd1Spgoyette  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20*82ae8dd1Spgoyette  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21*82ae8dd1Spgoyette  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22*82ae8dd1Spgoyette  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23*82ae8dd1Spgoyette  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24*82ae8dd1Spgoyette  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25*82ae8dd1Spgoyette  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26*82ae8dd1Spgoyette  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27*82ae8dd1Spgoyette  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28*82ae8dd1Spgoyette  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29*82ae8dd1Spgoyette  * POSSIBILITY OF SUCH DAMAGE.
30*82ae8dd1Spgoyette  */
31*82ae8dd1Spgoyette 
32*82ae8dd1Spgoyette /*-
33*82ae8dd1Spgoyette  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
34*82ae8dd1Spgoyette  *
35*82ae8dd1Spgoyette  * Authors: Joe Kloss; Ravi Pokala (rpokala@freebsd.org)
36*82ae8dd1Spgoyette  *
37*82ae8dd1Spgoyette  * Copyright (c) 2017-2018 Panasas
38*82ae8dd1Spgoyette  * All rights reserved.
39*82ae8dd1Spgoyette  *
40*82ae8dd1Spgoyette  * Redistribution and use in source and binary forms, with or without
41*82ae8dd1Spgoyette  * modification, are permitted provided that the following conditions
42*82ae8dd1Spgoyette  * are met:
43*82ae8dd1Spgoyette  * 1. Redistributions of source code must retain the above copyright
44*82ae8dd1Spgoyette  *    notice, this list of conditions and the following disclaimer.
45*82ae8dd1Spgoyette  * 2. Redistributions in binary form must reproduce the above copyright
46*82ae8dd1Spgoyette  *    notice, this list of conditions and the following disclaimer in the
47*82ae8dd1Spgoyette  *    documentation and/or other materials provided with the distribution.
48*82ae8dd1Spgoyette  *
49*82ae8dd1Spgoyette  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
50*82ae8dd1Spgoyette  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
51*82ae8dd1Spgoyette  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
52*82ae8dd1Spgoyette  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
53*82ae8dd1Spgoyette  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
54*82ae8dd1Spgoyette  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
55*82ae8dd1Spgoyette  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
56*82ae8dd1Spgoyette  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
57*82ae8dd1Spgoyette  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
58*82ae8dd1Spgoyette  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
59*82ae8dd1Spgoyette  * SUCH DAMAGE.
60*82ae8dd1Spgoyette  */
61*82ae8dd1Spgoyette 
62*82ae8dd1Spgoyette #ifndef _DEV__IMCSMB__IMCSMB_VAR_H_
63*82ae8dd1Spgoyette #define _DEV__IMCSMB__IMCSMB_VAR_H_
64*82ae8dd1Spgoyette 
65*82ae8dd1Spgoyette #include <sys/param.h>
66*82ae8dd1Spgoyette #include <sys/mutex.h>
67*82ae8dd1Spgoyette #include <sys/bus.h>
68*82ae8dd1Spgoyette 
69*82ae8dd1Spgoyette #include <dev/i2c/i2cvar.h>
70*82ae8dd1Spgoyette 
71*82ae8dd1Spgoyette #include <dev/pci/pcivar.h>
72*82ae8dd1Spgoyette /* #include <dev/pci/pcireg.h> PRG */
73*82ae8dd1Spgoyette 
74*82ae8dd1Spgoyette /* A detailed description of this device is present in imcsmb_pci.c */
75*82ae8dd1Spgoyette 
76*82ae8dd1Spgoyette /**
77*82ae8dd1Spgoyette  * The softc for a particular instance of the PCI device associated with a pair
78*82ae8dd1Spgoyette  * of iMC-SMB controllers.
79*82ae8dd1Spgoyette  *
80*82ae8dd1Spgoyette  * Ordinarily, locking would be done with a mutex. However, we might have an
81*82ae8dd1Spgoyette  * NVDIMM connected to this SMBus, and we might need to issue the SAVE command
82*82ae8dd1Spgoyette  * to the NVDIMM from a panic context. Mutex operations are not allowed while
83*82ae8dd1Spgoyette  * the scheduler is stopped, so just use a simple semaphore.
84*82ae8dd1Spgoyette  *
85*82ae8dd1Spgoyette  * If, as described in the manpage, additional steps are needed to stop/restart
86*82ae8dd1Spgoyette  * firmware operations before/after using the controller, then additional fields
87*82ae8dd1Spgoyette  * can be added to this softc.
88*82ae8dd1Spgoyette  */
89*82ae8dd1Spgoyette struct imc_softc {
90*82ae8dd1Spgoyette 	device_t	sc_dev;
91*82ae8dd1Spgoyette 	device_t	sc_smbchild[2];
92*82ae8dd1Spgoyette 	pcitag_t	sc_pci_tag;	/* pci config space info */
93*82ae8dd1Spgoyette 	pci_chipset_tag_t sc_pci_chipset_tag;
94*82ae8dd1Spgoyette };
95*82ae8dd1Spgoyette 
96*82ae8dd1Spgoyette void imcsmb_pci_release_bus(device_t dev);
97*82ae8dd1Spgoyette int imcsmb_pci_request_bus(device_t dev);
98*82ae8dd1Spgoyette 
99*82ae8dd1Spgoyette /**
100*82ae8dd1Spgoyette  * PCI config registers for each individual SMBus controller within the iMC.
101*82ae8dd1Spgoyette  * Each iMC-SMB has a separate set of registers. There is an array of these
102*82ae8dd1Spgoyette  * structures for the PCI device, and one of them is passed to driver for the
103*82ae8dd1Spgoyette  * actual iMC-SMB as the IVAR.
104*82ae8dd1Spgoyette  */
105*82ae8dd1Spgoyette struct imcsmb_reg_set {
106*82ae8dd1Spgoyette 	uint16_t smb_stat;
107*82ae8dd1Spgoyette 	uint16_t smb_cmd;
108*82ae8dd1Spgoyette 	uint16_t smb_cntl;
109*82ae8dd1Spgoyette };
110*82ae8dd1Spgoyette 
111*82ae8dd1Spgoyette /**
112*82ae8dd1Spgoyette  * The softc for the device associated with a particular iMC-SMB controller.
113*82ae8dd1Spgoyette  * There are two such controllers for each of the PCI devices. The PCI driver
114*82ae8dd1Spgoyette  * tells the iMC-SMB driver which set of registers to use via the IVAR. This
115*82ae8dd1Spgoyette  * technique was suggested by John Baldwin (jhb@).
116*82ae8dd1Spgoyette  */
117*82ae8dd1Spgoyette struct imcsmb_softc {
118*82ae8dd1Spgoyette 	device_t		sc_dev;
119*82ae8dd1Spgoyette 	device_t		sc_smbus;	/* child smbusX interface */
120*82ae8dd1Spgoyette 	struct imcsmb_reg_set	*sc_regs;	/* regs for this controller */
121*82ae8dd1Spgoyette 	struct i2c_controller	sc_i2c_tag;	/* i2c tag info */
122*82ae8dd1Spgoyette 	pcitag_t		sc_pci_tag;	/* pci config space info */
123*82ae8dd1Spgoyette 	pci_chipset_tag_t	sc_pci_chipset_tag;
124*82ae8dd1Spgoyette 	kmutex_t		sc_i2c_mutex;
125*82ae8dd1Spgoyette };
126*82ae8dd1Spgoyette 
127*82ae8dd1Spgoyette struct imc_attach_args {
128*82ae8dd1Spgoyette 	int			ia_unit;
129*82ae8dd1Spgoyette 	struct imcsmb_reg_set	*ia_regs;
130*82ae8dd1Spgoyette 	pci_chipset_tag_t	ia_pci_pc;
131*82ae8dd1Spgoyette 	pcitag_t		ia_pci_tag;
132*82ae8dd1Spgoyette 	pci_chipset_tag_t	ia_pci_chipset_tag;
133*82ae8dd1Spgoyette 
134*82ae8dd1Spgoyette };
135*82ae8dd1Spgoyette 
136*82ae8dd1Spgoyette /* Interface for enable/disable BIOS or other motherboard access to IMC */
137*82ae8dd1Spgoyette 
138*82ae8dd1Spgoyette typedef enum {
139*82ae8dd1Spgoyette 	IMC_BIOS_ENABLE,
140*82ae8dd1Spgoyette 	IMC_BIOS_DISABLE
141*82ae8dd1Spgoyette } imc_bios_control ;
142*82ae8dd1Spgoyette 
143*82ae8dd1Spgoyette void imc_callback(struct imcsmb_softc *, imc_bios_control);
144*82ae8dd1Spgoyette 
145*82ae8dd1Spgoyette #endif /* _DEV__IMCSMB__IMCSMB_VAR_H_ */
146