1 /* $NetBSD: imcsmb.c,v 1.2 2018/03/03 05:27:02 pgoyette Exp $ */ 2 3 /*- 4 * Copyright (c) 2018 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Goyette 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 34 * 35 * Authors: Joe Kloss; Ravi Pokala (rpokala@freebsd.org) 36 * 37 * Copyright (c) 2017-2018 Panasas 38 * All rights reserved. 39 * 40 * Redistribution and use in source and binary forms, with or without 41 * modification, are permitted provided that the following conditions 42 * are met: 43 * 1. Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * 2. Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in the 47 * documentation and/or other materials provided with the distribution. 48 * 49 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 50 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 51 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 52 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 53 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 54 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 55 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 56 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 57 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 58 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 59 * SUCH DAMAGE. 60 */ 61 62 /* 63 * Driver for the SMBus controllers in Intel's Integrated Memory Controllers 64 * in certain CPUs. A more detailed description of this device is present 65 * in imc.c 66 */ 67 68 #include <sys/cdefs.h> 69 __KERNEL_RCSID(0, "$NetBSD: imcsmb.c,v 1.2 2018/03/03 05:27:02 pgoyette Exp $"); 70 71 #include <sys/param.h> 72 #include <sys/kernel.h> 73 #include <sys/module.h> 74 #include <sys/endian.h> 75 #include <sys/errno.h> 76 #include <sys/mutex.h> 77 #include <sys/bus.h> 78 79 #include <dev/pci/pcidevs.h> 80 #include <dev/pci/pcivar.h> 81 #include <dev/pci/pcireg.h> 82 83 #include <dev/i2c/i2cvar.h> 84 85 #include "imcsmb_reg.h" 86 #include "imcsmb_var.h" 87 88 /* Device methods */ 89 static int imcsmb_probe(device_t, cfdata_t, void *); 90 static void imcsmb_attach(device_t, device_t, void *); 91 static int imcsmb_detach(device_t, int flags); 92 static int imcsmb_rescan(device_t, const char *, const int *); 93 static void imcsmb_chdet(device_t, device_t); 94 95 CFATTACH_DECL3_NEW(imcsmb, sizeof(struct imcsmb_softc), 96 imcsmb_probe, imcsmb_attach, imcsmb_detach, NULL, imcsmb_rescan, 97 imcsmb_chdet, 0); 98 99 /* Bus access control methods */ 100 static int imcsmb_acquire_bus(void *cookie, int flags); 101 static void imcsmb_release_bus(void *cookie, int flags); 102 103 /* SMBus methods */ 104 static int imcsmb_exec(void *cookie, i2c_op_t, i2c_addr_t, const void *, 105 size_t, void *, size_t, int); 106 107 /** 108 * device_attach() method. Set up the softc, including getting the set of the 109 * parent imcsmb_pci's registers that we will use. Create the smbus(4) device, 110 * which any SMBus slave device drivers will connect to. Probe and attach 111 * anything which might be downstream. 112 * 113 * @author rpokala 114 * 115 * @param[in,out] dev 116 * Device being attached. 117 */ 118 119 static void 120 imcsmb_attach(device_t parent, device_t self, void *aux) 121 { 122 struct imcsmb_softc *sc = device_private(self); 123 struct imc_attach_args *imca = aux; 124 125 aprint_naive("\n"); 126 aprint_normal(": SMBus controller\n"); 127 128 /* Initialize private state */ 129 sc->sc_dev = self; 130 sc->sc_regs = imca->ia_regs; 131 sc->sc_pci_tag = imca->ia_pci_tag; 132 sc->sc_pci_chipset_tag = imca->ia_pci_chipset_tag; 133 mutex_init(&sc->sc_i2c_mutex, MUTEX_DEFAULT, IPL_NONE); 134 135 if (!pmf_device_register(self, NULL, NULL)) 136 aprint_error_dev(self, "couldn't establish power handler\n"); 137 138 imcsmb_rescan(self, "i2cbus", 0); 139 } 140 141 static int 142 imcsmb_rescan(device_t self, const char *ifattr, const int *flags) 143 { 144 struct imcsmb_softc *sc = device_private(self); 145 struct i2cbus_attach_args iba; 146 147 if (!ifattr_match(ifattr, "i2cbus")) 148 return 0; 149 150 /* Create the i2cbus child */ 151 if (sc->sc_smbus != NULL) 152 return 0; 153 154 sc->sc_i2c_tag.ic_cookie = sc; 155 sc->sc_i2c_tag.ic_acquire_bus = imcsmb_acquire_bus; 156 sc->sc_i2c_tag.ic_release_bus = imcsmb_release_bus; 157 sc->sc_i2c_tag.ic_exec = imcsmb_exec; 158 159 memset(&iba, 0, sizeof(iba)); 160 iba.iba_type = I2C_TYPE_SMBUS; 161 iba.iba_tag = &sc->sc_i2c_tag; 162 sc->sc_smbus = config_found_ia(self, ifattr, &iba, iicbus_print); 163 164 if (sc->sc_smbus == NULL) { 165 aprint_normal_dev(self, "no child found\n"); 166 return ENXIO; 167 } 168 169 return 0; 170 } 171 172 static void 173 imcsmb_chdet(device_t self, device_t child) 174 { 175 struct imcsmb_softc *sc = device_private(self); 176 177 if (child == sc->sc_smbus) 178 sc->sc_smbus = NULL; 179 else KASSERT(child == NULL); 180 } 181 182 /** 183 * device_detach() method. attach() didn't do any allocations, so there's 184 * nothing special needed 185 */ 186 static int 187 imcsmb_detach(device_t self, int flags) 188 { 189 int error; 190 struct imcsmb_softc *sc = device_private(self); 191 192 if (sc->sc_smbus != NULL) { 193 error = config_detach(sc->sc_smbus, flags); 194 if (error) 195 return error; 196 } 197 198 pmf_device_deregister(self); 199 mutex_destroy(&sc->sc_i2c_mutex); 200 return 0; 201 } 202 203 /** 204 * device_probe() method. All the actual probing was done by the imc 205 * parent, so just report success. 206 * 207 * @author Joe Kloss 208 * 209 * @param[in,out] dev 210 * Device being probed. 211 */ 212 static int 213 imcsmb_probe(device_t parent, cfdata_t match, void *aux) 214 { 215 216 return 1; 217 } 218 219 static int 220 imcsmb_acquire_bus(void *cookie, int flags) 221 { 222 struct imcsmb_softc *sc = cookie; 223 224 if (cold) 225 return 0; 226 227 mutex_enter(&sc->sc_i2c_mutex); 228 229 imc_callback(sc, IMC_BIOS_DISABLE); 230 231 return 0; 232 } 233 234 static void 235 imcsmb_release_bus(void *cookie, int flags) 236 { 237 struct imcsmb_softc *sc = cookie; 238 239 if (cold) 240 return; 241 242 imc_callback(sc, IMC_BIOS_ENABLE); 243 244 mutex_exit(&sc->sc_i2c_mutex); 245 } 246 247 static int 248 imcsmb_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, const void *cmdbuf, 249 size_t cmdlen, void *buf, size_t len, int flags) 250 { 251 struct imcsmb_softc *sc = cookie; 252 int i; 253 int rc = 0; 254 uint32_t cmd_val; 255 uint32_t cntl_val; 256 uint32_t orig_cntl_val; 257 uint32_t stat_val; 258 uint16_t *word; 259 uint16_t lword; 260 uint8_t *byte; 261 uint8_t lbyte; 262 uint8_t cmd; 263 264 if ((cmdlen != 1) || (len > 2) || (len < 1)) 265 return EINVAL; 266 267 byte = (uint8_t *) buf; 268 word = (uint16_t *) buf; 269 lbyte = *byte; 270 lword = *word; 271 272 /* We modify the value of the control register; save the original, so 273 * we can restore it later 274 */ 275 orig_cntl_val = pci_conf_read(sc->sc_pci_chipset_tag, sc->sc_pci_tag, 276 sc->sc_regs->smb_cntl); 277 278 cntl_val = orig_cntl_val; 279 280 /* 281 * Set up the SMBCNTL register 282 */ 283 284 /* [31:28] Clear the existing value of the DTI bits, then set them to 285 * the four high bits of the slave address. 286 */ 287 cntl_val &= ~IMCSMB_CNTL_DTI_MASK; 288 cntl_val |= ((uint32_t) addr & 0x78) << 25; 289 290 /* [27:27] Set the CLK_OVERRIDE bit, to enable normal operation */ 291 cntl_val |= IMCSMB_CNTL_CLK_OVERRIDE; 292 293 /* [26:26] Clear the WRITE_DISABLE bit; the datasheet says this isn't 294 * necessary, but empirically, it is. 295 */ 296 cntl_val &= ~IMCSMB_CNTL_WRITE_DISABLE_BIT; 297 298 /* [9:9] Clear the POLL_EN bit, to stop the hardware TSOD polling. */ 299 cntl_val &= ~IMCSMB_CNTL_POLL_EN; 300 301 /* 302 * Set up the SMBCMD register 303 */ 304 305 /* [31:31] Set the TRIGGER bit; when this gets written, the controller 306 * will issue the command. 307 */ 308 cmd_val = IMCSMB_CMD_TRIGGER_BIT; 309 310 /* [29:29] For word operations, set the WORD_ACCESS bit. */ 311 if (len == 2) { 312 cmd_val |= IMCSMB_CMD_WORD_ACCESS; 313 } 314 315 /* [27:27] For write operations, set the WRITE bit. */ 316 if (I2C_OP_WRITE_P(op)) { 317 cmd_val |= IMCSMB_CMD_WRITE_BIT; 318 } 319 320 /* [26:24] The three non-DTI, non-R/W bits of the slave address. */ 321 cmd_val |= (uint32_t) ((addr & 0x7) << 24); 322 323 /* [23:16] The command (offset in the case of an EEPROM, or register in 324 * the case of TSOD or NVDIMM controller). 325 */ 326 cmd = *((const uint8_t *) cmdbuf); 327 cmd_val |= (uint32_t) (cmd << 16); 328 329 /* [15:0] The data to be written for a write operation. */ 330 if (I2C_OP_WRITE_P(op)) { 331 if (len == 2) { 332 /* The datasheet says the controller uses different 333 * endianness for word operations on I2C vs SMBus! 334 * I2C: [15:8] = MSB; [7:0] = LSB 335 * SMB: [15:8] = LSB; [7:0] = MSB 336 * As a practical matter, this controller is very 337 * specifically for use with DIMMs, the SPD (and 338 * NVDIMM controllers) are only accessed as bytes, 339 * the temperature sensor is only accessed as words, and 340 * the temperature sensors are I2C. Thus, byte-swap the 341 * word. 342 */ 343 lword = htobe16(*(uint16_t *)buf); 344 } else { 345 /* For byte operations, the data goes in the LSB, and 346 * the MSB is a don't care. 347 */ 348 lword = *(uint8_t *)buf; 349 } 350 cmd_val |= lword; 351 } 352 353 /* Write the updated value to the control register first, to disable 354 * the hardware TSOD polling. 355 */ 356 pci_conf_write(sc->sc_pci_chipset_tag, sc->sc_pci_tag, 357 sc->sc_regs->smb_cntl, cntl_val); 358 359 /* Poll on the BUSY bit in the status register until clear, or timeout. 360 * We just cleared the auto-poll bit, so we need to make sure the device 361 * is idle before issuing a command. We can safely timeout after 35 ms, 362 * as this is the maximum time the SMBus spec allows for a transaction. 363 */ 364 for (i = 4; i != 0; i--) { 365 stat_val = pci_conf_read(sc->sc_pci_chipset_tag, 366 sc->sc_pci_tag, sc->sc_regs->smb_stat); 367 if (! (stat_val & IMCSMB_STATUS_BUSY_BIT)) { 368 break; 369 } 370 delay(100); /* wait 10ms */ 371 } 372 373 if (i == 0) { 374 aprint_debug_dev(sc->sc_dev, 375 "transfer: timeout waiting for device to settle\n"); 376 } 377 378 /* Now that polling has stopped, we can write the command register. This 379 * starts the SMBus command. 380 */ 381 pci_conf_write(sc->sc_pci_chipset_tag, sc->sc_pci_tag, 382 sc->sc_regs->smb_cmd, cmd_val); 383 384 /* Wait for WRITE_DATA_DONE/READ_DATA_VALID to be set, or timeout and 385 * fail. We wait up to 35ms. 386 */ 387 for (i = 35000; i != 0; i -= 10) 388 { 389 delay(10); 390 stat_val = pci_conf_read(sc->sc_pci_chipset_tag, 391 sc->sc_pci_tag, sc->sc_regs->smb_stat); 392 /* 393 * For a write, the bits holding the data contain the data 394 * being written. You would think that would cause the 395 * READ_DATA_VALID bit to be cleared, because the data bits 396 * no longer contain valid data from the most recent read 397 * operation. While that would be logical, that's not the 398 * case here: READ_DATA_VALID is only cleared when starting 399 * a read operation, and WRITE_DATA_DONE is only cleared 400 * when starting a write operation. 401 */ 402 if (I2C_OP_WRITE_P(op)) { 403 if (stat_val & IMCSMB_STATUS_WRITE_DATA_DONE) { 404 break; 405 } 406 } else { 407 if (stat_val & IMCSMB_STATUS_READ_DATA_VALID) { 408 break; 409 } 410 } 411 } 412 if (i == 0) { 413 rc = ETIMEDOUT; 414 aprint_debug_dev(sc->sc_dev, "transfer timeout\n"); 415 goto out; 416 } 417 418 /* It is generally the case that this bit indicates non-ACK, but it 419 * could also indicate other bus errors. There's no way to tell the 420 * difference. 421 */ 422 if (stat_val & IMCSMB_STATUS_BUS_ERROR_BIT) { 423 /* While it is not documented, empirically, SPD page-change 424 * commands (writes with DTI = 0x30) always complete with the 425 * error bit set. So, ignore it in those cases. 426 */ 427 if ((addr & 0x78) != 0x30) { 428 rc = ENODEV; 429 goto out; 430 } 431 } 432 433 /* For a read operation, copy the data out */ 434 if (I2C_OP_READ_P(op)) { 435 if (len == 2) { 436 /* The data is returned in bits [15:0]; as discussed 437 * above, byte-swap. 438 */ 439 lword = (uint16_t) (stat_val & 0xffff); 440 lword = htobe16(lword); 441 *(uint16_t *)buf = lword; 442 } else { 443 /* The data is returned in bits [7:0] */ 444 lbyte = (uint8_t) (stat_val & 0xff); 445 *(uint8_t *)buf = lbyte; 446 } 447 } 448 449 out: 450 /* Restore the original value of the control register. */ 451 pci_conf_write(sc->sc_pci_chipset_tag, sc->sc_pci_tag, 452 sc->sc_regs->smb_cntl, orig_cntl_val); 453 return rc; 454 }; 455 456 MODULE(MODULE_CLASS_DRIVER, imcsmb, "imc,iic"); 457 458 #ifdef _MODULE 459 #include "ioconf.c" 460 #endif 461 462 static int 463 imcsmb_modcmd(modcmd_t cmd, void *opaque) 464 { 465 int error = 0; 466 467 #ifdef _MODULE 468 switch (cmd) { 469 case MODULE_CMD_INIT: 470 error = config_init_component(cfdriver_ioconf_imcsmb, 471 cfattach_ioconf_imcsmb, cfdata_ioconf_imcsmb); 472 break; 473 case MODULE_CMD_FINI: 474 error = config_fini_component(cfdriver_ioconf_imcsmb, 475 cfattach_ioconf_imcsmb, cfdata_ioconf_imcsmb); 476 break; 477 default: 478 error = ENOTTY; 479 break; 480 } 481 #endif 482 483 return error; 484 } 485