1 /* $NetBSD: imcsmb.c,v 1.4 2021/04/24 23:36:51 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2018 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Goyette 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 34 * 35 * Authors: Joe Kloss; Ravi Pokala (rpokala@freebsd.org) 36 * 37 * Copyright (c) 2017-2018 Panasas 38 * All rights reserved. 39 * 40 * Redistribution and use in source and binary forms, with or without 41 * modification, are permitted provided that the following conditions 42 * are met: 43 * 1. Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * 2. Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in the 47 * documentation and/or other materials provided with the distribution. 48 * 49 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 50 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 51 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 52 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 53 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 54 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 55 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 56 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 57 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 58 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 59 * SUCH DAMAGE. 60 */ 61 62 /* 63 * Driver for the SMBus controllers in Intel's Integrated Memory Controllers 64 * in certain CPUs. A more detailed description of this device is present 65 * in imc.c 66 */ 67 68 #include <sys/cdefs.h> 69 __KERNEL_RCSID(0, "$NetBSD: imcsmb.c,v 1.4 2021/04/24 23:36:51 thorpej Exp $"); 70 71 #include <sys/param.h> 72 #include <sys/kernel.h> 73 #include <sys/module.h> 74 #include <sys/endian.h> 75 #include <sys/errno.h> 76 #include <sys/mutex.h> 77 #include <sys/bus.h> 78 79 #include <dev/pci/pcidevs.h> 80 #include <dev/pci/pcivar.h> 81 #include <dev/pci/pcireg.h> 82 83 #include <dev/i2c/i2cvar.h> 84 85 #include "imcsmb_reg.h" 86 #include "imcsmb_var.h" 87 88 /* Device methods */ 89 static int imcsmb_probe(device_t, cfdata_t, void *); 90 static void imcsmb_attach(device_t, device_t, void *); 91 static int imcsmb_detach(device_t, int flags); 92 static int imcsmb_rescan(device_t, const char *, const int *); 93 static void imcsmb_chdet(device_t, device_t); 94 95 CFATTACH_DECL3_NEW(imcsmb, sizeof(struct imcsmb_softc), 96 imcsmb_probe, imcsmb_attach, imcsmb_detach, NULL, imcsmb_rescan, 97 imcsmb_chdet, 0); 98 99 /* Bus access control methods */ 100 static int imcsmb_acquire_bus(void *cookie, int flags); 101 static void imcsmb_release_bus(void *cookie, int flags); 102 103 /* SMBus methods */ 104 static int imcsmb_exec(void *cookie, i2c_op_t, i2c_addr_t, const void *, 105 size_t, void *, size_t, int); 106 107 /** 108 * device_attach() method. Set up the softc, including getting the set of the 109 * parent imcsmb_pci's registers that we will use. Create the smbus(4) device, 110 * which any SMBus slave device drivers will connect to. Probe and attach 111 * anything which might be downstream. 112 * 113 * @author rpokala 114 * 115 * @param[in,out] dev 116 * Device being attached. 117 */ 118 119 static void 120 imcsmb_attach(device_t parent, device_t self, void *aux) 121 { 122 struct imcsmb_softc *sc = device_private(self); 123 struct imc_attach_args *imca = aux; 124 125 aprint_naive("\n"); 126 aprint_normal(": SMBus controller\n"); 127 128 /* Initialize private state */ 129 sc->sc_dev = self; 130 sc->sc_regs = imca->ia_regs; 131 sc->sc_pci_tag = imca->ia_pci_tag; 132 sc->sc_pci_chipset_tag = imca->ia_pci_chipset_tag; 133 134 if (!pmf_device_register(self, NULL, NULL)) 135 aprint_error_dev(self, "couldn't establish power handler\n"); 136 137 imcsmb_rescan(self, NULL, NULL); 138 } 139 140 static int 141 imcsmb_rescan(device_t self, const char *ifattr, const int *locs) 142 { 143 struct imcsmb_softc *sc = device_private(self); 144 struct i2cbus_attach_args iba; 145 146 /* Create the i2cbus child */ 147 if (sc->sc_smbus != NULL) 148 return 0; 149 150 iic_tag_init(&sc->sc_i2c_tag); 151 sc->sc_i2c_tag.ic_cookie = sc; 152 sc->sc_i2c_tag.ic_acquire_bus = imcsmb_acquire_bus; 153 sc->sc_i2c_tag.ic_release_bus = imcsmb_release_bus; 154 sc->sc_i2c_tag.ic_exec = imcsmb_exec; 155 156 memset(&iba, 0, sizeof(iba)); 157 iba.iba_tag = &sc->sc_i2c_tag; 158 sc->sc_smbus = config_found(self, &iba, iicbus_print, CFARG_EOL); 159 160 if (sc->sc_smbus == NULL) { 161 aprint_normal_dev(self, "no child found\n"); 162 return ENXIO; 163 } 164 165 return 0; 166 } 167 168 static void 169 imcsmb_chdet(device_t self, device_t child) 170 { 171 struct imcsmb_softc *sc = device_private(self); 172 173 if (child == sc->sc_smbus) 174 sc->sc_smbus = NULL; 175 else KASSERT(child == NULL); 176 } 177 178 /** 179 * device_detach() method. attach() didn't do any allocations, so there's 180 * nothing special needed 181 */ 182 static int 183 imcsmb_detach(device_t self, int flags) 184 { 185 int error; 186 struct imcsmb_softc *sc = device_private(self); 187 188 if (sc->sc_smbus != NULL) { 189 error = config_detach(sc->sc_smbus, flags); 190 if (error) 191 return error; 192 } 193 194 pmf_device_deregister(self); 195 iic_tag_fini(&sc->sc_i2c_tag); 196 return 0; 197 } 198 199 /** 200 * device_probe() method. All the actual probing was done by the imc 201 * parent, so just report success. 202 * 203 * @author Joe Kloss 204 * 205 * @param[in,out] dev 206 * Device being probed. 207 */ 208 static int 209 imcsmb_probe(device_t parent, cfdata_t match, void *aux) 210 { 211 212 return 1; 213 } 214 215 static int 216 imcsmb_acquire_bus(void *cookie, int flags) 217 { 218 struct imcsmb_softc *sc = cookie; 219 220 if (cold) 221 return 0; 222 223 imc_callback(sc, IMC_BIOS_DISABLE); 224 225 return 0; 226 } 227 228 static void 229 imcsmb_release_bus(void *cookie, int flags) 230 { 231 struct imcsmb_softc *sc = cookie; 232 233 if (cold) 234 return; 235 236 imc_callback(sc, IMC_BIOS_ENABLE); 237 } 238 239 static int 240 imcsmb_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, const void *cmdbuf, 241 size_t cmdlen, void *buf, size_t len, int flags) 242 { 243 struct imcsmb_softc *sc = cookie; 244 int i; 245 int rc = 0; 246 uint32_t cmd_val; 247 uint32_t cntl_val; 248 uint32_t orig_cntl_val; 249 uint32_t stat_val; 250 uint16_t *word; 251 uint16_t lword; 252 uint8_t *byte; 253 uint8_t lbyte; 254 uint8_t cmd; 255 256 if ((cmdlen != 1) || (len > 2) || (len < 1)) 257 return EINVAL; 258 259 byte = (uint8_t *) buf; 260 word = (uint16_t *) buf; 261 lbyte = *byte; 262 lword = *word; 263 264 /* We modify the value of the control register; save the original, so 265 * we can restore it later 266 */ 267 orig_cntl_val = pci_conf_read(sc->sc_pci_chipset_tag, sc->sc_pci_tag, 268 sc->sc_regs->smb_cntl); 269 270 cntl_val = orig_cntl_val; 271 272 /* 273 * Set up the SMBCNTL register 274 */ 275 276 /* [31:28] Clear the existing value of the DTI bits, then set them to 277 * the four high bits of the slave address. 278 */ 279 cntl_val &= ~IMCSMB_CNTL_DTI_MASK; 280 cntl_val |= ((uint32_t) addr & 0x78) << 25; 281 282 /* [27:27] Set the CLK_OVERRIDE bit, to enable normal operation */ 283 cntl_val |= IMCSMB_CNTL_CLK_OVERRIDE; 284 285 /* [26:26] Clear the WRITE_DISABLE bit; the datasheet says this isn't 286 * necessary, but empirically, it is. 287 */ 288 cntl_val &= ~IMCSMB_CNTL_WRITE_DISABLE_BIT; 289 290 /* [9:9] Clear the POLL_EN bit, to stop the hardware TSOD polling. */ 291 cntl_val &= ~IMCSMB_CNTL_POLL_EN; 292 293 /* 294 * Set up the SMBCMD register 295 */ 296 297 /* [31:31] Set the TRIGGER bit; when this gets written, the controller 298 * will issue the command. 299 */ 300 cmd_val = IMCSMB_CMD_TRIGGER_BIT; 301 302 /* [29:29] For word operations, set the WORD_ACCESS bit. */ 303 if (len == 2) { 304 cmd_val |= IMCSMB_CMD_WORD_ACCESS; 305 } 306 307 /* [27:27] For write operations, set the WRITE bit. */ 308 if (I2C_OP_WRITE_P(op)) { 309 cmd_val |= IMCSMB_CMD_WRITE_BIT; 310 } 311 312 /* [26:24] The three non-DTI, non-R/W bits of the slave address. */ 313 cmd_val |= (uint32_t) ((addr & 0x7) << 24); 314 315 /* [23:16] The command (offset in the case of an EEPROM, or register in 316 * the case of TSOD or NVDIMM controller). 317 */ 318 cmd = *((const uint8_t *) cmdbuf); 319 cmd_val |= (uint32_t) (cmd << 16); 320 321 /* [15:0] The data to be written for a write operation. */ 322 if (I2C_OP_WRITE_P(op)) { 323 if (len == 2) { 324 /* The datasheet says the controller uses different 325 * endianness for word operations on I2C vs SMBus! 326 * I2C: [15:8] = MSB; [7:0] = LSB 327 * SMB: [15:8] = LSB; [7:0] = MSB 328 * As a practical matter, this controller is very 329 * specifically for use with DIMMs, the SPD (and 330 * NVDIMM controllers) are only accessed as bytes, 331 * the temperature sensor is only accessed as words, and 332 * the temperature sensors are I2C. Thus, byte-swap the 333 * word. 334 */ 335 lword = htobe16(*(uint16_t *)buf); 336 } else { 337 /* For byte operations, the data goes in the LSB, and 338 * the MSB is a don't care. 339 */ 340 lword = *(uint8_t *)buf; 341 } 342 cmd_val |= lword; 343 } 344 345 /* Write the updated value to the control register first, to disable 346 * the hardware TSOD polling. 347 */ 348 pci_conf_write(sc->sc_pci_chipset_tag, sc->sc_pci_tag, 349 sc->sc_regs->smb_cntl, cntl_val); 350 351 /* Poll on the BUSY bit in the status register until clear, or timeout. 352 * We just cleared the auto-poll bit, so we need to make sure the device 353 * is idle before issuing a command. We can safely timeout after 35 ms, 354 * as this is the maximum time the SMBus spec allows for a transaction. 355 */ 356 for (i = 4; i != 0; i--) { 357 stat_val = pci_conf_read(sc->sc_pci_chipset_tag, 358 sc->sc_pci_tag, sc->sc_regs->smb_stat); 359 if (! (stat_val & IMCSMB_STATUS_BUSY_BIT)) { 360 break; 361 } 362 delay(100); /* wait 10ms */ 363 } 364 365 if (i == 0) { 366 aprint_debug_dev(sc->sc_dev, 367 "transfer: timeout waiting for device to settle\n"); 368 } 369 370 /* Now that polling has stopped, we can write the command register. This 371 * starts the SMBus command. 372 */ 373 pci_conf_write(sc->sc_pci_chipset_tag, sc->sc_pci_tag, 374 sc->sc_regs->smb_cmd, cmd_val); 375 376 /* Wait for WRITE_DATA_DONE/READ_DATA_VALID to be set, or timeout and 377 * fail. We wait up to 35ms. 378 */ 379 for (i = 35000; i != 0; i -= 10) 380 { 381 delay(10); 382 stat_val = pci_conf_read(sc->sc_pci_chipset_tag, 383 sc->sc_pci_tag, sc->sc_regs->smb_stat); 384 /* 385 * For a write, the bits holding the data contain the data 386 * being written. You would think that would cause the 387 * READ_DATA_VALID bit to be cleared, because the data bits 388 * no longer contain valid data from the most recent read 389 * operation. While that would be logical, that's not the 390 * case here: READ_DATA_VALID is only cleared when starting 391 * a read operation, and WRITE_DATA_DONE is only cleared 392 * when starting a write operation. 393 */ 394 if (I2C_OP_WRITE_P(op)) { 395 if (stat_val & IMCSMB_STATUS_WRITE_DATA_DONE) { 396 break; 397 } 398 } else { 399 if (stat_val & IMCSMB_STATUS_READ_DATA_VALID) { 400 break; 401 } 402 } 403 } 404 if (i == 0) { 405 rc = ETIMEDOUT; 406 aprint_debug_dev(sc->sc_dev, "transfer timeout\n"); 407 goto out; 408 } 409 410 /* It is generally the case that this bit indicates non-ACK, but it 411 * could also indicate other bus errors. There's no way to tell the 412 * difference. 413 */ 414 if (stat_val & IMCSMB_STATUS_BUS_ERROR_BIT) { 415 /* While it is not documented, empirically, SPD page-change 416 * commands (writes with DTI = 0x30) always complete with the 417 * error bit set. So, ignore it in those cases. 418 */ 419 if ((addr & 0x78) != 0x30) { 420 rc = ENODEV; 421 goto out; 422 } 423 } 424 425 /* For a read operation, copy the data out */ 426 if (I2C_OP_READ_P(op)) { 427 if (len == 2) { 428 /* The data is returned in bits [15:0]; as discussed 429 * above, byte-swap. 430 */ 431 lword = (uint16_t) (stat_val & 0xffff); 432 lword = htobe16(lword); 433 *(uint16_t *)buf = lword; 434 } else { 435 /* The data is returned in bits [7:0] */ 436 lbyte = (uint8_t) (stat_val & 0xff); 437 *(uint8_t *)buf = lbyte; 438 } 439 } 440 441 out: 442 /* Restore the original value of the control register. */ 443 pci_conf_write(sc->sc_pci_chipset_tag, sc->sc_pci_tag, 444 sc->sc_regs->smb_cntl, orig_cntl_val); 445 return rc; 446 }; 447 448 MODULE(MODULE_CLASS_DRIVER, imcsmb, "imc,iic"); 449 450 #ifdef _MODULE 451 #include "ioconf.c" 452 #endif 453 454 static int 455 imcsmb_modcmd(modcmd_t cmd, void *opaque) 456 { 457 int error = 0; 458 459 #ifdef _MODULE 460 switch (cmd) { 461 case MODULE_CMD_INIT: 462 error = config_init_component(cfdriver_ioconf_imcsmb, 463 cfattach_ioconf_imcsmb, cfdata_ioconf_imcsmb); 464 break; 465 case MODULE_CMD_FINI: 466 error = config_fini_component(cfdriver_ioconf_imcsmb, 467 cfattach_ioconf_imcsmb, cfdata_ioconf_imcsmb); 468 break; 469 default: 470 error = ENOTTY; 471 break; 472 } 473 #endif 474 475 return error; 476 } 477