1 /* $NetBSD: imcsmb.c,v 1.3 2019/12/22 23:23:31 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2018 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Goyette 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 34 * 35 * Authors: Joe Kloss; Ravi Pokala (rpokala@freebsd.org) 36 * 37 * Copyright (c) 2017-2018 Panasas 38 * All rights reserved. 39 * 40 * Redistribution and use in source and binary forms, with or without 41 * modification, are permitted provided that the following conditions 42 * are met: 43 * 1. Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * 2. Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in the 47 * documentation and/or other materials provided with the distribution. 48 * 49 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 50 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 51 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 52 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 53 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 54 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 55 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 56 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 57 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 58 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 59 * SUCH DAMAGE. 60 */ 61 62 /* 63 * Driver for the SMBus controllers in Intel's Integrated Memory Controllers 64 * in certain CPUs. A more detailed description of this device is present 65 * in imc.c 66 */ 67 68 #include <sys/cdefs.h> 69 __KERNEL_RCSID(0, "$NetBSD: imcsmb.c,v 1.3 2019/12/22 23:23:31 thorpej Exp $"); 70 71 #include <sys/param.h> 72 #include <sys/kernel.h> 73 #include <sys/module.h> 74 #include <sys/endian.h> 75 #include <sys/errno.h> 76 #include <sys/mutex.h> 77 #include <sys/bus.h> 78 79 #include <dev/pci/pcidevs.h> 80 #include <dev/pci/pcivar.h> 81 #include <dev/pci/pcireg.h> 82 83 #include <dev/i2c/i2cvar.h> 84 85 #include "imcsmb_reg.h" 86 #include "imcsmb_var.h" 87 88 /* Device methods */ 89 static int imcsmb_probe(device_t, cfdata_t, void *); 90 static void imcsmb_attach(device_t, device_t, void *); 91 static int imcsmb_detach(device_t, int flags); 92 static int imcsmb_rescan(device_t, const char *, const int *); 93 static void imcsmb_chdet(device_t, device_t); 94 95 CFATTACH_DECL3_NEW(imcsmb, sizeof(struct imcsmb_softc), 96 imcsmb_probe, imcsmb_attach, imcsmb_detach, NULL, imcsmb_rescan, 97 imcsmb_chdet, 0); 98 99 /* Bus access control methods */ 100 static int imcsmb_acquire_bus(void *cookie, int flags); 101 static void imcsmb_release_bus(void *cookie, int flags); 102 103 /* SMBus methods */ 104 static int imcsmb_exec(void *cookie, i2c_op_t, i2c_addr_t, const void *, 105 size_t, void *, size_t, int); 106 107 /** 108 * device_attach() method. Set up the softc, including getting the set of the 109 * parent imcsmb_pci's registers that we will use. Create the smbus(4) device, 110 * which any SMBus slave device drivers will connect to. Probe and attach 111 * anything which might be downstream. 112 * 113 * @author rpokala 114 * 115 * @param[in,out] dev 116 * Device being attached. 117 */ 118 119 static void 120 imcsmb_attach(device_t parent, device_t self, void *aux) 121 { 122 struct imcsmb_softc *sc = device_private(self); 123 struct imc_attach_args *imca = aux; 124 125 aprint_naive("\n"); 126 aprint_normal(": SMBus controller\n"); 127 128 /* Initialize private state */ 129 sc->sc_dev = self; 130 sc->sc_regs = imca->ia_regs; 131 sc->sc_pci_tag = imca->ia_pci_tag; 132 sc->sc_pci_chipset_tag = imca->ia_pci_chipset_tag; 133 134 if (!pmf_device_register(self, NULL, NULL)) 135 aprint_error_dev(self, "couldn't establish power handler\n"); 136 137 imcsmb_rescan(self, "i2cbus", 0); 138 } 139 140 static int 141 imcsmb_rescan(device_t self, const char *ifattr, const int *flags) 142 { 143 struct imcsmb_softc *sc = device_private(self); 144 struct i2cbus_attach_args iba; 145 146 if (!ifattr_match(ifattr, "i2cbus")) 147 return 0; 148 149 /* Create the i2cbus child */ 150 if (sc->sc_smbus != NULL) 151 return 0; 152 153 iic_tag_init(&sc->sc_i2c_tag); 154 sc->sc_i2c_tag.ic_cookie = sc; 155 sc->sc_i2c_tag.ic_acquire_bus = imcsmb_acquire_bus; 156 sc->sc_i2c_tag.ic_release_bus = imcsmb_release_bus; 157 sc->sc_i2c_tag.ic_exec = imcsmb_exec; 158 159 memset(&iba, 0, sizeof(iba)); 160 iba.iba_tag = &sc->sc_i2c_tag; 161 sc->sc_smbus = config_found_ia(self, ifattr, &iba, iicbus_print); 162 163 if (sc->sc_smbus == NULL) { 164 aprint_normal_dev(self, "no child found\n"); 165 return ENXIO; 166 } 167 168 return 0; 169 } 170 171 static void 172 imcsmb_chdet(device_t self, device_t child) 173 { 174 struct imcsmb_softc *sc = device_private(self); 175 176 if (child == sc->sc_smbus) 177 sc->sc_smbus = NULL; 178 else KASSERT(child == NULL); 179 } 180 181 /** 182 * device_detach() method. attach() didn't do any allocations, so there's 183 * nothing special needed 184 */ 185 static int 186 imcsmb_detach(device_t self, int flags) 187 { 188 int error; 189 struct imcsmb_softc *sc = device_private(self); 190 191 if (sc->sc_smbus != NULL) { 192 error = config_detach(sc->sc_smbus, flags); 193 if (error) 194 return error; 195 } 196 197 pmf_device_deregister(self); 198 iic_tag_fini(&sc->sc_i2c_tag); 199 return 0; 200 } 201 202 /** 203 * device_probe() method. All the actual probing was done by the imc 204 * parent, so just report success. 205 * 206 * @author Joe Kloss 207 * 208 * @param[in,out] dev 209 * Device being probed. 210 */ 211 static int 212 imcsmb_probe(device_t parent, cfdata_t match, void *aux) 213 { 214 215 return 1; 216 } 217 218 static int 219 imcsmb_acquire_bus(void *cookie, int flags) 220 { 221 struct imcsmb_softc *sc = cookie; 222 223 if (cold) 224 return 0; 225 226 imc_callback(sc, IMC_BIOS_DISABLE); 227 228 return 0; 229 } 230 231 static void 232 imcsmb_release_bus(void *cookie, int flags) 233 { 234 struct imcsmb_softc *sc = cookie; 235 236 if (cold) 237 return; 238 239 imc_callback(sc, IMC_BIOS_ENABLE); 240 } 241 242 static int 243 imcsmb_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, const void *cmdbuf, 244 size_t cmdlen, void *buf, size_t len, int flags) 245 { 246 struct imcsmb_softc *sc = cookie; 247 int i; 248 int rc = 0; 249 uint32_t cmd_val; 250 uint32_t cntl_val; 251 uint32_t orig_cntl_val; 252 uint32_t stat_val; 253 uint16_t *word; 254 uint16_t lword; 255 uint8_t *byte; 256 uint8_t lbyte; 257 uint8_t cmd; 258 259 if ((cmdlen != 1) || (len > 2) || (len < 1)) 260 return EINVAL; 261 262 byte = (uint8_t *) buf; 263 word = (uint16_t *) buf; 264 lbyte = *byte; 265 lword = *word; 266 267 /* We modify the value of the control register; save the original, so 268 * we can restore it later 269 */ 270 orig_cntl_val = pci_conf_read(sc->sc_pci_chipset_tag, sc->sc_pci_tag, 271 sc->sc_regs->smb_cntl); 272 273 cntl_val = orig_cntl_val; 274 275 /* 276 * Set up the SMBCNTL register 277 */ 278 279 /* [31:28] Clear the existing value of the DTI bits, then set them to 280 * the four high bits of the slave address. 281 */ 282 cntl_val &= ~IMCSMB_CNTL_DTI_MASK; 283 cntl_val |= ((uint32_t) addr & 0x78) << 25; 284 285 /* [27:27] Set the CLK_OVERRIDE bit, to enable normal operation */ 286 cntl_val |= IMCSMB_CNTL_CLK_OVERRIDE; 287 288 /* [26:26] Clear the WRITE_DISABLE bit; the datasheet says this isn't 289 * necessary, but empirically, it is. 290 */ 291 cntl_val &= ~IMCSMB_CNTL_WRITE_DISABLE_BIT; 292 293 /* [9:9] Clear the POLL_EN bit, to stop the hardware TSOD polling. */ 294 cntl_val &= ~IMCSMB_CNTL_POLL_EN; 295 296 /* 297 * Set up the SMBCMD register 298 */ 299 300 /* [31:31] Set the TRIGGER bit; when this gets written, the controller 301 * will issue the command. 302 */ 303 cmd_val = IMCSMB_CMD_TRIGGER_BIT; 304 305 /* [29:29] For word operations, set the WORD_ACCESS bit. */ 306 if (len == 2) { 307 cmd_val |= IMCSMB_CMD_WORD_ACCESS; 308 } 309 310 /* [27:27] For write operations, set the WRITE bit. */ 311 if (I2C_OP_WRITE_P(op)) { 312 cmd_val |= IMCSMB_CMD_WRITE_BIT; 313 } 314 315 /* [26:24] The three non-DTI, non-R/W bits of the slave address. */ 316 cmd_val |= (uint32_t) ((addr & 0x7) << 24); 317 318 /* [23:16] The command (offset in the case of an EEPROM, or register in 319 * the case of TSOD or NVDIMM controller). 320 */ 321 cmd = *((const uint8_t *) cmdbuf); 322 cmd_val |= (uint32_t) (cmd << 16); 323 324 /* [15:0] The data to be written for a write operation. */ 325 if (I2C_OP_WRITE_P(op)) { 326 if (len == 2) { 327 /* The datasheet says the controller uses different 328 * endianness for word operations on I2C vs SMBus! 329 * I2C: [15:8] = MSB; [7:0] = LSB 330 * SMB: [15:8] = LSB; [7:0] = MSB 331 * As a practical matter, this controller is very 332 * specifically for use with DIMMs, the SPD (and 333 * NVDIMM controllers) are only accessed as bytes, 334 * the temperature sensor is only accessed as words, and 335 * the temperature sensors are I2C. Thus, byte-swap the 336 * word. 337 */ 338 lword = htobe16(*(uint16_t *)buf); 339 } else { 340 /* For byte operations, the data goes in the LSB, and 341 * the MSB is a don't care. 342 */ 343 lword = *(uint8_t *)buf; 344 } 345 cmd_val |= lword; 346 } 347 348 /* Write the updated value to the control register first, to disable 349 * the hardware TSOD polling. 350 */ 351 pci_conf_write(sc->sc_pci_chipset_tag, sc->sc_pci_tag, 352 sc->sc_regs->smb_cntl, cntl_val); 353 354 /* Poll on the BUSY bit in the status register until clear, or timeout. 355 * We just cleared the auto-poll bit, so we need to make sure the device 356 * is idle before issuing a command. We can safely timeout after 35 ms, 357 * as this is the maximum time the SMBus spec allows for a transaction. 358 */ 359 for (i = 4; i != 0; i--) { 360 stat_val = pci_conf_read(sc->sc_pci_chipset_tag, 361 sc->sc_pci_tag, sc->sc_regs->smb_stat); 362 if (! (stat_val & IMCSMB_STATUS_BUSY_BIT)) { 363 break; 364 } 365 delay(100); /* wait 10ms */ 366 } 367 368 if (i == 0) { 369 aprint_debug_dev(sc->sc_dev, 370 "transfer: timeout waiting for device to settle\n"); 371 } 372 373 /* Now that polling has stopped, we can write the command register. This 374 * starts the SMBus command. 375 */ 376 pci_conf_write(sc->sc_pci_chipset_tag, sc->sc_pci_tag, 377 sc->sc_regs->smb_cmd, cmd_val); 378 379 /* Wait for WRITE_DATA_DONE/READ_DATA_VALID to be set, or timeout and 380 * fail. We wait up to 35ms. 381 */ 382 for (i = 35000; i != 0; i -= 10) 383 { 384 delay(10); 385 stat_val = pci_conf_read(sc->sc_pci_chipset_tag, 386 sc->sc_pci_tag, sc->sc_regs->smb_stat); 387 /* 388 * For a write, the bits holding the data contain the data 389 * being written. You would think that would cause the 390 * READ_DATA_VALID bit to be cleared, because the data bits 391 * no longer contain valid data from the most recent read 392 * operation. While that would be logical, that's not the 393 * case here: READ_DATA_VALID is only cleared when starting 394 * a read operation, and WRITE_DATA_DONE is only cleared 395 * when starting a write operation. 396 */ 397 if (I2C_OP_WRITE_P(op)) { 398 if (stat_val & IMCSMB_STATUS_WRITE_DATA_DONE) { 399 break; 400 } 401 } else { 402 if (stat_val & IMCSMB_STATUS_READ_DATA_VALID) { 403 break; 404 } 405 } 406 } 407 if (i == 0) { 408 rc = ETIMEDOUT; 409 aprint_debug_dev(sc->sc_dev, "transfer timeout\n"); 410 goto out; 411 } 412 413 /* It is generally the case that this bit indicates non-ACK, but it 414 * could also indicate other bus errors. There's no way to tell the 415 * difference. 416 */ 417 if (stat_val & IMCSMB_STATUS_BUS_ERROR_BIT) { 418 /* While it is not documented, empirically, SPD page-change 419 * commands (writes with DTI = 0x30) always complete with the 420 * error bit set. So, ignore it in those cases. 421 */ 422 if ((addr & 0x78) != 0x30) { 423 rc = ENODEV; 424 goto out; 425 } 426 } 427 428 /* For a read operation, copy the data out */ 429 if (I2C_OP_READ_P(op)) { 430 if (len == 2) { 431 /* The data is returned in bits [15:0]; as discussed 432 * above, byte-swap. 433 */ 434 lword = (uint16_t) (stat_val & 0xffff); 435 lword = htobe16(lword); 436 *(uint16_t *)buf = lword; 437 } else { 438 /* The data is returned in bits [7:0] */ 439 lbyte = (uint8_t) (stat_val & 0xff); 440 *(uint8_t *)buf = lbyte; 441 } 442 } 443 444 out: 445 /* Restore the original value of the control register. */ 446 pci_conf_write(sc->sc_pci_chipset_tag, sc->sc_pci_tag, 447 sc->sc_regs->smb_cntl, orig_cntl_val); 448 return rc; 449 }; 450 451 MODULE(MODULE_CLASS_DRIVER, imcsmb, "imc,iic"); 452 453 #ifdef _MODULE 454 #include "ioconf.c" 455 #endif 456 457 static int 458 imcsmb_modcmd(modcmd_t cmd, void *opaque) 459 { 460 int error = 0; 461 462 #ifdef _MODULE 463 switch (cmd) { 464 case MODULE_CMD_INIT: 465 error = config_init_component(cfdriver_ioconf_imcsmb, 466 cfattach_ioconf_imcsmb, cfdata_ioconf_imcsmb); 467 break; 468 case MODULE_CMD_FINI: 469 error = config_fini_component(cfdriver_ioconf_imcsmb, 470 cfattach_ioconf_imcsmb, cfdata_ioconf_imcsmb); 471 break; 472 default: 473 error = ENOTTY; 474 break; 475 } 476 #endif 477 478 return error; 479 } 480