1 /* $NetBSD: ichlpcib.c,v 1.61 2023/05/09 23:11:09 riastradh Exp $ */ 2 3 /*- 4 * Copyright (c) 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Minoura Makoto and Matthew R. Green. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Intel I/O Controller Hub (ICHn) LPC Interface Bridge driver 34 * 35 * LPC Interface Bridge is basically a pcib (PCI-ISA Bridge), but has 36 * some power management and monitoring functions. 37 * Currently we support the watchdog timer, SpeedStep (on some systems), 38 * the gpio interface, hpet timer, hardware random number generator, 39 * and the power management timer. 40 */ 41 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "$NetBSD: ichlpcib.c,v 1.61 2023/05/09 23:11:09 riastradh Exp $"); 44 45 #include <sys/types.h> 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/device.h> 49 #include <sys/sysctl.h> 50 #include <sys/timetc.h> 51 #include <sys/gpio.h> 52 #include <sys/bus.h> 53 54 #include <dev/pci/pcivar.h> 55 #include <dev/pci/pcireg.h> 56 #include <dev/pci/pcidevs.h> 57 58 #include <dev/gpio/gpiovar.h> 59 60 #include <dev/ic/acpipmtimer.h> 61 #include <dev/ic/i82801lpcreg.h> 62 #include <dev/ic/i82801lpcvar.h> 63 #include <dev/ic/hpetreg.h> 64 #include <dev/ic/hpetvar.h> 65 66 #include <arch/x86/pci/tco.h> 67 68 #include "pcibvar.h" 69 #include "gpio.h" 70 #include "fwhrng.h" 71 72 #define LPCIB_GPIO_NPINS 64 73 74 struct lpcib_softc { 75 /* we call pcibattach() which assumes this starts like this: */ 76 struct pcib_softc sc_pcib; 77 78 struct pci_attach_args sc_pa; 79 int sc_has_rcba; 80 int sc_has_ich5_hpet; 81 82 /* RCBA */ 83 bus_space_tag_t sc_rcbat; 84 bus_space_handle_t sc_rcbah; 85 pcireg_t sc_rcba_reg; 86 87 /* Power management variables. */ 88 bus_space_tag_t sc_pmt; 89 bus_space_handle_t sc_pmh; 90 bus_size_t sc_iosize; 91 92 /* TCO variables. */ 93 bus_space_tag_t sc_tcot; 94 bus_space_handle_t sc_tcoh; 95 bus_size_t sc_tcosz; 96 97 /* HPET variables. */ 98 uint32_t sc_hpet_reg; 99 100 #if NGPIO > 0 101 device_t sc_gpiobus; 102 kmutex_t sc_gpio_mtx; 103 bus_space_tag_t sc_gpio_iot; 104 bus_space_handle_t sc_gpio_ioh; 105 bus_size_t sc_gpio_ios; 106 struct gpio_chipset_tag sc_gpio_gc; 107 gpio_pin_t sc_gpio_pins[LPCIB_GPIO_NPINS]; 108 #endif 109 110 #if NFWHRNG > 0 111 device_t sc_fwhbus; 112 #endif 113 114 /* Speedstep */ 115 pcireg_t sc_pmcon_orig; 116 117 /* Power management */ 118 pcireg_t sc_pirq[2]; 119 pcireg_t sc_pmcon; 120 pcireg_t sc_fwhsel2; 121 122 /* Child devices */ 123 device_t sc_tco; 124 device_t sc_hpetbus; 125 acpipmtimer_t sc_pmtimer; 126 pcireg_t sc_acpi_cntl; 127 128 struct sysctllog *sc_log; 129 }; 130 131 static int lpcibmatch(device_t, cfdata_t, void *); 132 static void lpcibattach(device_t, device_t, void *); 133 static int lpcibdetach(device_t, int); 134 static void lpcibchilddet(device_t, device_t); 135 static int lpcibrescan(device_t, const char *, const int *); 136 static bool lpcib_suspend(device_t, const pmf_qual_t *); 137 static bool lpcib_resume(device_t, const pmf_qual_t *); 138 static bool lpcib_shutdown(device_t, int); 139 140 static void pmtimer_configure(device_t); 141 static void pmtimer_unconfigure(device_t, int); 142 143 static void tcotimer_configure(device_t); 144 145 static void speedstep_configure(device_t); 146 static void speedstep_unconfigure(device_t); 147 static int speedstep_sysctl_helper(SYSCTLFN_ARGS); 148 149 static void lpcib_hpet_configure(device_t); 150 151 #if NGPIO > 0 152 static void lpcib_gpio_configure(device_t); 153 static void lpcib_gpio_unconfigure(device_t); 154 static int lpcib_gpio_pin_read(void *, int); 155 static void lpcib_gpio_pin_write(void *, int, int); 156 static void lpcib_gpio_pin_ctl(void *, int, int); 157 #endif 158 159 #if NFWHRNG > 0 160 static void lpcib_fwh_configure(device_t); 161 #endif 162 163 struct lpcib_softc *speedstep_cookie; /* XXX */ 164 165 CFATTACH_DECL2_NEW(ichlpcib, sizeof(struct lpcib_softc), 166 lpcibmatch, lpcibattach, lpcibdetach, NULL, lpcibrescan, lpcibchilddet); 167 168 static const struct lpcib_device { 169 pcireg_t vendor, product; 170 int has_rcba; 171 int has_ich5_hpet; 172 } lpcib_devices[] = { 173 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_3400_LPC, 1, 0 }, 174 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_3420_LPC, 1, 0 }, 175 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_3450_LPC, 1, 0 }, 176 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_6300ESB_LPC, 1, 0 }, 177 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_63XXESB_LPC, 1, 0 }, 178 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AA_LPC, 0, 0 }, 179 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AB_LPC, 0, 0 }, 180 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BA_LPC, 0, 0 }, 181 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BAM_LPC, 0, 0 }, 182 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CA_LPC, 0, 0 }, 183 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CAM_LPC, 0, 0 }, 184 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DB_LPC, 0, 0 }, 185 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DBM_LPC, 0, 0 }, 186 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801E_LPC, 0, 1 }, 187 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801EB_LPC, 0, 1 }, 188 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801FB_LPC, 1, 0 }, 189 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801FBM_LPC, 1, 0 }, 190 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801G_LPC, 1, 0 }, 191 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GBM_LPC, 1, 0 }, 192 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GH_LPC, 1, 0 }, 193 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GHM_LPC, 1, 0 }, 194 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_LPC, 1, 0 }, 195 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HEM_LPC, 1, 0 }, 196 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HH_LPC, 1, 0 }, 197 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HO_LPC, 1, 0 }, 198 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HBM_LPC, 1, 0 }, 199 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IB_LPC, 1, 0 }, 200 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IH_LPC, 1, 0 }, 201 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IM_LPC, 1, 0 }, 202 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IO_LPC, 1, 0 }, 203 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IR_LPC, 1, 0 }, 204 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IEM_LPC, 1, 0 }, 205 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801JD_LPC, 1, 0 }, 206 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801JDO_LPC, 1, 0 }, 207 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801JIB_LPC, 1, 0 }, 208 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801JIR_LPC, 1, 0 }, 209 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C202_LPC, 1, 0 }, 210 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C204_LPC, 1, 0 }, 211 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C206_LPC, 1, 0 }, 212 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C216_LPC, 1, 0 }, 213 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_NM10_LPC, 1, 0 }, 214 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_H55_LPC, 1, 0 }, 215 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_H57_LPC, 1, 0 }, 216 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_HM55_LPC, 1, 0 }, 217 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_HM57_LPC, 1, 0 }, 218 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_P55_LPC, 1, 0 }, 219 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PM55_LPC, 1, 0 }, 220 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Q57_LPC, 1, 0 }, 221 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_QM57_LPC, 1, 0 }, 222 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_QS57_LPC, 1, 0 }, 223 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_B65_LPC, 1, 0 }, 224 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_H61_LPC, 1, 0 }, 225 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_H67_LPC, 1, 0 }, 226 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_HM65_LPC, 1, 0 }, 227 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_HM67_LPC, 1, 0 }, 228 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_P67_LPC, 1, 0 }, 229 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Q65_LPC, 1, 0 }, 230 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Q67_LPC, 1, 0 }, 231 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_QM67_LPC, 1, 0 }, 232 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_QS67_LPC, 1, 0 }, 233 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_UM67_LPC, 1, 0 }, 234 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Z68_LPC, 1, 0 }, 235 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_B75_LPC, 1, 0 }, 236 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_H77_LPC, 1, 0 }, 237 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MOBILE_HM70_LPC, 1, 0 }, 238 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MOBILE_HM75_LPC, 1, 0 }, 239 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MOBILE_HM76_LPC, 1, 0 }, 240 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MOBILE_HM77_LPC, 1, 0 }, 241 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MOBILE_QM77_LPC, 1, 0 }, 242 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MOBILE_QS77_LPC, 1, 0 }, 243 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MOBILE_UM77_LPC, 1, 0 }, 244 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_NM70_LPC, 1, 0 }, 245 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Q75_LPC, 1, 0 }, 246 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Q77_LPC, 1, 0 }, 247 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Z75_LPC, 1, 0 }, 248 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Z77_LPC, 1, 0 }, 249 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Z87_LPC, 1, 0 }, 250 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Z85_LPC, 1, 0 }, 251 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_HM86_LPC, 1, 0 }, 252 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_H87_LPC, 1, 0 }, 253 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_HM87_LPC, 1, 0 }, 254 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Q85_LPC, 1, 0 }, 255 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Q87_LPC, 1, 0 }, 256 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_QM87_LPC, 1, 0 }, 257 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_B85_LPC, 1, 0 }, 258 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_H97_LPC, 1, 0 }, 259 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Z97_LPC, 1, 0 }, 260 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_X99_LPC, 1, 0 }, 261 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_X99_LPC_2, 1, 0 }, 262 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE5G_M_LPC_4, 1, 0 }, 263 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE5G_M_LPC_7, 1, 0 }, 264 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C222_LPC, 1, 0 }, 265 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C224_LPC, 1, 0 }, 266 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C226_LPC, 1, 0 }, 267 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_H81_LPC, 1, 0 }, 268 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C600_LPC, 1, 0 }, 269 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_DH89XXCC_LPC, 1, 0 }, 270 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_DH89XXCL_LPC, 1, 0 }, 271 #if 0 272 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C2000_PCU_1, 1, 0 }, 273 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C2000_PCU_2, 1, 0 }, 274 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C2000_PCU_3, 1, 0 }, 275 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C2000_PCU_4, 1, 0 }, 276 #endif 277 278 { 0, 0, 0, 0 }, 279 }; 280 281 /* 282 * Allow user to enable GPIO functionality if they really need it. The 283 * vast majority of systems with an ICH should not expose GPIO to the 284 * kernel or user. In at least one instance the gpio_resume() handler 285 * on ICH GPIO was found to sabotage S3 suspend/resume. 286 */ 287 int ichlpcib_gpio_disable = 1; 288 289 /* 290 * Autoconf callbacks. 291 */ 292 static int 293 lpcibmatch(device_t parent, cfdata_t match, void *aux) 294 { 295 struct pci_attach_args *pa = aux; 296 const struct lpcib_device *lpcib_dev; 297 298 /* We are ISA bridge, of course */ 299 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_BRIDGE || 300 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_BRIDGE_ISA) 301 return 0; 302 303 for (lpcib_dev = lpcib_devices; lpcib_dev->vendor; ++lpcib_dev) { 304 if (PCI_VENDOR(pa->pa_id) == lpcib_dev->vendor && 305 PCI_PRODUCT(pa->pa_id) == lpcib_dev->product) 306 return 10; 307 } 308 309 return 0; 310 } 311 312 static void 313 lpcibattach(device_t parent, device_t self, void *aux) 314 { 315 struct pci_attach_args *pa = aux; 316 struct lpcib_softc *sc = device_private(self); 317 const struct lpcib_device *lpcib_dev; 318 pcireg_t pmbase; 319 320 sc->sc_pa = *pa; 321 322 for (lpcib_dev = lpcib_devices; lpcib_dev->vendor; ++lpcib_dev) { 323 if (PCI_VENDOR(pa->pa_id) != lpcib_dev->vendor || 324 PCI_PRODUCT(pa->pa_id) != lpcib_dev->product) 325 continue; 326 sc->sc_has_rcba = lpcib_dev->has_rcba; 327 sc->sc_has_ich5_hpet = lpcib_dev->has_ich5_hpet; 328 break; 329 } 330 331 pcibattach(parent, self, aux); 332 333 /* 334 * Part of our I/O registers are used as ACPI PM regs. 335 * Since our ACPI subsystem accesses the I/O space directly so far, 336 * we do not have to bother bus_space I/O map confliction. 337 * 338 * The PMBASE register is alike PCI BAR but not completely compatible 339 * with it. The PMBASE define the base address and the type but 340 * not describe the size. The value of the register may be lower 341 * than LPCIB_PCI_PM_SIZE. It makes impossible to use 342 * pci_mapreg_submap() because the function does range check. 343 */ 344 sc->sc_pmt = pa->pa_iot; 345 pmbase = pci_conf_read(pa->pa_pc, pa->pa_tag, LPCIB_PCI_PMBASE); 346 if (bus_space_map(sc->sc_pmt, PCI_MAPREG_IO_ADDR(pmbase), 347 LPCIB_PCI_PM_SIZE, 0, &sc->sc_pmh) != 0) { 348 aprint_error_dev(self, 349 "can't map power management i/o space\n"); 350 return; 351 } 352 353 if (bus_space_subregion(sc->sc_pmt, sc->sc_pmh, PMC_TCO_BASE, 354 TCO_REGSIZE, &sc->sc_tcoh)) { 355 aprint_error_dev(self, "can't map TCO space\n"); 356 } else { 357 sc->sc_tcot = sc->sc_pmt; 358 } 359 360 sc->sc_pmcon_orig = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 361 LPCIB_PCI_GEN_PMCON_1); 362 363 /* For ICH6 and later, always enable RCBA */ 364 if (sc->sc_has_rcba) { 365 pcireg_t rcba; 366 367 sc->sc_rcbat = sc->sc_pa.pa_memt; 368 369 rcba = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 370 LPCIB_RCBA); 371 if ((rcba & LPCIB_RCBA_EN) == 0) { 372 aprint_error_dev(self, "RCBA is not enabled\n"); 373 return; 374 } 375 rcba &= ~LPCIB_RCBA_EN; 376 377 if (bus_space_map(sc->sc_rcbat, rcba, LPCIB_RCBA_SIZE, 0, 378 &sc->sc_rcbah)) { 379 aprint_error_dev(self, "RCBA could not be mapped\n"); 380 return; 381 } 382 } 383 384 /* Set up the power management timer. */ 385 pmtimer_configure(self); 386 387 /* Set up the TCO (watchdog). */ 388 tcotimer_configure(self); 389 390 /* Set up SpeedStep. */ 391 speedstep_configure(self); 392 393 /* Set up HPET. */ 394 lpcib_hpet_configure(self); 395 396 #if NGPIO > 0 397 /* Set up GPIO */ 398 lpcib_gpio_configure(self); 399 #endif 400 401 #if NFWHRNG > 0 402 lpcib_fwh_configure(self); 403 #endif 404 405 /* Install power handler */ 406 if (!pmf_device_register1(self, lpcib_suspend, lpcib_resume, 407 lpcib_shutdown)) 408 aprint_error_dev(self, "couldn't establish power handler\n"); 409 } 410 411 static void 412 lpcibchilddet(device_t self, device_t child) 413 { 414 struct lpcib_softc *sc = device_private(self); 415 uint32_t val; 416 417 #if NFWHRNG > 0 418 if (sc->sc_fwhbus == child) { 419 sc->sc_fwhbus = NULL; 420 return; 421 } 422 #endif 423 #if NGPIO > 0 424 if (sc->sc_gpiobus == child) { 425 sc->sc_gpiobus = NULL; 426 return; 427 } 428 #endif 429 if (sc->sc_tco == child) { 430 sc->sc_tco = NULL; 431 return; 432 } 433 434 if (sc->sc_hpetbus != child) { 435 pcibchilddet(self, child); 436 return; 437 } 438 sc->sc_hpetbus = NULL; 439 if (sc->sc_has_ich5_hpet) { 440 val = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 441 LPCIB_PCI_GEN_CNTL); 442 switch (val & LPCIB_ICH5_HPTC_WIN_MASK) { 443 case LPCIB_ICH5_HPTC_0000: 444 case LPCIB_ICH5_HPTC_1000: 445 case LPCIB_ICH5_HPTC_2000: 446 case LPCIB_ICH5_HPTC_3000: 447 break; 448 default: 449 return; 450 } 451 val &= ~LPCIB_ICH5_HPTC_EN; 452 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 453 LPCIB_PCI_GEN_CNTL, val); 454 } else if (sc->sc_has_rcba) { 455 val = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 456 LPCIB_RCBA_HPTC); 457 switch (val & LPCIB_RCBA_HPTC_WIN_MASK) { 458 case LPCIB_RCBA_HPTC_0000: 459 case LPCIB_RCBA_HPTC_1000: 460 case LPCIB_RCBA_HPTC_2000: 461 case LPCIB_RCBA_HPTC_3000: 462 break; 463 default: 464 return; 465 } 466 val &= ~LPCIB_RCBA_HPTC_EN; 467 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, LPCIB_RCBA_HPTC, 468 val); 469 } 470 } 471 472 static int 473 lpcibrescan(device_t self, const char *ifattr, const int *locators) 474 { 475 struct lpcib_softc *sc = device_private(self); 476 477 if (ifattr_match(ifattr, "tcoichbus") && sc->sc_tco == NULL) 478 tcotimer_configure(self); 479 480 #if NFWHRNG > 0 481 if (ifattr_match(ifattr, "fwhichbus") && sc->sc_fwhbus == NULL) 482 lpcib_fwh_configure(self); 483 #endif 484 485 if (ifattr_match(ifattr, "hpetichbus") && sc->sc_hpetbus == NULL) 486 lpcib_hpet_configure(self); 487 488 #if NGPIO > 0 489 if (ifattr_match(ifattr, "gpiobus") && sc->sc_gpiobus == NULL) 490 lpcib_gpio_configure(self); 491 #endif 492 493 return pcibrescan(self, ifattr, locators); 494 } 495 496 static int 497 lpcibdetach(device_t self, int flags) 498 { 499 struct lpcib_softc *sc = device_private(self); 500 int error; 501 502 error = config_detach_children(self, flags); 503 if (error) 504 return error; 505 506 pmf_device_deregister(self); 507 508 #if NGPIO > 0 509 lpcib_gpio_unconfigure(self); 510 #endif 511 512 /* Set up SpeedStep. */ 513 speedstep_unconfigure(self); 514 515 pmtimer_unconfigure(self, flags); 516 517 if (sc->sc_has_rcba) 518 bus_space_unmap(sc->sc_rcbat, sc->sc_rcbah, LPCIB_RCBA_SIZE); 519 520 bus_space_unmap(sc->sc_pmt, sc->sc_pmh, sc->sc_iosize); 521 522 error = pcibdetach(self, flags); 523 KASSERTMSG(error == 0, "error=%d", error); 524 525 return 0; 526 } 527 528 static bool 529 lpcib_shutdown(device_t dv, int howto) 530 { 531 struct lpcib_softc *sc = device_private(dv); 532 533 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 534 LPCIB_PCI_GEN_PMCON_1, sc->sc_pmcon_orig); 535 536 return true; 537 } 538 539 static bool 540 lpcib_suspend(device_t dv, const pmf_qual_t *qual) 541 { 542 struct lpcib_softc *sc = device_private(dv); 543 pci_chipset_tag_t pc = sc->sc_pcib.sc_pc; 544 pcitag_t tag = sc->sc_pcib.sc_tag; 545 546 /* capture PIRQ routing control registers */ 547 sc->sc_pirq[0] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQA_ROUT); 548 sc->sc_pirq[1] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQE_ROUT); 549 550 sc->sc_pmcon = pci_conf_read(pc, tag, LPCIB_PCI_GEN_PMCON_1); 551 sc->sc_fwhsel2 = pci_conf_read(pc, tag, LPCIB_PCI_GEN_STA); 552 553 if (sc->sc_has_rcba) { 554 sc->sc_rcba_reg = pci_conf_read(pc, tag, LPCIB_RCBA); 555 sc->sc_hpet_reg = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 556 LPCIB_RCBA_HPTC); 557 } else if (sc->sc_has_ich5_hpet) { 558 sc->sc_hpet_reg = pci_conf_read(pc, tag, LPCIB_PCI_GEN_CNTL); 559 } 560 561 return true; 562 } 563 564 static bool 565 lpcib_resume(device_t dv, const pmf_qual_t *qual) 566 { 567 struct lpcib_softc *sc = device_private(dv); 568 pci_chipset_tag_t pc = sc->sc_pcib.sc_pc; 569 pcitag_t tag = sc->sc_pcib.sc_tag; 570 571 /* restore PIRQ routing control registers */ 572 pci_conf_write(pc, tag, LPCIB_PCI_PIRQA_ROUT, sc->sc_pirq[0]); 573 pci_conf_write(pc, tag, LPCIB_PCI_PIRQE_ROUT, sc->sc_pirq[1]); 574 575 pci_conf_write(pc, tag, LPCIB_PCI_GEN_PMCON_1, sc->sc_pmcon); 576 pci_conf_write(pc, tag, LPCIB_PCI_GEN_STA, sc->sc_fwhsel2); 577 578 if (sc->sc_has_rcba) { 579 pci_conf_write(pc, tag, LPCIB_RCBA, sc->sc_rcba_reg); 580 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, LPCIB_RCBA_HPTC, 581 sc->sc_hpet_reg); 582 } else if (sc->sc_has_ich5_hpet) { 583 pci_conf_write(pc, tag, LPCIB_PCI_GEN_CNTL, sc->sc_hpet_reg); 584 } 585 586 return true; 587 } 588 589 /* 590 * Initialize the power management timer. 591 */ 592 static void 593 pmtimer_configure(device_t self) 594 { 595 struct lpcib_softc *sc = device_private(self); 596 pcireg_t control; 597 598 /* 599 * Check if power management I/O space is enabled and enable the ACPI_EN 600 * bit if it's disabled. 601 */ 602 control = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 603 LPCIB_PCI_ACPI_CNTL); 604 sc->sc_acpi_cntl = control; 605 if ((control & LPCIB_PCI_ACPI_CNTL_EN) == 0) { 606 control |= LPCIB_PCI_ACPI_CNTL_EN; 607 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 608 LPCIB_PCI_ACPI_CNTL, control); 609 } 610 611 /* Attach our PM timer with the generic acpipmtimer function */ 612 sc->sc_pmtimer = acpipmtimer_attach(self, sc->sc_pmt, sc->sc_pmh, 613 PMC_PM1_TMR, 0); 614 } 615 616 static void 617 pmtimer_unconfigure(device_t self, int flags) 618 { 619 struct lpcib_softc *sc = device_private(self); 620 int error __diagused; 621 622 if (sc->sc_pmtimer != NULL) { 623 error = acpipmtimer_detach(sc->sc_pmtimer, flags); 624 KASSERTMSG(error == 0, "error=%d", error); 625 } 626 627 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 628 LPCIB_PCI_ACPI_CNTL, sc->sc_acpi_cntl); 629 } 630 631 /* 632 * Configure the watchdog timer. 633 */ 634 static void 635 tcotimer_configure(device_t self) 636 { 637 struct lpcib_softc *sc = device_private(self); 638 struct tco_attach_args arg; 639 640 if (sc->sc_has_rcba) 641 arg.ta_version = TCO_VERSION_RCBA; 642 else 643 arg.ta_version = TCO_VERSION_PCIB; 644 arg.ta_pmt = sc->sc_pmt; 645 arg.ta_pmh = sc->sc_pmh; 646 arg.ta_rcbat = sc->sc_rcbat; 647 arg.ta_rcbah = sc->sc_rcbah; 648 arg.ta_pcib = &sc->sc_pcib; 649 arg.ta_tcot = sc->sc_tcot; 650 arg.ta_tcoh = sc->sc_tcoh; 651 652 sc->sc_tco = config_found(self, &arg, NULL, 653 CFARGS(.iattr = "tcoichbus")); 654 } 655 656 657 /* 658 * Intel ICH SpeedStep support. 659 */ 660 #define SS_READ(sc, reg) \ 661 bus_space_read_1((sc)->sc_pmt, (sc)->sc_pmh, (reg)) 662 #define SS_WRITE(sc, reg, val) \ 663 bus_space_write_1((sc)->sc_pmt, (sc)->sc_pmh, (reg), (val)) 664 665 /* 666 * Linux driver says that SpeedStep on older chipsets cause 667 * lockups on Dell Inspiron 8000 and 8100. 668 * It should also not be enabled on systems with the 82855GM 669 * Hub, which typically have an EST-enabled CPU. 670 */ 671 static int 672 speedstep_bad_hb_check(const struct pci_attach_args *pa) 673 { 674 675 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82815_FULL_HUB && 676 PCI_REVISION(pa->pa_class) < 5) 677 return 1; 678 679 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82855GM_MCH) 680 return 1; 681 682 return 0; 683 } 684 685 static void 686 speedstep_configure(device_t self) 687 { 688 struct lpcib_softc *sc = device_private(self); 689 const struct sysctlnode *node, *ssnode; 690 int rv; 691 692 /* Supported on ICH2-M, ICH3-M and ICH4-M. */ 693 if (PCI_PRODUCT(sc->sc_pa.pa_id) == PCI_PRODUCT_INTEL_82801DBM_LPC || 694 PCI_PRODUCT(sc->sc_pa.pa_id) == PCI_PRODUCT_INTEL_82801CAM_LPC || 695 (PCI_PRODUCT(sc->sc_pa.pa_id) == PCI_PRODUCT_INTEL_82801BAM_LPC && 696 pci_find_device(&sc->sc_pa, speedstep_bad_hb_check) == 0)) { 697 pcireg_t pmcon; 698 699 /* Enable SpeedStep if it isn't already enabled. */ 700 pmcon = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 701 LPCIB_PCI_GEN_PMCON_1); 702 if ((pmcon & LPCIB_PCI_GEN_PMCON_1_SS_EN) == 0) 703 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 704 LPCIB_PCI_GEN_PMCON_1, 705 pmcon | LPCIB_PCI_GEN_PMCON_1_SS_EN); 706 707 /* Put in machdep.speedstep_state (0 for low, 1 for high). */ 708 if ((rv = sysctl_createv(&sc->sc_log, 0, NULL, &node, 709 CTLFLAG_PERMANENT, CTLTYPE_NODE, "machdep", NULL, 710 NULL, 0, NULL, 0, CTL_MACHDEP, CTL_EOL)) != 0) 711 goto err; 712 713 /* CTLFLAG_ANYWRITE? kernel option like EST? */ 714 if ((rv = sysctl_createv(&sc->sc_log, 0, &node, &ssnode, 715 CTLFLAG_READWRITE, CTLTYPE_INT, "speedstep_state", NULL, 716 speedstep_sysctl_helper, 0, NULL, 0, CTL_CREATE, 717 CTL_EOL)) != 0) 718 goto err; 719 720 /* XXX save the sc for IO tag/handle */ 721 speedstep_cookie = sc; 722 aprint_verbose_dev(self, "SpeedStep enabled\n"); 723 } 724 725 return; 726 727 err: 728 aprint_normal("%s: sysctl_createv failed (rv = %d)\n", __func__, rv); 729 } 730 731 static void 732 speedstep_unconfigure(device_t self) 733 { 734 struct lpcib_softc *sc = device_private(self); 735 736 sysctl_teardown(&sc->sc_log); 737 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 738 LPCIB_PCI_GEN_PMCON_1, sc->sc_pmcon_orig); 739 740 speedstep_cookie = NULL; 741 } 742 743 /* 744 * get/set the SpeedStep state: 0 == low power, 1 == high power. 745 */ 746 static int 747 speedstep_sysctl_helper(SYSCTLFN_ARGS) 748 { 749 struct sysctlnode node; 750 struct lpcib_softc *sc = speedstep_cookie; 751 uint8_t state, state2; 752 int ostate, nstate, s, error = 0; 753 754 /* 755 * We do the dance with spl's to avoid being at high ipl during 756 * sysctl_lookup() which can both copyin and copyout. 757 */ 758 s = splserial(); 759 state = SS_READ(sc, PMC_PM_SS_CNTL); 760 splx(s); 761 if ((state & PMC_PM_SS_STATE_LOW) == 0) 762 ostate = 1; 763 else 764 ostate = 0; 765 nstate = ostate; 766 767 node = *rnode; 768 node.sysctl_data = &nstate; 769 770 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 771 if (error || newp == NULL) 772 goto out; 773 774 /* Only two states are available */ 775 if (nstate != 0 && nstate != 1) { 776 error = EINVAL; 777 goto out; 778 } 779 780 s = splserial(); 781 state2 = SS_READ(sc, PMC_PM_SS_CNTL); 782 if ((state2 & PMC_PM_SS_STATE_LOW) == 0) 783 ostate = 1; 784 else 785 ostate = 0; 786 787 if (ostate != nstate) { 788 uint8_t cntl; 789 790 if (nstate == 0) 791 state2 |= PMC_PM_SS_STATE_LOW; 792 else 793 state2 &= ~PMC_PM_SS_STATE_LOW; 794 795 /* 796 * Must disable bus master arbitration during the change. 797 */ 798 cntl = SS_READ(sc, PMC_PM_CTRL); 799 SS_WRITE(sc, PMC_PM_CTRL, cntl | PMC_PM_SS_CNTL_ARB_DIS); 800 SS_WRITE(sc, PMC_PM_SS_CNTL, state2); 801 SS_WRITE(sc, PMC_PM_CTRL, cntl); 802 } 803 splx(s); 804 out: 805 return error; 806 } 807 808 static void 809 lpcib_hpet_configure(device_t self) 810 { 811 struct lpcib_softc *sc = device_private(self); 812 struct lpcib_hpet_attach_args arg; 813 uint32_t hpet_reg, val; 814 815 if (sc->sc_has_ich5_hpet) { 816 val = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 817 LPCIB_PCI_GEN_CNTL); 818 switch (val & LPCIB_ICH5_HPTC_WIN_MASK) { 819 case LPCIB_ICH5_HPTC_0000: 820 hpet_reg = LPCIB_ICH5_HPTC_0000_BASE; 821 break; 822 case LPCIB_ICH5_HPTC_1000: 823 hpet_reg = LPCIB_ICH5_HPTC_1000_BASE; 824 break; 825 case LPCIB_ICH5_HPTC_2000: 826 hpet_reg = LPCIB_ICH5_HPTC_2000_BASE; 827 break; 828 case LPCIB_ICH5_HPTC_3000: 829 hpet_reg = LPCIB_ICH5_HPTC_3000_BASE; 830 break; 831 default: 832 return; 833 } 834 val |= sc->sc_hpet_reg | LPCIB_ICH5_HPTC_EN; 835 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 836 LPCIB_PCI_GEN_CNTL, val); 837 } else if (sc->sc_has_rcba) { 838 val = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 839 LPCIB_RCBA_HPTC); 840 switch (val & LPCIB_RCBA_HPTC_WIN_MASK) { 841 case LPCIB_RCBA_HPTC_0000: 842 hpet_reg = LPCIB_RCBA_HPTC_0000_BASE; 843 break; 844 case LPCIB_RCBA_HPTC_1000: 845 hpet_reg = LPCIB_RCBA_HPTC_1000_BASE; 846 break; 847 case LPCIB_RCBA_HPTC_2000: 848 hpet_reg = LPCIB_RCBA_HPTC_2000_BASE; 849 break; 850 case LPCIB_RCBA_HPTC_3000: 851 hpet_reg = LPCIB_RCBA_HPTC_3000_BASE; 852 break; 853 default: 854 return; 855 } 856 val |= LPCIB_RCBA_HPTC_EN; 857 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, LPCIB_RCBA_HPTC, 858 val); 859 } else { 860 /* No HPET here */ 861 return; 862 } 863 864 arg.hpet_mem_t = sc->sc_pa.pa_memt; 865 arg.hpet_reg = hpet_reg; 866 867 sc->sc_hpetbus = config_found(self, &arg, NULL, 868 CFARGS(.iattr = "hpetichbus")); 869 } 870 871 #if NGPIO > 0 872 static void 873 lpcib_gpio_configure(device_t self) 874 { 875 struct lpcib_softc *sc = device_private(self); 876 struct gpiobus_attach_args gba; 877 pcireg_t gpio_cntl; 878 uint32_t use, io, bit; 879 int pin, shift, base_reg, cntl_reg, reg; 880 int rv; 881 882 if (ichlpcib_gpio_disable != 0) 883 return; 884 885 /* this implies ICH >= 6, and thus different mapreg */ 886 if (sc->sc_has_rcba) { 887 base_reg = LPCIB_PCI_GPIO_BASE_ICH6; 888 cntl_reg = LPCIB_PCI_GPIO_CNTL_ICH6; 889 } else { 890 base_reg = LPCIB_PCI_GPIO_BASE; 891 cntl_reg = LPCIB_PCI_GPIO_CNTL; 892 } 893 894 gpio_cntl = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 895 cntl_reg); 896 897 /* Is GPIO enabled? */ 898 if ((gpio_cntl & LPCIB_PCI_GPIO_CNTL_EN) == 0) 899 return; 900 /* 901 * The GPIO_BASE register is alike PCI BAR but not completely 902 * compatible with it. The PMBASE define the base address and the type 903 * but not describe the size. The value of the register may be lower 904 * than LPCIB_PCI_GPIO_SIZE. It makes impossible to use 905 * pci_mapreg_submap() because the function does range check. 906 */ 907 sc->sc_gpio_iot = sc->sc_pa.pa_iot; 908 reg = pci_conf_read(sc->sc_pa.pa_pc, sc->sc_pa.pa_tag, base_reg); 909 rv = bus_space_map(sc->sc_gpio_iot, PCI_MAPREG_IO_ADDR(reg), 910 LPCIB_PCI_GPIO_SIZE, 0, &sc->sc_gpio_ioh); 911 if (rv != 0) { 912 aprint_error_dev(self, "can't map general purpose i/o space(rv = %d)\n", rv); 913 return; 914 } 915 916 mutex_init(&sc->sc_gpio_mtx, MUTEX_DEFAULT, IPL_NONE); 917 918 for (pin = 0; pin < LPCIB_GPIO_NPINS; pin++) { 919 sc->sc_gpio_pins[pin].pin_num = pin; 920 921 /* Read initial state */ 922 reg = (pin < 32) ? LPCIB_GPIO_GPIO_USE_SEL : LPCIB_GPIO_GPIO_USE_SEL2; 923 use = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 924 reg = (pin < 32) ? LPCIB_GPIO_GP_IO_SEL : LPCIB_GPIO_GP_IO_SEL; 925 io = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, 4); 926 shift = pin % 32; 927 bit = __BIT(shift); 928 929 if ((use & bit) != 0) { 930 sc->sc_gpio_pins[pin].pin_caps = 931 GPIO_PIN_INPUT | GPIO_PIN_OUTPUT; 932 if (pin < 32) 933 sc->sc_gpio_pins[pin].pin_caps |= 934 GPIO_PIN_PULSATE; 935 if ((io & bit) != 0) 936 sc->sc_gpio_pins[pin].pin_flags = 937 GPIO_PIN_INPUT; 938 else 939 sc->sc_gpio_pins[pin].pin_flags = 940 GPIO_PIN_OUTPUT; 941 } else 942 sc->sc_gpio_pins[pin].pin_caps = 0; 943 944 if (lpcib_gpio_pin_read(sc, pin) == 0) 945 sc->sc_gpio_pins[pin].pin_state = GPIO_PIN_LOW; 946 else 947 sc->sc_gpio_pins[pin].pin_state = GPIO_PIN_HIGH; 948 949 } 950 951 /* Create controller tag */ 952 sc->sc_gpio_gc.gp_cookie = sc; 953 sc->sc_gpio_gc.gp_pin_read = lpcib_gpio_pin_read; 954 sc->sc_gpio_gc.gp_pin_write = lpcib_gpio_pin_write; 955 sc->sc_gpio_gc.gp_pin_ctl = lpcib_gpio_pin_ctl; 956 957 memset(&gba, 0, sizeof(gba)); 958 959 gba.gba_gc = &sc->sc_gpio_gc; 960 gba.gba_pins = sc->sc_gpio_pins; 961 gba.gba_npins = LPCIB_GPIO_NPINS; 962 963 sc->sc_gpiobus = config_found(self, &gba, gpiobus_print, 964 CFARGS(.iattr = "gpiobus")); 965 } 966 967 static void 968 lpcib_gpio_unconfigure(device_t self) 969 { 970 struct lpcib_softc *sc = device_private(self); 971 972 mutex_destroy(&sc->sc_gpio_mtx); 973 974 bus_space_unmap(sc->sc_gpio_iot, sc->sc_gpio_ioh, sc->sc_gpio_ios); 975 } 976 977 static int 978 lpcib_gpio_pin_read(void *arg, int pin) 979 { 980 struct lpcib_softc *sc = arg; 981 uint32_t data; 982 int reg, shift; 983 984 reg = (pin < 32) ? LPCIB_GPIO_GP_LVL : LPCIB_GPIO_GP_LVL2; 985 shift = pin % 32; 986 987 mutex_enter(&sc->sc_gpio_mtx); 988 data = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 989 mutex_exit(&sc->sc_gpio_mtx); 990 991 return (__SHIFTOUT(data, __BIT(shift)) ? GPIO_PIN_HIGH : GPIO_PIN_LOW); 992 } 993 994 static void 995 lpcib_gpio_pin_write(void *arg, int pin, int value) 996 { 997 struct lpcib_softc *sc = arg; 998 uint32_t data; 999 int reg, shift; 1000 1001 reg = (pin < 32) ? LPCIB_GPIO_GP_LVL : LPCIB_GPIO_GP_LVL2; 1002 shift = pin % 32; 1003 1004 mutex_enter(&sc->sc_gpio_mtx); 1005 1006 data = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 1007 1008 if (value) 1009 data |= __BIT(shift); 1010 else 1011 data &= ~__BIT(shift); 1012 1013 bus_space_write_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg, data); 1014 1015 mutex_exit(&sc->sc_gpio_mtx); 1016 } 1017 1018 static void 1019 lpcib_gpio_pin_ctl(void *arg, int pin, int flags) 1020 { 1021 struct lpcib_softc *sc = arg; 1022 uint32_t data; 1023 int reg, shift; 1024 1025 shift = pin % 32; 1026 reg = (pin < 32) ? LPCIB_GPIO_GP_IO_SEL : LPCIB_GPIO_GP_IO_SEL2; 1027 1028 mutex_enter(&sc->sc_gpio_mtx); 1029 1030 data = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 1031 1032 if (flags & GPIO_PIN_OUTPUT) 1033 data &= ~__BIT(shift); 1034 1035 if (flags & GPIO_PIN_INPUT) 1036 data |= __BIT(shift); 1037 1038 bus_space_write_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg, data); 1039 1040 1041 if (pin < 32) { 1042 reg = LPCIB_GPIO_GPO_BLINK; 1043 data = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 1044 1045 if (flags & GPIO_PIN_PULSATE) 1046 data |= __BIT(shift); 1047 else 1048 data &= ~__BIT(shift); 1049 1050 bus_space_write_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg, data); 1051 } 1052 1053 mutex_exit(&sc->sc_gpio_mtx); 1054 } 1055 #endif 1056 1057 #if NFWHRNG > 0 1058 static void 1059 lpcib_fwh_configure(device_t self) 1060 { 1061 struct lpcib_softc *sc; 1062 pcireg_t pr; 1063 1064 sc = device_private(self); 1065 1066 if (sc->sc_has_rcba) { 1067 /* 1068 * Very unlikely to find a 82802 on a ICH6 or newer. 1069 * Also the write enable register moved at that point. 1070 */ 1071 return; 1072 } else { 1073 /* Enable FWH write to identify FWH. */ 1074 pr = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 1075 LPCIB_PCI_BIOS_CNTL); 1076 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 1077 LPCIB_PCI_BIOS_CNTL, pr|LPCIB_PCI_BIOS_CNTL_BWE); 1078 } 1079 1080 sc->sc_fwhbus = config_found(self, NULL, NULL, 1081 CFARGS(.iattr = "fwhichbus")); 1082 1083 /* restore previous write enable setting */ 1084 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 1085 LPCIB_PCI_BIOS_CNTL, pr); 1086 } 1087 #endif 1088