1 /* $NetBSD: ichlpcib.c,v 1.12 2008/07/20 17:18:21 martin Exp $ */ 2 3 /*- 4 * Copyright (c) 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Minoura Makoto and Matthew R. Green. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Intel I/O Controller Hub (ICHn) LPC Interface Bridge driver 34 * 35 * LPC Interface Bridge is basically a pcib (PCI-ISA Bridge), but has 36 * some power management and monitoring functions. 37 * Currently we support the watchdog timer, SpeedStep (on some systems) 38 * and the power management timer. 39 */ 40 41 #include <sys/cdefs.h> 42 __KERNEL_RCSID(0, "$NetBSD: ichlpcib.c,v 1.12 2008/07/20 17:18:21 martin Exp $"); 43 44 #include <sys/types.h> 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/device.h> 48 #include <sys/sysctl.h> 49 #include <sys/timetc.h> 50 #include <machine/bus.h> 51 52 #include <dev/pci/pcivar.h> 53 #include <dev/pci/pcireg.h> 54 #include <dev/pci/pcidevs.h> 55 56 #include <dev/sysmon/sysmonvar.h> 57 58 #include <dev/ic/acpipmtimer.h> 59 #include <dev/ic/i82801lpcreg.h> 60 #include <dev/ic/hpetreg.h> 61 #include <dev/ic/hpetvar.h> 62 63 #include "hpet.h" 64 #include "pcibvar.h" 65 66 struct lpcib_softc { 67 /* we call pcibattach() which assumes this starts like this: */ 68 struct pcib_softc sc_pcib; 69 70 struct pci_attach_args sc_pa; 71 int sc_has_rcba; 72 int sc_has_ich5_hpet; 73 74 /* RCBA */ 75 bus_space_tag_t sc_rcbat; 76 bus_space_handle_t sc_rcbah; 77 pcireg_t sc_rcba_reg; 78 79 /* Watchdog variables. */ 80 struct sysmon_wdog sc_smw; 81 bus_space_tag_t sc_iot; 82 bus_space_handle_t sc_ioh; 83 84 #if NHPET > 0 85 /* HPET variables. */ 86 uint32_t sc_hpet_reg; 87 #endif 88 89 /* Power management */ 90 pcireg_t sc_pirq[2]; 91 pcireg_t sc_pmcon; 92 pcireg_t sc_fwhsel2; 93 }; 94 95 static int lpcibmatch(device_t, cfdata_t, void *); 96 static void lpcibattach(device_t, device_t, void *); 97 static bool lpcib_suspend(device_t PMF_FN_PROTO); 98 static bool lpcib_resume(device_t PMF_FN_PROTO); 99 100 static void pmtimer_configure(device_t); 101 102 static void tcotimer_configure(device_t); 103 static int tcotimer_setmode(struct sysmon_wdog *); 104 static int tcotimer_tickle(struct sysmon_wdog *); 105 static void tcotimer_stop(struct lpcib_softc *); 106 static void tcotimer_start(struct lpcib_softc *); 107 static void tcotimer_status_reset(struct lpcib_softc *); 108 static int tcotimer_disable_noreboot(device_t); 109 110 static void speedstep_configure(device_t); 111 static int speedstep_sysctl_helper(SYSCTLFN_ARGS); 112 113 #if NHPET > 0 114 static void lpcib_hpet_configure(device_t); 115 #endif 116 117 struct lpcib_softc *speedstep_cookie; /* XXX */ 118 119 CFATTACH_DECL_NEW(ichlpcib, sizeof(struct lpcib_softc), 120 lpcibmatch, lpcibattach, NULL, NULL); 121 122 static struct lpcib_device { 123 pcireg_t vendor, product; 124 int has_rcba; 125 int has_ich5_hpet; 126 } lpcib_devices[] = { 127 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AA_LPC, 0, 0 }, 128 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BA_LPC, 0, 0 }, 129 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BAM_LPC, 0, 0 }, 130 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CA_LPC, 0, 0 }, 131 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CAM_LPC, 0, 0 }, 132 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DB_LPC, 0, 0 }, 133 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DB_ISA, 0, 0 }, 134 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801EB_LPC, 0, 1 }, 135 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801FB_LPC, 1, 0 }, 136 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801FBM_LPC, 1, 0 }, 137 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801G_LPC, 1, 0 }, 138 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GBM_LPC, 1, 0 }, 139 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GHM_LPC, 1, 0 }, 140 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_LPC, 1, 0 }, 141 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HEM_LPC, 1, 0 }, 142 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HH_LPC, 1, 0 }, 143 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HO_LPC, 1, 0 }, 144 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HBM_LPC, 1, 0 }, 145 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IH_LPC, 1, 0 }, 146 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IO_LPC, 1, 0 }, 147 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IR_LPC, 1, 0 }, 148 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IB_LPC, 1, 0 }, 149 { 0, 0, 0, 0 }, 150 }; 151 152 /* 153 * Autoconf callbacks. 154 */ 155 static int 156 lpcibmatch(device_t parent, cfdata_t match, void *aux) 157 { 158 struct pci_attach_args *pa = aux; 159 struct lpcib_device *lpcib_dev; 160 161 /* We are ISA bridge, of course */ 162 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_BRIDGE || 163 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_BRIDGE_ISA) 164 return 0; 165 166 for (lpcib_dev = lpcib_devices; lpcib_dev->vendor; ++lpcib_dev) { 167 if (PCI_VENDOR(pa->pa_id) == lpcib_dev->vendor && 168 PCI_PRODUCT(pa->pa_id) == lpcib_dev->product) 169 return 10; 170 } 171 172 return 0; 173 } 174 175 static void 176 lpcibattach(device_t parent, device_t self, void *aux) 177 { 178 struct pci_attach_args *pa = aux; 179 struct lpcib_softc *sc = device_private(self); 180 struct lpcib_device *lpcib_dev; 181 182 sc->sc_pa = *pa; 183 184 for (lpcib_dev = lpcib_devices; lpcib_dev->vendor; ++lpcib_dev) { 185 if (PCI_VENDOR(pa->pa_id) != lpcib_dev->vendor || 186 PCI_PRODUCT(pa->pa_id) != lpcib_dev->product) 187 continue; 188 sc->sc_has_rcba = lpcib_dev->has_rcba; 189 sc->sc_has_ich5_hpet = lpcib_dev->has_ich5_hpet; 190 break; 191 } 192 193 pcibattach(parent, self, aux); 194 195 /* 196 * Part of our I/O registers are used as ACPI PM regs. 197 * Since our ACPI subsystem accesses the I/O space directly so far, 198 * we do not have to bother bus_space I/O map confliction. 199 */ 200 if (pci_mapreg_map(pa, LPCIB_PCI_PMBASE, PCI_MAPREG_TYPE_IO, 0, 201 &sc->sc_iot, &sc->sc_ioh, NULL, NULL)) { 202 aprint_error_dev(self, "can't map power management i/o space"); 203 return; 204 } 205 206 /* For ICH6 and later, always enable RCBA */ 207 if (sc->sc_has_rcba) { 208 pcireg_t rcba; 209 210 sc->sc_rcbat = sc->sc_pa.pa_memt; 211 212 rcba = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 213 LPCIB_RCBA); 214 if ((rcba & LPCIB_RCBA_EN) == 0) { 215 aprint_error_dev(self, "RCBA is not enabled"); 216 return; 217 } 218 rcba &= ~LPCIB_RCBA_EN; 219 220 if (bus_space_map(sc->sc_rcbat, rcba, LPCIB_RCBA_SIZE, 0, 221 &sc->sc_rcbah)) { 222 aprint_error_dev(self, "RCBA could not be mapped"); 223 return; 224 } 225 } 226 227 /* Set up the power management timer. */ 228 pmtimer_configure(self); 229 230 /* Set up the TCO (watchdog). */ 231 tcotimer_configure(self); 232 233 /* Set up SpeedStep. */ 234 speedstep_configure(self); 235 236 #if NHPET > 0 237 /* Set up HPET. */ 238 lpcib_hpet_configure(self); 239 #endif 240 241 /* Install power handler */ 242 if (!pmf_device_register(self, lpcib_suspend, lpcib_resume)) 243 aprint_error_dev(self, "couldn't establish power handler\n"); 244 } 245 246 static bool 247 lpcib_suspend(device_t dv PMF_FN_ARGS) 248 { 249 struct lpcib_softc *sc = device_private(dv); 250 pci_chipset_tag_t pc = sc->sc_pcib.sc_pc; 251 pcitag_t tag = sc->sc_pcib.sc_tag; 252 253 /* capture PIRQ routing control registers */ 254 sc->sc_pirq[0] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQA_ROUT); 255 sc->sc_pirq[1] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQE_ROUT); 256 257 sc->sc_pmcon = pci_conf_read(pc, tag, LPCIB_PCI_GEN_PMCON_1); 258 sc->sc_fwhsel2 = pci_conf_read(pc, tag, LPCIB_PCI_GEN_STA); 259 260 if (sc->sc_has_rcba) { 261 sc->sc_rcba_reg = pci_conf_read(pc, tag, LPCIB_RCBA); 262 #if NHPET > 0 263 sc->sc_hpet_reg = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 264 LPCIB_RCBA_HPTC); 265 #endif 266 } else if (sc->sc_has_ich5_hpet) { 267 #if NHPET > 0 268 sc->sc_hpet_reg = pci_conf_read(pc, tag, LPCIB_PCI_GEN_CNTL); 269 #endif 270 } 271 272 return true; 273 } 274 275 static bool 276 lpcib_resume(device_t dv PMF_FN_ARGS) 277 { 278 struct lpcib_softc *sc = device_private(dv); 279 pci_chipset_tag_t pc = sc->sc_pcib.sc_pc; 280 pcitag_t tag = sc->sc_pcib.sc_tag; 281 282 /* restore PIRQ routing control registers */ 283 pci_conf_write(pc, tag, LPCIB_PCI_PIRQA_ROUT, sc->sc_pirq[0]); 284 pci_conf_write(pc, tag, LPCIB_PCI_PIRQE_ROUT, sc->sc_pirq[1]); 285 286 pci_conf_write(pc, tag, LPCIB_PCI_GEN_PMCON_1, sc->sc_pmcon); 287 pci_conf_write(pc, tag, LPCIB_PCI_GEN_STA, sc->sc_fwhsel2); 288 289 if (sc->sc_has_rcba) { 290 pci_conf_write(pc, tag, LPCIB_RCBA, sc->sc_rcba_reg); 291 #if NHPET > 0 292 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, LPCIB_RCBA_HPTC, 293 sc->sc_hpet_reg); 294 #endif 295 } else if (sc->sc_has_ich5_hpet) { 296 #if NHPET > 0 297 pci_conf_write(pc, tag, LPCIB_PCI_GEN_CNTL, sc->sc_hpet_reg); 298 #endif 299 } 300 301 return true; 302 } 303 304 /* 305 * Initialize the power management timer. 306 */ 307 static void 308 pmtimer_configure(device_t self) 309 { 310 struct lpcib_softc *sc = device_private(self); 311 pcireg_t control; 312 313 /* 314 * Check if power management I/O space is enabled and enable the ACPI_EN 315 * bit if it's disabled. 316 */ 317 control = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 318 LPCIB_PCI_ACPI_CNTL); 319 if ((control & LPCIB_PCI_ACPI_CNTL_EN) == 0) { 320 control |= LPCIB_PCI_ACPI_CNTL_EN; 321 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 322 LPCIB_PCI_ACPI_CNTL, control); 323 } 324 325 /* Attach our PM timer with the generic acpipmtimer function */ 326 acpipmtimer_attach(self, sc->sc_iot, sc->sc_ioh, 327 LPCIB_PM1_TMR, 0); 328 } 329 330 /* 331 * Initialize the watchdog timer. 332 */ 333 static void 334 tcotimer_configure(device_t self) 335 { 336 struct lpcib_softc *sc = device_private(self); 337 uint32_t ioreg; 338 unsigned int period; 339 340 /* 341 * Clear the No Reboot (NR) bit. If this fails, enabling the TCO_EN bit 342 * in the SMI_EN register is the last chance. 343 */ 344 if (tcotimer_disable_noreboot(self)) { 345 ioreg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, LPCIB_SMI_EN); 346 ioreg |= LPCIB_SMI_EN_TCO_EN; 347 bus_space_write_4(sc->sc_iot, sc->sc_ioh, LPCIB_SMI_EN, ioreg); 348 } 349 350 /* Reset the watchdog status registers. */ 351 tcotimer_status_reset(sc); 352 353 /* Explicitly stop the TCO timer. */ 354 tcotimer_stop(sc); 355 356 /* 357 * Register the driver with the sysmon watchdog framework. 358 */ 359 sc->sc_smw.smw_name = device_xname(self); 360 sc->sc_smw.smw_cookie = sc; 361 sc->sc_smw.smw_setmode = tcotimer_setmode; 362 sc->sc_smw.smw_tickle = tcotimer_tickle; 363 if (sc->sc_has_rcba) 364 period = LPCIB_TCOTIMER2_MAX_TICK; 365 else 366 period = LPCIB_TCOTIMER_MAX_TICK; 367 sc->sc_smw.smw_period = lpcib_tcotimer_tick_to_second(period); 368 369 if (sysmon_wdog_register(&sc->sc_smw)) { 370 aprint_error_dev(self, "unable to register TCO timer" 371 "as a sysmon watchdog device.\n"); 372 return; 373 } 374 375 aprint_verbose_dev(self, "TCO (watchdog) timer configured.\n"); 376 } 377 378 /* 379 * Sysmon watchdog callbacks. 380 */ 381 static int 382 tcotimer_setmode(struct sysmon_wdog *smw) 383 { 384 struct lpcib_softc *sc = smw->smw_cookie; 385 unsigned int period; 386 uint16_t ich6period = 0; 387 388 if ((smw->smw_mode & WDOG_MODE_MASK) == WDOG_MODE_DISARMED) { 389 /* Stop the TCO timer. */ 390 tcotimer_stop(sc); 391 } else { 392 /* 393 * ICH6 or newer are limited to 2s min and 613s max. 394 * ICH5 or older are limited to 4s min and 39s max. 395 */ 396 if (sc->sc_has_rcba) { 397 if (smw->smw_period < LPCIB_TCOTIMER2_MIN_TICK || 398 smw->smw_period > LPCIB_TCOTIMER2_MAX_TICK) 399 return EINVAL; 400 } else { 401 if (smw->smw_period < LPCIB_TCOTIMER_MIN_TICK || 402 smw->smw_period > LPCIB_TCOTIMER_MAX_TICK) 403 return EINVAL; 404 } 405 period = lpcib_tcotimer_second_to_tick(smw->smw_period); 406 407 /* Stop the TCO timer, */ 408 tcotimer_stop(sc); 409 410 /* set the timeout, */ 411 if (sc->sc_has_rcba) { 412 /* ICH6 or newer */ 413 ich6period = bus_space_read_2(sc->sc_iot, sc->sc_ioh, 414 LPCIB_TCO_TMR2); 415 ich6period &= 0xfc00; 416 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 417 LPCIB_TCO_TMR2, ich6period | period); 418 } else { 419 /* ICH5 or older */ 420 period |= bus_space_read_1(sc->sc_iot, sc->sc_ioh, 421 LPCIB_TCO_TMR); 422 period &= 0xc0; 423 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 424 LPCIB_TCO_TMR, period); 425 } 426 427 /* and start/reload the timer. */ 428 tcotimer_start(sc); 429 tcotimer_tickle(smw); 430 } 431 432 return 0; 433 } 434 435 static int 436 tcotimer_tickle(struct sysmon_wdog *smw) 437 { 438 struct lpcib_softc *sc = smw->smw_cookie; 439 440 /* any value is allowed */ 441 if (sc->sc_has_rcba) 442 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO_RLD, 1); 443 else 444 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_TCO_RLD, 1); 445 446 return 0; 447 } 448 449 static void 450 tcotimer_stop(struct lpcib_softc *sc) 451 { 452 uint16_t ioreg; 453 454 ioreg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT); 455 ioreg |= LPCIB_TCO1_CNT_TCO_TMR_HLT; 456 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT, ioreg); 457 } 458 459 static void 460 tcotimer_start(struct lpcib_softc *sc) 461 { 462 uint16_t ioreg; 463 464 ioreg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT); 465 ioreg &= ~LPCIB_TCO1_CNT_TCO_TMR_HLT; 466 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT, ioreg); 467 } 468 469 static void 470 tcotimer_status_reset(struct lpcib_softc *sc) 471 { 472 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_STS, 473 LPCIB_TCO1_STS_TIMEOUT); 474 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO2_STS, 475 LPCIB_TCO2_STS_BOOT_STS); 476 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO2_STS, 477 LPCIB_TCO2_STS_SECONDS_TO_STS); 478 } 479 480 /* 481 * Clear the No Reboot (NR) bit, this enables reboots when the timer 482 * reaches the timeout for the second time. 483 */ 484 static int 485 tcotimer_disable_noreboot(device_t self) 486 { 487 struct lpcib_softc *sc = device_private(self); 488 489 if (sc->sc_has_rcba) { 490 uint32_t status; 491 492 status = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 493 LPCIB_GCS_OFFSET); 494 status &= ~LPCIB_GCS_NO_REBOOT; 495 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, 496 LPCIB_GCS_OFFSET, status); 497 status = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 498 LPCIB_GCS_OFFSET); 499 if (status & LPCIB_GCS_NO_REBOOT) 500 goto error; 501 } else { 502 pcireg_t pcireg; 503 504 pcireg = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 505 LPCIB_PCI_GEN_STA); 506 if (pcireg & LPCIB_PCI_GEN_STA_NO_REBOOT) { 507 /* TCO timeout reset is disabled; try to enable it */ 508 pcireg &= ~LPCIB_PCI_GEN_STA_NO_REBOOT; 509 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 510 LPCIB_PCI_GEN_STA, pcireg); 511 if (pcireg & LPCIB_PCI_GEN_STA_NO_REBOOT) 512 goto error; 513 } 514 } 515 516 return 0; 517 error: 518 aprint_error_dev(self, "TCO timer reboot disabled by hardware; " 519 "hope SMBIOS properly handles it.\n"); 520 return EINVAL; 521 } 522 523 524 /* 525 * Intel ICH SpeedStep support. 526 */ 527 #define SS_READ(sc, reg) \ 528 bus_space_read_1((sc)->sc_iot, (sc)->sc_ioh, (reg)) 529 #define SS_WRITE(sc, reg, val) \ 530 bus_space_write_1((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) 531 532 /* 533 * Linux driver says that SpeedStep on older chipsets cause 534 * lockups on Dell Inspiron 8000 and 8100. 535 */ 536 static int 537 speedstep_bad_hb_check(struct pci_attach_args *pa) 538 { 539 540 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82815_FULL_HUB && 541 PCI_REVISION(pa->pa_class) < 5) 542 return 1; 543 544 return 0; 545 } 546 547 static void 548 speedstep_configure(device_t self) 549 { 550 struct lpcib_softc *sc = device_private(self); 551 const struct sysctlnode *node, *ssnode; 552 int rv; 553 554 /* Supported on ICH2-M, ICH3-M and ICH4-M. */ 555 if (PCI_PRODUCT(sc->sc_pa.pa_id) == PCI_PRODUCT_INTEL_82801DB_ISA || 556 PCI_PRODUCT(sc->sc_pa.pa_id) == PCI_PRODUCT_INTEL_82801CAM_LPC || 557 (PCI_PRODUCT(sc->sc_pa.pa_id) == PCI_PRODUCT_INTEL_82801BAM_LPC && 558 pci_find_device(&sc->sc_pa, speedstep_bad_hb_check) == 0)) { 559 uint8_t pmcon; 560 561 /* Enable SpeedStep if it isn't already enabled. */ 562 pmcon = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 563 LPCIB_PCI_GEN_PMCON_1); 564 if ((pmcon & LPCIB_PCI_GEN_PMCON_1_SS_EN) == 0) 565 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 566 LPCIB_PCI_GEN_PMCON_1, 567 pmcon | LPCIB_PCI_GEN_PMCON_1_SS_EN); 568 569 /* Put in machdep.speedstep_state (0 for low, 1 for high). */ 570 if ((rv = sysctl_createv(NULL, 0, NULL, &node, 571 CTLFLAG_PERMANENT, CTLTYPE_NODE, "machdep", NULL, 572 NULL, 0, NULL, 0, CTL_MACHDEP, CTL_EOL)) != 0) 573 goto err; 574 575 /* CTLFLAG_ANYWRITE? kernel option like EST? */ 576 if ((rv = sysctl_createv(NULL, 0, &node, &ssnode, 577 CTLFLAG_READWRITE, CTLTYPE_INT, "speedstep_state", NULL, 578 speedstep_sysctl_helper, 0, NULL, 0, CTL_CREATE, 579 CTL_EOL)) != 0) 580 goto err; 581 582 /* XXX save the sc for IO tag/handle */ 583 speedstep_cookie = sc; 584 aprint_verbose_dev(self, "SpeedStep enabled\n"); 585 } 586 587 return; 588 589 err: 590 aprint_normal("%s: sysctl_createv failed (rv = %d)\n", __func__, rv); 591 } 592 593 /* 594 * get/set the SpeedStep state: 0 == low power, 1 == high power. 595 */ 596 static int 597 speedstep_sysctl_helper(SYSCTLFN_ARGS) 598 { 599 struct sysctlnode node; 600 struct lpcib_softc *sc = speedstep_cookie; 601 uint8_t state, state2; 602 int ostate, nstate, s, error = 0; 603 604 /* 605 * We do the dance with spl's to avoid being at high ipl during 606 * sysctl_lookup() which can both copyin and copyout. 607 */ 608 s = splserial(); 609 state = SS_READ(sc, LPCIB_PM_SS_CNTL); 610 splx(s); 611 if ((state & LPCIB_PM_SS_STATE_LOW) == 0) 612 ostate = 1; 613 else 614 ostate = 0; 615 nstate = ostate; 616 617 node = *rnode; 618 node.sysctl_data = &nstate; 619 620 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 621 if (error || newp == NULL) 622 goto out; 623 624 /* Only two states are available */ 625 if (nstate != 0 && nstate != 1) { 626 error = EINVAL; 627 goto out; 628 } 629 630 s = splserial(); 631 state2 = SS_READ(sc, LPCIB_PM_SS_CNTL); 632 if ((state2 & LPCIB_PM_SS_STATE_LOW) == 0) 633 ostate = 1; 634 else 635 ostate = 0; 636 637 if (ostate != nstate) { 638 uint8_t cntl; 639 640 if (nstate == 0) 641 state2 |= LPCIB_PM_SS_STATE_LOW; 642 else 643 state2 &= ~LPCIB_PM_SS_STATE_LOW; 644 645 /* 646 * Must disable bus master arbitration during the change. 647 */ 648 cntl = SS_READ(sc, LPCIB_PM_CTRL); 649 SS_WRITE(sc, LPCIB_PM_CTRL, cntl | LPCIB_PM_SS_CNTL_ARB_DIS); 650 SS_WRITE(sc, LPCIB_PM_SS_CNTL, state2); 651 SS_WRITE(sc, LPCIB_PM_CTRL, cntl); 652 } 653 splx(s); 654 out: 655 return error; 656 } 657 658 #if NHPET > 0 659 struct lpcib_hpet_attach_arg { 660 bus_space_tag_t hpet_mem_t; 661 uint32_t hpet_reg; 662 }; 663 664 static int 665 lpcib_hpet_match(device_t parent, cfdata_t match, void *aux) 666 { 667 struct lpcib_hpet_attach_arg *arg = aux; 668 bus_space_tag_t tag; 669 bus_space_handle_t handle; 670 671 tag = arg->hpet_mem_t; 672 673 if (bus_space_map(tag, arg->hpet_reg, HPET_WINDOW_SIZE, 0, &handle)) { 674 aprint_verbose_dev(parent, "HPET window not mapped, skipping\n"); 675 return 0; 676 } 677 bus_space_unmap(tag, handle, HPET_WINDOW_SIZE); 678 679 return 1; 680 } 681 682 static void 683 lpcib_hpet_attach(device_t parent, device_t self, void *aux) 684 { 685 struct hpet_softc *sc = device_private(self); 686 struct lpcib_hpet_attach_arg *arg = aux; 687 688 aprint_naive("\n"); 689 aprint_normal("\n"); 690 691 sc->sc_memt = arg->hpet_mem_t; 692 693 if (bus_space_map(sc->sc_memt, arg->hpet_reg, HPET_WINDOW_SIZE, 0, 694 &sc->sc_memh)) { 695 aprint_error_dev(self, 696 "HPET memory window could not be mapped"); 697 return; 698 } 699 700 hpet_attach_subr(self); 701 } 702 703 CFATTACH_DECL_NEW(ichlpcib_hpet, sizeof(struct hpet_softc), lpcib_hpet_match, 704 lpcib_hpet_attach, NULL, NULL); 705 706 static void 707 lpcib_hpet_configure(device_t self) 708 { 709 struct lpcib_softc *sc = device_private(self); 710 struct lpcib_hpet_attach_arg arg; 711 uint32_t hpet_reg, val; 712 713 if (sc->sc_has_ich5_hpet) { 714 val = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 715 LPCIB_PCI_GEN_CNTL); 716 switch (val & LPCIB_ICH5_HPTC_WIN_MASK) { 717 case LPCIB_ICH5_HPTC_0000: 718 hpet_reg = LPCIB_ICH5_HPTC_0000_BASE; 719 break; 720 case LPCIB_ICH5_HPTC_1000: 721 hpet_reg = LPCIB_ICH5_HPTC_1000_BASE; 722 break; 723 case LPCIB_ICH5_HPTC_2000: 724 hpet_reg = LPCIB_ICH5_HPTC_2000_BASE; 725 break; 726 case LPCIB_ICH5_HPTC_3000: 727 hpet_reg = LPCIB_ICH5_HPTC_3000_BASE; 728 break; 729 default: 730 return; 731 } 732 val |= sc->sc_hpet_reg | LPCIB_ICH5_HPTC_EN; 733 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 734 LPCIB_PCI_GEN_CNTL, val); 735 } else if (sc->sc_has_rcba) { 736 val = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 737 LPCIB_RCBA_HPTC); 738 switch (val & LPCIB_RCBA_HPTC_WIN_MASK) { 739 case LPCIB_RCBA_HPTC_0000: 740 hpet_reg = LPCIB_RCBA_HPTC_0000_BASE; 741 break; 742 case LPCIB_RCBA_HPTC_1000: 743 hpet_reg = LPCIB_RCBA_HPTC_1000_BASE; 744 break; 745 case LPCIB_RCBA_HPTC_2000: 746 hpet_reg = LPCIB_RCBA_HPTC_2000_BASE; 747 break; 748 case LPCIB_RCBA_HPTC_3000: 749 hpet_reg = LPCIB_RCBA_HPTC_3000_BASE; 750 break; 751 default: 752 return; 753 } 754 val |= LPCIB_RCBA_HPTC_EN; 755 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, LPCIB_RCBA_HPTC, 756 val); 757 } else { 758 /* No HPET here */ 759 return; 760 } 761 762 arg.hpet_mem_t = sc->sc_pa.pa_memt; 763 arg.hpet_reg = hpet_reg; 764 765 config_found_ia(self, "hpetichbus", &arg, NULL); 766 } 767 #endif 768