1 /* $NetBSD: dwiic_pci.c,v 1.9 2022/10/19 22:28:35 riastradh Exp $ */ 2 3 /*- 4 * Copyright (c) 2017 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Manuel Bouyer. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 /* 32 * Synopsys DesignWare I2C controller, PCI front-end 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: dwiic_pci.c,v 1.9 2022/10/19 22:28:35 riastradh Exp $"); 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 41 #include <dev/pci/pcireg.h> 42 #include <dev/pci/pcivar.h> 43 #include <dev/pci/pcidevs.h> 44 45 #include <dev/acpi/acpivar.h> 46 #include <dev/acpi/acpi_pci.h> 47 #include <dev/acpi/acpi_util.h> 48 #include <dev/acpi/acpi_i2c.h> 49 50 #include <dev/ic/dwiic_var.h> 51 #include <arch/x86/pci/lpssreg.h> 52 53 //#define DWIIC_DEBUG 54 55 #ifdef DWIIC_DEBUG 56 #define DPRINTF(x) printf x 57 #else 58 #define DPRINTF(x) 59 #endif 60 61 struct pci_dwiic_softc { 62 struct dwiic_softc sc_dwiic; 63 pci_chipset_tag_t sc_pc; 64 pcitag_t sc_ptag; 65 struct acpi_devnode *sc_acpinode; 66 }; 67 68 #define VIDDID(a, b) PCI_ID_CODE(PCI_VENDOR_ ## a, PCI_PRODUCT_ ## a ## _ ## b) 69 70 static const struct device_compatible_entry compat_data[] = { 71 { .id = VIDDID(INTEL, CORE4G_M_S_I2C_0) }, 72 { .id = VIDDID(INTEL, CORE4G_M_S_I2C_1) }, 73 { .id = VIDDID(INTEL, 100SERIES_I2C_0) }, 74 { .id = VIDDID(INTEL, 100SERIES_I2C_1) }, 75 { .id = VIDDID(INTEL, 100SERIES_I2C_2) }, 76 { .id = VIDDID(INTEL, 100SERIES_I2C_3) }, 77 { .id = VIDDID(INTEL, 100SERIES_LP_I2C_0) }, 78 { .id = VIDDID(INTEL, 100SERIES_LP_I2C_1) }, 79 { .id = VIDDID(INTEL, 100SERIES_LP_I2C_2) }, 80 { .id = VIDDID(INTEL, 100SERIES_LP_I2C_3) }, 81 { .id = VIDDID(INTEL, 100SERIES_LP_I2C_4) }, 82 { .id = VIDDID(INTEL, 100SERIES_LP_I2C_5) }, 83 { .id = VIDDID(INTEL, 2HS_I2C_0) }, 84 { .id = VIDDID(INTEL, 2HS_I2C_1) }, 85 { .id = VIDDID(INTEL, 2HS_I2C_2) }, 86 { .id = VIDDID(INTEL, 2HS_I2C_3) }, 87 { .id = VIDDID(INTEL, 3HS_I2C_0) }, 88 { .id = VIDDID(INTEL, 3HS_I2C_1) }, 89 { .id = VIDDID(INTEL, 3HS_I2C_2) }, 90 { .id = VIDDID(INTEL, 3HS_I2C_3) }, 91 { .id = VIDDID(INTEL, 3HS_U_I2C_0) }, 92 { .id = VIDDID(INTEL, 3HS_U_I2C_1) }, 93 { .id = VIDDID(INTEL, 3HS_U_I2C_2) }, 94 { .id = VIDDID(INTEL, 3HS_U_I2C_3) }, 95 { .id = VIDDID(INTEL, 3HS_U_I2C_4) }, 96 { .id = VIDDID(INTEL, 3HS_U_I2C_5) }, 97 { .id = VIDDID(INTEL, 4HS_H_I2C_0) }, 98 { .id = VIDDID(INTEL, 4HS_H_I2C_1) }, 99 { .id = VIDDID(INTEL, 4HS_H_I2C_2) }, 100 { .id = VIDDID(INTEL, 4HS_H_I2C_3) }, 101 { .id = VIDDID(INTEL, 4HS_V_I2C_0) }, 102 { .id = VIDDID(INTEL, 4HS_V_I2C_1) }, 103 { .id = VIDDID(INTEL, 4HS_V_I2C_2) }, 104 { .id = VIDDID(INTEL, 4HS_V_I2C_3) }, 105 { .id = VIDDID(INTEL, CMTLK_I2C_0) }, /* 4HS LP */ 106 { .id = VIDDID(INTEL, CMTLK_I2C_1) }, 107 { .id = VIDDID(INTEL, CMTLK_I2C_2) }, 108 { .id = VIDDID(INTEL, CMTLK_I2C_3) }, 109 { .id = VIDDID(INTEL, CMTLK_I2C_4) }, 110 { .id = VIDDID(INTEL, CMTLK_I2C_5) }, 111 { .id = VIDDID(INTEL, 495_YU_I2C_0) }, 112 { .id = VIDDID(INTEL, 495_YU_I2C_1) }, 113 { .id = VIDDID(INTEL, 495_YU_I2C_2) }, 114 { .id = VIDDID(INTEL, 495_YU_I2C_3) }, 115 { .id = VIDDID(INTEL, 495_YU_I2C_4) }, 116 { .id = VIDDID(INTEL, 495_YU_I2C_5) }, 117 { .id = VIDDID(INTEL, 5HS_H_I2C_0) }, 118 { .id = VIDDID(INTEL, 5HS_H_I2C_1) }, 119 { .id = VIDDID(INTEL, 5HS_H_I2C_2) }, 120 { .id = VIDDID(INTEL, 5HS_H_I2C_3) }, 121 { .id = VIDDID(INTEL, 5HS_H_I2C_4) }, 122 { .id = VIDDID(INTEL, 5HS_H_I2C_5) }, 123 { .id = VIDDID(INTEL, 5HS_H_I2C_6) }, 124 { .id = VIDDID(INTEL, 5HS_LP_I2C_0) }, 125 { .id = VIDDID(INTEL, 5HS_LP_I2C_1) }, 126 { .id = VIDDID(INTEL, 5HS_LP_I2C_2) }, 127 { .id = VIDDID(INTEL, 5HS_LP_I2C_3) }, 128 { .id = VIDDID(INTEL, 5HS_LP_I2C_4) }, 129 { .id = VIDDID(INTEL, 5HS_LP_I2C_5) }, 130 { .id = VIDDID(INTEL, BAYTRAIL_SIO_I2C1) }, 131 { .id = VIDDID(INTEL, BAYTRAIL_SIO_I2C2) }, 132 { .id = VIDDID(INTEL, BAYTRAIL_SIO_I2C3) }, 133 { .id = VIDDID(INTEL, BAYTRAIL_SIO_I2C4) }, 134 { .id = VIDDID(INTEL, BAYTRAIL_SIO_I2C5) }, 135 { .id = VIDDID(INTEL, BAYTRAIL_SIO_I2C6) }, 136 { .id = VIDDID(INTEL, BAYTRAIL_SIO_I2C7) }, 137 { .id = VIDDID(INTEL, BSW_SIO_I2C_1) }, 138 { .id = VIDDID(INTEL, BSW_SIO_I2C_2) }, 139 { .id = VIDDID(INTEL, BSW_SIO_I2C_3) }, 140 { .id = VIDDID(INTEL, BSW_SIO_I2C_4) }, 141 { .id = VIDDID(INTEL, BSW_SIO_I2C_5) }, 142 { .id = VIDDID(INTEL, BSW_SIO_I2C_6) }, 143 { .id = VIDDID(INTEL, BSW_SIO_I2C_7) }, 144 { .id = VIDDID(INTEL, APL_I2C_0) }, 145 { .id = VIDDID(INTEL, APL_I2C_1) }, 146 { .id = VIDDID(INTEL, APL_I2C_2) }, 147 { .id = VIDDID(INTEL, APL_I2C_3) }, 148 { .id = VIDDID(INTEL, APL_I2C_4) }, 149 { .id = VIDDID(INTEL, APL_I2C_5) }, 150 { .id = VIDDID(INTEL, APL_I2C_6) }, 151 { .id = VIDDID(INTEL, APL_I2C_7) }, 152 { .id = VIDDID(INTEL, GLK_I2C_0) }, 153 { .id = VIDDID(INTEL, GLK_I2C_1) }, 154 { .id = VIDDID(INTEL, GLK_I2C_2) }, 155 { .id = VIDDID(INTEL, GLK_I2C_3) }, 156 { .id = VIDDID(INTEL, GLK_I2C_4) }, 157 { .id = VIDDID(INTEL, GLK_I2C_5) }, 158 { .id = VIDDID(INTEL, GLK_I2C_6) }, 159 { .id = VIDDID(INTEL, GLK_I2C_7) }, 160 { .id = VIDDID(INTEL, EHL_SIO_I2C_0) }, 161 { .id = VIDDID(INTEL, EHL_SIO_I2C_1) }, 162 { .id = VIDDID(INTEL, EHL_SIO_I2C_2) }, 163 { .id = VIDDID(INTEL, EHL_SIO_I2C_3) }, 164 { .id = VIDDID(INTEL, EHL_SIO_I2C_4) }, 165 { .id = VIDDID(INTEL, EHL_SIO_I2C_5) }, 166 { .id = VIDDID(INTEL, EHL_SIO_I2C_6) }, 167 { .id = VIDDID(INTEL, EHL_SIO_I2C_7) }, 168 { .id = VIDDID(INTEL, JSL_LPSS_I2C_0) }, 169 { .id = VIDDID(INTEL, JSL_LPSS_I2C_1) }, 170 { .id = VIDDID(INTEL, JSL_LPSS_I2C_2) }, 171 { .id = VIDDID(INTEL, JSL_LPSS_I2C_3) }, 172 { .id = VIDDID(INTEL, JSL_LPSS_I2C_4) }, 173 { .id = VIDDID(INTEL, JSL_LPSS_I2C_5) }, 174 175 PCI_COMPAT_EOL 176 }; 177 178 static uint32_t 179 lpss_read(struct pci_dwiic_softc *sc, int offset) 180 { 181 return bus_space_read_4(sc->sc_dwiic.sc_iot, sc->sc_dwiic.sc_ioh, 182 offset); 183 } 184 185 static void 186 lpss_write(struct pci_dwiic_softc *sc, int offset, uint32_t val) 187 { 188 bus_space_write_4(sc->sc_dwiic.sc_iot, sc->sc_dwiic.sc_ioh, 189 offset, val); 190 } 191 192 static int pci_dwiic_match(device_t, cfdata_t, void *); 193 static void pci_dwiic_attach(device_t, device_t, void *); 194 static bool dwiic_pci_power(struct dwiic_softc *, bool); 195 196 CFATTACH_DECL_NEW(pcidwiic, sizeof(struct pci_dwiic_softc), 197 pci_dwiic_match, pci_dwiic_attach, dwiic_detach, NULL); 198 199 200 int 201 pci_dwiic_match(device_t parent, cfdata_t match, void *aux) 202 { 203 struct pci_attach_args *pa = aux; 204 205 return pci_compatible_match(pa, compat_data); 206 } 207 208 void 209 pci_dwiic_attach(device_t parent, device_t self, void *aux) 210 { 211 struct pci_dwiic_softc *sc = device_private(self); 212 struct pci_attach_args *pa = aux; 213 const char *intrstr; 214 pci_intr_handle_t intrhandle; 215 char intrbuf[PCI_INTRSTR_LEN]; 216 pcireg_t memtype; 217 pcireg_t csr; 218 uint32_t caps; 219 220 sc->sc_dwiic.sc_dev = self; 221 sc->sc_dwiic.sc_power = dwiic_pci_power; 222 sc->sc_dwiic.sc_type = dwiic_type_sunrisepoint; 223 224 sc->sc_pc = pa->pa_pc; 225 sc->sc_ptag = pa->pa_tag; 226 227 /* register access not enabled by BIOS */ 228 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 229 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 230 csr | PCI_COMMAND_MEM_ENABLE); 231 232 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, PCI_BAR0); 233 if (pci_mapreg_map(pa, PCI_BAR0, memtype, 0, &sc->sc_dwiic.sc_iot, 234 &sc->sc_dwiic.sc_ioh, NULL, NULL) != 0) { 235 aprint_error(": can't map register space\n"); 236 goto out; 237 } 238 dwiic_pci_power(&sc->sc_dwiic, 1); 239 240 caps = lpss_read(sc, LPSS_CAP); 241 242 aprint_naive(": I2C controller\n"); 243 aprint_normal(": I2C controller instance %d\n", 244 (int)(caps & LPSS_CAP_INSTANCE)); 245 246 if (pci_intr_map(pa, &intrhandle)) { 247 aprint_error_dev(self, "can't map interrupt\n"); 248 goto out; 249 } 250 intrstr = pci_intr_string(pa->pa_pc, intrhandle, 251 intrbuf, sizeof(intrbuf)); 252 253 sc->sc_dwiic.sc_ih = pci_intr_establish(pa->pa_pc, intrhandle, 254 IPL_VM, dwiic_intr, sc); 255 if (sc->sc_dwiic.sc_ih == NULL) { 256 aprint_error_dev(self, "couldn't establish interrupt"); 257 if (intrstr != NULL) 258 aprint_error(" at %s", intrstr); 259 aprint_error("\n"); 260 goto out; 261 } 262 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 263 264 lpss_write(sc, LPSS_RESET, LPSS_RESET_CTRL_REL); 265 lpss_write(sc, LPSS_REMAP_LO, 266 pci_conf_read(sc->sc_pc, sc->sc_ptag, PCI_BAR0)); 267 lpss_write(sc, LPSS_REMAP_HI, 268 pci_conf_read(sc->sc_pc, sc->sc_ptag, PCI_BAR0 + 0x4)); 269 270 sc->sc_acpinode = acpi_pcidev_find(0 /*XXX segment*/, 271 pa->pa_bus, pa->pa_device, pa->pa_function); 272 273 if (sc->sc_acpinode) { 274 sc->sc_dwiic.sc_iba.iba_child_devices = 275 acpi_enter_i2c_devs(NULL, sc->sc_acpinode); 276 } else { 277 aprint_verbose_dev(self, "no matching ACPI node\n"); 278 } 279 280 if (!dwiic_attach(&sc->sc_dwiic)) 281 goto out; 282 283 config_found(self, &sc->sc_dwiic.sc_iba, iicbus_print, CFARGS_NONE); 284 285 pmf_device_register(self, dwiic_suspend, dwiic_resume); 286 287 out: 288 return; 289 } 290 291 static bool 292 dwiic_pci_power(struct dwiic_softc *dwsc, bool power) 293 { 294 struct pci_dwiic_softc *sc = container_of(dwsc, struct pci_dwiic_softc, 295 sc_dwiic); 296 pcireg_t pmreg, csr; 297 uint32_t reset, rlo, rhi; 298 299 csr = pci_conf_read(sc->sc_pc, sc->sc_ptag, PCI_COMMAND_STATUS_REG); 300 reset = lpss_read(sc, LPSS_RESET); 301 rlo = lpss_read(sc, LPSS_REMAP_LO); 302 rhi = lpss_read(sc, LPSS_REMAP_HI); 303 aprint_debug_dev(dwsc->sc_dev, 304 "status 0x%x reset 0x%x rlo 0x%x rhi 0x%x\n", 305 csr, reset, rlo, rhi); 306 307 if (!power) 308 lpss_write(sc, LPSS_CLKGATE, LPSS_CLKGATE_CTRL_OFF); 309 if (pci_get_capability(sc->sc_pc, sc->sc_ptag, PCI_CAP_PWRMGMT, 310 &pmreg, NULL)) { 311 DPRINTF(("%s: power status 0x%x", device_xname(dwsc->sc_dev), 312 pci_conf_read(sc->sc_pc, sc->sc_ptag, pmreg + PCI_PMCSR))); 313 pci_conf_write(sc->sc_pc, sc->sc_ptag, pmreg + PCI_PMCSR, 314 power ? PCI_PMCSR_STATE_D0 : PCI_PMCSR_STATE_D3); 315 DELAY(10000); /* 10 milliseconds */ 316 DPRINTF((" -> 0x%x\n", 317 pci_conf_read(sc->sc_pc, sc->sc_ptag, pmreg + PCI_PMCSR))); 318 } 319 if (power) { 320 lpss_write(sc, LPSS_CLKGATE, LPSS_CLKGATE_CTRL_ON); 321 } 322 return true; 323 } 324