1 /* $NetBSD: amdtemp.c,v 1.13 2012/03/02 19:26:41 nonaka Exp $ */ 2 /* $OpenBSD: kate.c,v 1.2 2008/03/27 04:52:03 cnst Exp $ */ 3 4 /* 5 * Copyright (c) 2008 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Christoph Egger. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Copyright (c) 2008 Constantine A. Murenin <cnst+openbsd@bugmail.mojo.ru> 35 * 36 * Permission to use, copy, modify, and distribute this software for any 37 * purpose with or without fee is hereby granted, provided that the above 38 * copyright notice and this permission notice appear in all copies. 39 * 40 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 41 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 42 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 43 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 44 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 45 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 46 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 47 */ 48 49 50 #include <sys/cdefs.h> 51 __KERNEL_RCSID(0, "$NetBSD: amdtemp.c,v 1.13 2012/03/02 19:26:41 nonaka Exp $ "); 52 53 #include <sys/param.h> 54 #include <sys/bus.h> 55 #include <sys/cpu.h> 56 #include <sys/systm.h> 57 #include <sys/device.h> 58 #include <sys/kmem.h> 59 #include <sys/module.h> 60 61 #include <machine/specialreg.h> 62 63 #include <dev/pci/pcireg.h> 64 #include <dev/pci/pcivar.h> 65 #include <dev/pci/pcidevs.h> 66 67 #include <dev/sysmon/sysmonvar.h> 68 69 /* 70 * AMD K8: 71 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/32559.pdf 72 * AMD K8 Errata: #141 73 * http://support.amd.com/us/Processor_TechDocs/33610_PUB_Rev3%2042v3.pdf 74 * 75 * Family10h: 76 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/31116.PDF 77 * Family10h Errata: #319 78 * http://support.amd.com/de/Processor_TechDocs/41322.pdf 79 * 80 * Family11h: 81 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/41256.pdf 82 */ 83 84 /* AMD Processors, Function 3 -- Miscellaneous Control 85 */ 86 87 /* Function 3 Registers */ 88 #define THERMTRIP_STAT_R 0xe4 89 #define NORTHBRIDGE_CAP_R 0xe8 90 #define CPUID_FAMILY_MODEL_R 0xfc 91 92 /* 93 * AMD NPT Family 0Fh Processors, Function 3 -- Miscellaneous Control 94 */ 95 96 /* Bits within Thermtrip Status Register */ 97 #define K8_THERM_SENSE_SEL (1 << 6) 98 #define K8_THERM_SENSE_CORE_SEL (1 << 2) 99 100 /* Flip core and sensor selection bits */ 101 #define K8_T_SEL_C0(v) (v |= K8_THERM_SENSE_CORE_SEL) 102 #define K8_T_SEL_C1(v) (v &= ~(K8_THERM_SENSE_CORE_SEL)) 103 #define K8_T_SEL_S0(v) (v &= ~(K8_THERM_SENSE_SEL)) 104 #define K8_T_SEL_S1(v) (v |= K8_THERM_SENSE_SEL) 105 106 107 108 /* 109 * AMD Family 10h Processors, Function 3 -- Miscellaneous Control 110 */ 111 112 /* Function 3 Registers */ 113 #define F10_TEMPERATURE_CTL_R 0xa4 114 115 /* Bits within Reported Temperature Control Register */ 116 #define F10_TEMP_CURTEMP (1 << 21) 117 118 /* 119 * Revision Guide for AMD NPT Family 0Fh Processors, 120 * Publication # 33610, Revision 3.30, February 2008 121 */ 122 #define K8_SOCKET_F 1 /* Server */ 123 #define K8_SOCKET_AM2 2 /* Desktop */ 124 #define K8_SOCKET_S1 3 /* Laptop */ 125 126 static const struct { 127 const char rev[5]; 128 const struct { 129 const pcireg_t cpuid; 130 const uint8_t socket; 131 } cpu[5]; 132 } amdtemp_core[] = { 133 { "BH-F", { { 0x00040FB0, K8_SOCKET_AM2 }, /* F2 */ 134 { 0x00040F80, K8_SOCKET_S1 }, /* F2 */ 135 { 0, 0 }, { 0, 0 }, { 0, 0 } } }, 136 { "DH-F", { { 0x00040FF0, K8_SOCKET_AM2 }, /* F2 */ 137 { 0x00040FC0, K8_SOCKET_S1 }, /* F2 */ 138 { 0x00050FF0, K8_SOCKET_AM2 }, /* F2, F3 */ 139 { 0, 0 }, { 0, 0 } } }, 140 { "JH-F", { { 0x00040F10, K8_SOCKET_F }, /* F2, F3 */ 141 { 0x00040F30, K8_SOCKET_AM2 }, /* F2, F3 */ 142 { 0x000C0F10, K8_SOCKET_F }, /* F3 */ 143 { 0, 0 }, { 0, 0 } } }, 144 { "BH-G", { { 0x00060FB0, K8_SOCKET_AM2 }, /* G1, G2 */ 145 { 0x00060F80, K8_SOCKET_S1 }, /* G1, G2 */ 146 { 0, 0 }, { 0, 0 }, { 0, 0 } } }, 147 { "DH-G", { { 0x00060FF0, K8_SOCKET_AM2 }, /* G1, G2 */ 148 { 0x00060FC0, K8_SOCKET_S1 }, /* G2 */ 149 { 0x00070FF0, K8_SOCKET_AM2 }, /* G1, G2 */ 150 { 0x00070FC0, K8_SOCKET_S1 }, /* G2 */ 151 { 0, 0 } } } 152 }; 153 154 155 struct amdtemp_softc { 156 pci_chipset_tag_t sc_pc; 157 pcitag_t sc_pcitag; 158 159 struct sysmon_envsys *sc_sme; 160 envsys_data_t *sc_sensor; 161 size_t sc_sensor_len; 162 163 char sc_rev; 164 int8_t sc_numsensors; 165 uint32_t sc_family; 166 int32_t sc_adjustment; 167 }; 168 169 170 static int amdtemp_match(device_t, cfdata_t, void *); 171 static void amdtemp_attach(device_t, device_t, void *); 172 static int amdtemp_detach(device_t, int); 173 174 static void amdtemp_k8_init(struct amdtemp_softc *, pcireg_t); 175 static void amdtemp_k8_setup_sensors(struct amdtemp_softc *, int); 176 static void amdtemp_k8_refresh(struct sysmon_envsys *, envsys_data_t *); 177 178 static void amdtemp_family10_init(struct amdtemp_softc *); 179 static void amdtemp_family10_setup_sensors(struct amdtemp_softc *, int); 180 static void amdtemp_family10_refresh(struct sysmon_envsys *, envsys_data_t *); 181 182 CFATTACH_DECL_NEW(amdtemp, sizeof(struct amdtemp_softc), 183 amdtemp_match, amdtemp_attach, amdtemp_detach, NULL); 184 185 static int 186 amdtemp_match(device_t parent, cfdata_t match, void *aux) 187 { 188 struct pci_attach_args *pa = aux; 189 pcireg_t cpu_signature; 190 uint32_t family; 191 192 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_AMD) 193 return 0; 194 195 switch (PCI_PRODUCT(pa->pa_id)) { 196 case PCI_PRODUCT_AMD_AMD64_MISC: 197 case PCI_PRODUCT_AMD_AMD64_F10_MISC: 198 case PCI_PRODUCT_AMD_AMD64_F11_MISC: 199 case PCI_PRODUCT_AMD_F14_NB: /* Family12h too */ 200 break; 201 default: 202 return 0; 203 } 204 205 cpu_signature = pci_conf_read(pa->pa_pc, 206 pa->pa_tag, CPUID_FAMILY_MODEL_R); 207 208 /* This CPUID northbridge register has been introduced 209 * in Revision F */ 210 if (cpu_signature == 0x0) 211 return 0; 212 213 family = CPUID2FAMILY(cpu_signature); 214 if (family == 0xf) 215 family += CPUID2EXTFAMILY(cpu_signature); 216 217 /* Errata #319: This has been fixed in Revision C2. */ 218 if (family == 0x10) { 219 if (CPUID2MODEL(cpu_signature) < 4) 220 return 0; 221 if (CPUID2MODEL(cpu_signature) == 4 222 && CPUID2STEPPING(cpu_signature) < 2) 223 return 0; 224 } 225 226 227 /* Not yet supported CPUs */ 228 if (family > 0x14) 229 return 0; 230 231 return 2; /* supercede pchb(4) */ 232 } 233 234 static void 235 amdtemp_attach(device_t parent, device_t self, void *aux) 236 { 237 struct amdtemp_softc *sc = device_private(self); 238 struct pci_attach_args *pa = aux; 239 pcireg_t cpu_signature; 240 int error; 241 uint8_t i; 242 243 aprint_naive("\n"); 244 aprint_normal(": AMD CPU Temperature Sensors"); 245 246 cpu_signature = pci_conf_read(pa->pa_pc, 247 pa->pa_tag, CPUID_FAMILY_MODEL_R); 248 249 /* If we hit this, then match routine is wrong. */ 250 KASSERT(cpu_signature != 0x0); 251 252 sc->sc_family = CPUID2FAMILY(cpu_signature); 253 sc->sc_family += CPUID2EXTFAMILY(cpu_signature); 254 255 KASSERT(sc->sc_family >= 0xf); 256 257 sc->sc_sme = NULL; 258 sc->sc_sensor = NULL; 259 260 sc->sc_pc = pa->pa_pc; 261 sc->sc_pcitag = pa->pa_tag; 262 sc->sc_adjustment = 0; 263 264 switch (sc->sc_family) { 265 case 0xf: /* AMD K8 NPT */ 266 amdtemp_k8_init(sc, cpu_signature); 267 break; 268 269 case 0x10: /* AMD Barcelona/Phenom */ 270 case 0x11: /* AMD Griffin */ 271 case 0x12: /* AMD Lynx/Sabine (Llano) */ 272 case 0x14: /* AMD Brazos (Ontario/Zacate/Desna) */ 273 amdtemp_family10_init(sc); 274 break; 275 276 default: 277 aprint_normal(", family 0x%x not supported\n", 278 sc->sc_family); 279 return; 280 } 281 282 aprint_normal("\n"); 283 284 if (sc->sc_adjustment != 0) 285 aprint_debug_dev(self, "Workaround enabled\n"); 286 287 sc->sc_sme = sysmon_envsys_create(); 288 sc->sc_sensor_len = sizeof(envsys_data_t) * sc->sc_numsensors; 289 sc->sc_sensor = kmem_zalloc(sc->sc_sensor_len, KM_SLEEP); 290 291 if (sc->sc_sensor == NULL) 292 goto bad; 293 294 switch (sc->sc_family) { 295 case 0xf: 296 amdtemp_k8_setup_sensors(sc, device_unit(self)); 297 break; 298 case 0x10: 299 case 0x11: 300 case 0x12: 301 case 0x14: 302 amdtemp_family10_setup_sensors(sc, device_unit(self)); 303 break; 304 } 305 306 /* 307 * Set properties in sensors. 308 */ 309 for (i = 0; i < sc->sc_numsensors; i++) { 310 if (sysmon_envsys_sensor_attach(sc->sc_sme, 311 &sc->sc_sensor[i])) 312 goto bad; 313 } 314 315 /* 316 * Register the sysmon_envsys device. 317 */ 318 sc->sc_sme->sme_name = device_xname(self); 319 sc->sc_sme->sme_cookie = sc; 320 321 switch (sc->sc_family) { 322 case 0xf: 323 sc->sc_sme->sme_refresh = amdtemp_k8_refresh; 324 break; 325 case 0x10: 326 case 0x11: 327 case 0x12: 328 case 0x14: 329 sc->sc_sme->sme_refresh = amdtemp_family10_refresh; 330 break; 331 } 332 333 error = sysmon_envsys_register(sc->sc_sme); 334 if (error) { 335 aprint_error_dev(self, "unable to register with sysmon " 336 "(error=%d)\n", error); 337 goto bad; 338 } 339 340 (void)pmf_device_register(self, NULL, NULL); 341 342 return; 343 344 bad: 345 if (sc->sc_sme != NULL) { 346 sysmon_envsys_destroy(sc->sc_sme); 347 sc->sc_sme = NULL; 348 } 349 350 if (sc->sc_sensor != NULL) { 351 kmem_free(sc->sc_sensor, sc->sc_sensor_len); 352 sc->sc_sensor = NULL; 353 } 354 } 355 356 static int 357 amdtemp_detach(device_t self, int flags) 358 { 359 struct amdtemp_softc *sc = device_private(self); 360 361 if (sc->sc_sme != NULL) 362 sysmon_envsys_unregister(sc->sc_sme); 363 364 if (sc->sc_sensor != NULL) 365 kmem_free(sc->sc_sensor, sc->sc_sensor_len); 366 367 return 0; 368 } 369 370 static void 371 amdtemp_k8_init(struct amdtemp_softc *sc, pcireg_t cpu_signature) 372 { 373 pcireg_t data; 374 uint32_t cmpcap; 375 uint8_t i, j; 376 377 aprint_normal(" (K8"); 378 379 for (i = 0; i < __arraycount(amdtemp_core) && sc->sc_rev == '\0'; i++) { 380 for (j = 0; amdtemp_core[i].cpu[j].cpuid != 0; j++) { 381 if ((cpu_signature & ~0xf) 382 != amdtemp_core[i].cpu[j].cpuid) 383 continue; 384 385 sc->sc_rev = amdtemp_core[i].rev[3]; 386 aprint_normal(": core rev %.4s%.1x", 387 amdtemp_core[i].rev, 388 CPUID2STEPPING(cpu_signature)); 389 390 switch (amdtemp_core[i].cpu[j].socket) { 391 case K8_SOCKET_AM2: 392 if (sc->sc_rev == 'G') 393 sc->sc_adjustment = 21000000; 394 aprint_normal(", socket AM2"); 395 break; 396 case K8_SOCKET_S1: 397 aprint_normal(", socket S1"); 398 break; 399 case K8_SOCKET_F: 400 aprint_normal(", socket F"); 401 break; 402 } 403 } 404 } 405 406 if (sc->sc_rev == '\0') { 407 /* CPUID Family Model Register was introduced in 408 * Revision F */ 409 sc->sc_rev = 'G'; /* newer than E, assume G */ 410 aprint_normal(": cpuid 0x%x", cpu_signature); 411 } 412 413 aprint_normal(")"); 414 415 data = pci_conf_read(sc->sc_pc, sc->sc_pcitag, NORTHBRIDGE_CAP_R); 416 cmpcap = (data >> 12) & 0x3; 417 418 sc->sc_numsensors = cmpcap ? 4 : 2; 419 } 420 421 422 static void 423 amdtemp_k8_setup_sensors(struct amdtemp_softc *sc, int dv_unit) 424 { 425 uint8_t i; 426 427 /* There are two sensors per CPU core. So we use the 428 * device unit as socket counter to correctly enumerate 429 * the CPUs on multi-socket machines. 430 */ 431 dv_unit *= (sc->sc_numsensors / 2); 432 for (i = 0; i < sc->sc_numsensors; i++) { 433 sc->sc_sensor[i].units = ENVSYS_STEMP; 434 sc->sc_sensor[i].state = ENVSYS_SVALID; 435 436 snprintf(sc->sc_sensor[i].desc, sizeof(sc->sc_sensor[i].desc), 437 "CPU%u Sensor%u", dv_unit + (i / 2), i % 2); 438 } 439 } 440 441 442 static void 443 amdtemp_k8_refresh(struct sysmon_envsys *sme, envsys_data_t *edata) 444 { 445 struct amdtemp_softc *sc = sme->sme_cookie; 446 pcireg_t status, match, tmp; 447 uint32_t value; 448 449 status = pci_conf_read(sc->sc_pc, sc->sc_pcitag, THERMTRIP_STAT_R); 450 451 switch(edata->sensor) { /* sensor number */ 452 case 0: /* Core 0 Sensor 0 */ 453 K8_T_SEL_C0(status); 454 K8_T_SEL_S0(status); 455 break; 456 case 1: /* Core 0 Sensor 1 */ 457 K8_T_SEL_C0(status); 458 K8_T_SEL_S1(status); 459 break; 460 case 2: /* Core 1 Sensor 0 */ 461 K8_T_SEL_C1(status); 462 K8_T_SEL_S0(status); 463 break; 464 case 3: /* Core 1 Sensor 1 */ 465 K8_T_SEL_C1(status); 466 K8_T_SEL_S1(status); 467 break; 468 } 469 470 match = status & (K8_THERM_SENSE_CORE_SEL | K8_THERM_SENSE_SEL); 471 pci_conf_write(sc->sc_pc, sc->sc_pcitag, THERMTRIP_STAT_R, status); 472 status = pci_conf_read(sc->sc_pc, sc->sc_pcitag, THERMTRIP_STAT_R); 473 tmp = status & (K8_THERM_SENSE_CORE_SEL | K8_THERM_SENSE_SEL); 474 475 value = 0x3ff & (status >> 14); 476 if (sc->sc_rev != 'G') 477 value &= ~0x3; 478 479 edata->state = ENVSYS_SINVALID; 480 if ((tmp == match) && ((value & ~0x3) != 0)) { 481 edata->state = ENVSYS_SVALID; 482 edata->value_cur = (value * 250000 - 49000000) + 273150000 483 + sc->sc_adjustment; 484 } 485 } 486 487 488 static void 489 amdtemp_family10_init(struct amdtemp_softc *sc) 490 { 491 aprint_normal(" (Family%02xh)", sc->sc_family); 492 493 sc->sc_numsensors = 1; 494 } 495 496 static void 497 amdtemp_family10_setup_sensors(struct amdtemp_softc *sc, int dv_unit) 498 { 499 /* sanity check for future enhancements */ 500 KASSERT(sc->sc_numsensors == 1); 501 502 /* There's one sensor per memory controller (= socket) 503 * so we use the device unit as socket counter 504 * to correctly enumerate the CPUs 505 */ 506 sc->sc_sensor[0].units = ENVSYS_STEMP; 507 sc->sc_sensor[0].state = ENVSYS_SVALID; 508 509 snprintf(sc->sc_sensor[0].desc, sizeof(sc->sc_sensor[0].desc), 510 "cpu%u temperature", dv_unit); 511 } 512 513 514 static void 515 amdtemp_family10_refresh(struct sysmon_envsys *sme, envsys_data_t *edata) 516 { 517 struct amdtemp_softc *sc = sme->sme_cookie; 518 pcireg_t status; 519 uint32_t value; 520 521 status = pci_conf_read(sc->sc_pc, 522 sc->sc_pcitag, F10_TEMPERATURE_CTL_R); 523 524 value = (status >> 21); 525 526 edata->state = ENVSYS_SVALID; 527 edata->value_cur = (value * 125000) + 273150000; /* From C to uK. */ 528 } 529 530 MODULE(MODULE_CLASS_DRIVER, amdtemp, NULL); 531 532 #ifdef _MODULE 533 #include "ioconf.c" 534 #endif 535 536 static int 537 amdtemp_modcmd(modcmd_t cmd, void *aux) 538 { 539 int error = 0; 540 541 switch (cmd) { 542 case MODULE_CMD_INIT: 543 #ifdef _MODULE 544 error = config_init_component(cfdriver_ioconf_amdtemp, 545 cfattach_ioconf_amdtemp, cfdata_ioconf_amdtemp); 546 #endif 547 return error; 548 case MODULE_CMD_FINI: 549 #ifdef _MODULE 550 error = config_fini_component(cfdriver_ioconf_amdtemp, 551 cfattach_ioconf_amdtemp, cfdata_ioconf_amdtemp); 552 #endif 553 return error; 554 default: 555 return ENOTTY; 556 } 557 } 558