1 /* $NetBSD: amdtemp.c,v 1.16 2012/07/16 01:52:37 pgoyette Exp $ */ 2 /* $OpenBSD: kate.c,v 1.2 2008/03/27 04:52:03 cnst Exp $ */ 3 4 /* 5 * Copyright (c) 2008 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Christoph Egger. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Copyright (c) 2008 Constantine A. Murenin <cnst+openbsd@bugmail.mojo.ru> 35 * 36 * Permission to use, copy, modify, and distribute this software for any 37 * purpose with or without fee is hereby granted, provided that the above 38 * copyright notice and this permission notice appear in all copies. 39 * 40 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 41 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 42 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 43 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 44 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 45 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 46 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 47 */ 48 49 50 #include <sys/cdefs.h> 51 __KERNEL_RCSID(0, "$NetBSD: amdtemp.c,v 1.16 2012/07/16 01:52:37 pgoyette Exp $ "); 52 53 #include <sys/param.h> 54 #include <sys/bus.h> 55 #include <sys/cpu.h> 56 #include <sys/systm.h> 57 #include <sys/device.h> 58 #include <sys/kmem.h> 59 #include <sys/module.h> 60 61 #include <machine/specialreg.h> 62 63 #include <dev/pci/pcireg.h> 64 #include <dev/pci/pcivar.h> 65 #include <dev/pci/pcidevs.h> 66 67 #include <dev/sysmon/sysmonvar.h> 68 69 /* 70 * AMD K8: 71 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/32559.pdf 72 * AMD K8 Errata: #141 73 * http://support.amd.com/us/Processor_TechDocs/33610_PUB_Rev3%2042v3.pdf 74 * 75 * Family10h: 76 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/31116.PDF 77 * Family10h Errata: #319 78 * http://support.amd.com/de/Processor_TechDocs/41322.pdf 79 * 80 * Family11h: 81 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/41256.pdf 82 */ 83 84 /* AMD Processors, Function 3 -- Miscellaneous Control 85 */ 86 87 /* Function 3 Registers */ 88 #define THERMTRIP_STAT_R 0xe4 89 #define NORTHBRIDGE_CAP_R 0xe8 90 #define CPUID_FAMILY_MODEL_R 0xfc 91 92 /* 93 * AMD NPT Family 0Fh Processors, Function 3 -- Miscellaneous Control 94 */ 95 96 /* Bits within Thermtrip Status Register */ 97 #define K8_THERM_SENSE_SEL (1 << 6) 98 #define K8_THERM_SENSE_CORE_SEL (1 << 2) 99 100 /* Flip core and sensor selection bits */ 101 #define K8_T_SEL_C0(v) (v |= K8_THERM_SENSE_CORE_SEL) 102 #define K8_T_SEL_C1(v) (v &= ~(K8_THERM_SENSE_CORE_SEL)) 103 #define K8_T_SEL_S0(v) (v &= ~(K8_THERM_SENSE_SEL)) 104 #define K8_T_SEL_S1(v) (v |= K8_THERM_SENSE_SEL) 105 106 107 108 /* 109 * AMD Family 10h Processors, Function 3 -- Miscellaneous Control 110 */ 111 112 /* Function 3 Registers */ 113 #define F10_TEMPERATURE_CTL_R 0xa4 114 115 /* Bits within Reported Temperature Control Register */ 116 #define F10_TEMP_CURTEMP (1 << 21) 117 118 /* 119 * Revision Guide for AMD NPT Family 0Fh Processors, 120 * Publication # 33610, Revision 3.30, February 2008 121 */ 122 #define K8_SOCKET_F 1 /* Server */ 123 #define K8_SOCKET_AM2 2 /* Desktop */ 124 #define K8_SOCKET_S1 3 /* Laptop */ 125 126 static const struct { 127 const char rev[5]; 128 const struct { 129 const pcireg_t cpuid; 130 const uint8_t socket; 131 } cpu[5]; 132 } amdtemp_core[] = { 133 { "BH-F", { { 0x00040FB0, K8_SOCKET_AM2 }, /* F2 */ 134 { 0x00040F80, K8_SOCKET_S1 }, /* F2 */ 135 { 0, 0 }, { 0, 0 }, { 0, 0 } } }, 136 { "DH-F", { { 0x00040FF0, K8_SOCKET_AM2 }, /* F2 */ 137 { 0x00040FC0, K8_SOCKET_S1 }, /* F2 */ 138 { 0x00050FF0, K8_SOCKET_AM2 }, /* F2, F3 */ 139 { 0, 0 }, { 0, 0 } } }, 140 { "JH-F", { { 0x00040F10, K8_SOCKET_F }, /* F2, F3 */ 141 { 0x00040F30, K8_SOCKET_AM2 }, /* F2, F3 */ 142 { 0x000C0F10, K8_SOCKET_F }, /* F3 */ 143 { 0, 0 }, { 0, 0 } } }, 144 { "BH-G", { { 0x00060FB0, K8_SOCKET_AM2 }, /* G1, G2 */ 145 { 0x00060F80, K8_SOCKET_S1 }, /* G1, G2 */ 146 { 0, 0 }, { 0, 0 }, { 0, 0 } } }, 147 { "DH-G", { { 0x00060FF0, K8_SOCKET_AM2 }, /* G1, G2 */ 148 { 0x00060FC0, K8_SOCKET_S1 }, /* G2 */ 149 { 0x00070FF0, K8_SOCKET_AM2 }, /* G1, G2 */ 150 { 0x00070FC0, K8_SOCKET_S1 }, /* G2 */ 151 { 0, 0 } } } 152 }; 153 154 155 struct amdtemp_softc { 156 pci_chipset_tag_t sc_pc; 157 pcitag_t sc_pcitag; 158 159 struct sysmon_envsys *sc_sme; 160 envsys_data_t *sc_sensor; 161 size_t sc_sensor_len; 162 163 char sc_rev; 164 int8_t sc_numsensors; 165 uint32_t sc_family; 166 int32_t sc_adjustment; 167 }; 168 169 170 static int amdtemp_match(device_t, cfdata_t, void *); 171 static void amdtemp_attach(device_t, device_t, void *); 172 static int amdtemp_detach(device_t, int); 173 174 static void amdtemp_k8_init(struct amdtemp_softc *, pcireg_t); 175 static void amdtemp_k8_setup_sensors(struct amdtemp_softc *, int); 176 static void amdtemp_k8_refresh(struct sysmon_envsys *, envsys_data_t *); 177 178 static void amdtemp_family10_init(struct amdtemp_softc *); 179 static void amdtemp_family10_setup_sensors(struct amdtemp_softc *, int); 180 static void amdtemp_family10_refresh(struct sysmon_envsys *, envsys_data_t *); 181 182 CFATTACH_DECL_NEW(amdtemp, sizeof(struct amdtemp_softc), 183 amdtemp_match, amdtemp_attach, amdtemp_detach, NULL); 184 185 static int 186 amdtemp_match(device_t parent, cfdata_t match, void *aux) 187 { 188 struct pci_attach_args *pa = aux; 189 pcireg_t cpu_signature; 190 uint32_t family; 191 192 KASSERT(PCI_VENDOR(pa->pa_id) == PCI_VENDOR_AMD); 193 194 cpu_signature = pci_conf_read(pa->pa_pc, 195 pa->pa_tag, CPUID_FAMILY_MODEL_R); 196 197 /* This CPUID northbridge register has been introduced 198 * in Revision F */ 199 if (cpu_signature == 0x0) 200 return 0; 201 202 family = CPUID2FAMILY(cpu_signature); 203 if (family == 0xf) 204 family += CPUID2EXTFAMILY(cpu_signature); 205 206 /* Errata #319: This has been fixed in Revision C2. */ 207 if (family == 0x10) { 208 if (CPUID2MODEL(cpu_signature) < 4) 209 return 0; 210 if (CPUID2MODEL(cpu_signature) == 4 211 && CPUID2STEPPING(cpu_signature) < 2) 212 return 0; 213 } 214 215 216 /* Not yet supported CPUs */ 217 if (family > 0x15) 218 return 0; 219 220 return 1; 221 } 222 223 static void 224 amdtemp_attach(device_t parent, device_t self, void *aux) 225 { 226 struct amdtemp_softc *sc = device_private(self); 227 struct pci_attach_args *pa = aux; 228 pcireg_t cpu_signature; 229 int error; 230 uint8_t i; 231 232 aprint_naive("\n"); 233 aprint_normal(": AMD CPU Temperature Sensors"); 234 235 cpu_signature = pci_conf_read(pa->pa_pc, 236 pa->pa_tag, CPUID_FAMILY_MODEL_R); 237 238 /* If we hit this, then match routine is wrong. */ 239 KASSERT(cpu_signature != 0x0); 240 241 sc->sc_family = CPUID2FAMILY(cpu_signature); 242 sc->sc_family += CPUID2EXTFAMILY(cpu_signature); 243 244 KASSERT(sc->sc_family >= 0xf); 245 246 sc->sc_sme = NULL; 247 sc->sc_sensor = NULL; 248 249 sc->sc_pc = pa->pa_pc; 250 sc->sc_pcitag = pa->pa_tag; 251 sc->sc_adjustment = 0; 252 253 switch (sc->sc_family) { 254 case 0xf: /* AMD K8 NPT */ 255 amdtemp_k8_init(sc, cpu_signature); 256 break; 257 258 case 0x10: /* AMD Barcelona/Phenom */ 259 case 0x11: /* AMD Griffin */ 260 case 0x12: /* AMD Lynx/Sabine (Llano) */ 261 case 0x14: /* AMD Brazos (Ontario/Zacate/Desna) */ 262 case 0x15: 263 amdtemp_family10_init(sc); 264 break; 265 266 default: 267 aprint_normal(", family 0x%x not supported\n", 268 sc->sc_family); 269 return; 270 } 271 272 aprint_normal("\n"); 273 274 if (sc->sc_adjustment != 0) 275 aprint_debug_dev(self, "Workaround enabled\n"); 276 277 sc->sc_sme = sysmon_envsys_create(); 278 sc->sc_sensor_len = sizeof(envsys_data_t) * sc->sc_numsensors; 279 sc->sc_sensor = kmem_zalloc(sc->sc_sensor_len, KM_SLEEP); 280 281 if (sc->sc_sensor == NULL) 282 goto bad; 283 284 switch (sc->sc_family) { 285 case 0xf: 286 amdtemp_k8_setup_sensors(sc, device_unit(self)); 287 break; 288 case 0x10: 289 case 0x11: 290 case 0x12: 291 case 0x14: 292 case 0x15: 293 amdtemp_family10_setup_sensors(sc, device_unit(self)); 294 break; 295 } 296 297 /* 298 * Set properties in sensors. 299 */ 300 for (i = 0; i < sc->sc_numsensors; i++) { 301 if (sysmon_envsys_sensor_attach(sc->sc_sme, 302 &sc->sc_sensor[i])) 303 goto bad; 304 } 305 306 /* 307 * Register the sysmon_envsys device. 308 */ 309 sc->sc_sme->sme_name = device_xname(self); 310 sc->sc_sme->sme_cookie = sc; 311 312 switch (sc->sc_family) { 313 case 0xf: 314 sc->sc_sme->sme_refresh = amdtemp_k8_refresh; 315 break; 316 case 0x10: 317 case 0x11: 318 case 0x12: 319 case 0x14: 320 case 0x15: 321 sc->sc_sme->sme_refresh = amdtemp_family10_refresh; 322 break; 323 } 324 325 error = sysmon_envsys_register(sc->sc_sme); 326 if (error) { 327 aprint_error_dev(self, "unable to register with sysmon " 328 "(error=%d)\n", error); 329 goto bad; 330 } 331 332 (void)pmf_device_register(self, NULL, NULL); 333 334 return; 335 336 bad: 337 if (sc->sc_sme != NULL) { 338 sysmon_envsys_destroy(sc->sc_sme); 339 sc->sc_sme = NULL; 340 } 341 342 if (sc->sc_sensor != NULL) { 343 kmem_free(sc->sc_sensor, sc->sc_sensor_len); 344 sc->sc_sensor = NULL; 345 } 346 } 347 348 static int 349 amdtemp_detach(device_t self, int flags) 350 { 351 struct amdtemp_softc *sc = device_private(self); 352 353 pmf_device_deregister(self); 354 if (sc->sc_sme != NULL) 355 sysmon_envsys_unregister(sc->sc_sme); 356 357 if (sc->sc_sensor != NULL) 358 kmem_free(sc->sc_sensor, sc->sc_sensor_len); 359 360 return 0; 361 } 362 363 static void 364 amdtemp_k8_init(struct amdtemp_softc *sc, pcireg_t cpu_signature) 365 { 366 pcireg_t data; 367 uint32_t cmpcap; 368 uint8_t i, j; 369 370 aprint_normal(" (K8"); 371 372 for (i = 0; i < __arraycount(amdtemp_core) && sc->sc_rev == '\0'; i++) { 373 for (j = 0; amdtemp_core[i].cpu[j].cpuid != 0; j++) { 374 if ((cpu_signature & ~0xf) 375 != amdtemp_core[i].cpu[j].cpuid) 376 continue; 377 378 sc->sc_rev = amdtemp_core[i].rev[3]; 379 aprint_normal(": core rev %.4s%.1x", 380 amdtemp_core[i].rev, 381 CPUID2STEPPING(cpu_signature)); 382 383 switch (amdtemp_core[i].cpu[j].socket) { 384 case K8_SOCKET_AM2: 385 if (sc->sc_rev == 'G') 386 sc->sc_adjustment = 21000000; 387 aprint_normal(", socket AM2"); 388 break; 389 case K8_SOCKET_S1: 390 aprint_normal(", socket S1"); 391 break; 392 case K8_SOCKET_F: 393 aprint_normal(", socket F"); 394 break; 395 } 396 } 397 } 398 399 if (sc->sc_rev == '\0') { 400 /* CPUID Family Model Register was introduced in 401 * Revision F */ 402 sc->sc_rev = 'G'; /* newer than E, assume G */ 403 aprint_normal(": cpuid 0x%x", cpu_signature); 404 } 405 406 aprint_normal(")"); 407 408 data = pci_conf_read(sc->sc_pc, sc->sc_pcitag, NORTHBRIDGE_CAP_R); 409 cmpcap = (data >> 12) & 0x3; 410 411 sc->sc_numsensors = cmpcap ? 4 : 2; 412 } 413 414 415 static void 416 amdtemp_k8_setup_sensors(struct amdtemp_softc *sc, int dv_unit) 417 { 418 uint8_t i; 419 420 /* There are two sensors per CPU core. So we use the 421 * device unit as socket counter to correctly enumerate 422 * the CPUs on multi-socket machines. 423 */ 424 dv_unit *= (sc->sc_numsensors / 2); 425 for (i = 0; i < sc->sc_numsensors; i++) { 426 sc->sc_sensor[i].units = ENVSYS_STEMP; 427 sc->sc_sensor[i].state = ENVSYS_SVALID; 428 sc->sc_sensor[i].flags = ENVSYS_FHAS_ENTROPY; 429 430 snprintf(sc->sc_sensor[i].desc, sizeof(sc->sc_sensor[i].desc), 431 "CPU%u Sensor%u", dv_unit + (i / 2), i % 2); 432 } 433 } 434 435 436 static void 437 amdtemp_k8_refresh(struct sysmon_envsys *sme, envsys_data_t *edata) 438 { 439 struct amdtemp_softc *sc = sme->sme_cookie; 440 pcireg_t status, match, tmp; 441 uint32_t value; 442 443 status = pci_conf_read(sc->sc_pc, sc->sc_pcitag, THERMTRIP_STAT_R); 444 445 switch(edata->sensor) { /* sensor number */ 446 case 0: /* Core 0 Sensor 0 */ 447 K8_T_SEL_C0(status); 448 K8_T_SEL_S0(status); 449 break; 450 case 1: /* Core 0 Sensor 1 */ 451 K8_T_SEL_C0(status); 452 K8_T_SEL_S1(status); 453 break; 454 case 2: /* Core 1 Sensor 0 */ 455 K8_T_SEL_C1(status); 456 K8_T_SEL_S0(status); 457 break; 458 case 3: /* Core 1 Sensor 1 */ 459 K8_T_SEL_C1(status); 460 K8_T_SEL_S1(status); 461 break; 462 } 463 464 match = status & (K8_THERM_SENSE_CORE_SEL | K8_THERM_SENSE_SEL); 465 pci_conf_write(sc->sc_pc, sc->sc_pcitag, THERMTRIP_STAT_R, status); 466 status = pci_conf_read(sc->sc_pc, sc->sc_pcitag, THERMTRIP_STAT_R); 467 tmp = status & (K8_THERM_SENSE_CORE_SEL | K8_THERM_SENSE_SEL); 468 469 value = 0x3ff & (status >> 14); 470 if (sc->sc_rev != 'G') 471 value &= ~0x3; 472 473 edata->state = ENVSYS_SINVALID; 474 if ((tmp == match) && ((value & ~0x3) != 0)) { 475 edata->state = ENVSYS_SVALID; 476 edata->value_cur = (value * 250000 - 49000000) + 273150000 477 + sc->sc_adjustment; 478 } 479 } 480 481 482 static void 483 amdtemp_family10_init(struct amdtemp_softc *sc) 484 { 485 aprint_normal(" (Family%02xh)", sc->sc_family); 486 487 sc->sc_numsensors = 1; 488 } 489 490 static void 491 amdtemp_family10_setup_sensors(struct amdtemp_softc *sc, int dv_unit) 492 { 493 /* sanity check for future enhancements */ 494 KASSERT(sc->sc_numsensors == 1); 495 496 /* There's one sensor per memory controller (= socket) 497 * so we use the device unit as socket counter 498 * to correctly enumerate the CPUs 499 */ 500 sc->sc_sensor[0].units = ENVSYS_STEMP; 501 sc->sc_sensor[0].state = ENVSYS_SVALID; 502 sc->sc_sensor[0].flags = ENVSYS_FHAS_ENTROPY; 503 504 snprintf(sc->sc_sensor[0].desc, sizeof(sc->sc_sensor[0].desc), 505 "cpu%u temperature", dv_unit); 506 } 507 508 509 static void 510 amdtemp_family10_refresh(struct sysmon_envsys *sme, envsys_data_t *edata) 511 { 512 struct amdtemp_softc *sc = sme->sme_cookie; 513 pcireg_t status; 514 uint32_t value; 515 516 status = pci_conf_read(sc->sc_pc, 517 sc->sc_pcitag, F10_TEMPERATURE_CTL_R); 518 519 value = (status >> 21); 520 521 edata->state = ENVSYS_SVALID; 522 edata->value_cur = (value * 125000) + 273150000; /* From C to uK. */ 523 } 524 525 MODULE(MODULE_CLASS_DRIVER, amdtemp, NULL); 526 527 #ifdef _MODULE 528 #include "ioconf.c" 529 #endif 530 531 static int 532 amdtemp_modcmd(modcmd_t cmd, void *aux) 533 { 534 int error = 0; 535 536 switch (cmd) { 537 case MODULE_CMD_INIT: 538 #ifdef _MODULE 539 error = config_init_component(cfdriver_ioconf_amdtemp, 540 cfattach_ioconf_amdtemp, cfdata_ioconf_amdtemp); 541 #endif 542 return error; 543 case MODULE_CMD_FINI: 544 #ifdef _MODULE 545 error = config_fini_component(cfdriver_ioconf_amdtemp, 546 cfattach_ioconf_amdtemp, cfdata_ioconf_amdtemp); 547 #endif 548 return error; 549 default: 550 return ENOTTY; 551 } 552 } 553