1 /* $NetBSD: amdtemp.c,v 1.4 2008/05/20 14:45:22 cegger Exp $ */ 2 /* $OpenBSD: kate.c,v 1.2 2008/03/27 04:52:03 cnst Exp $ */ 3 4 /* 5 * Copyright (c) 2008 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Christoph Egger. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Copyright (c) 2008 Constantine A. Murenin <cnst+openbsd@bugmail.mojo.ru> 35 * 36 * Permission to use, copy, modify, and distribute this software for any 37 * purpose with or without fee is hereby granted, provided that the above 38 * copyright notice and this permission notice appear in all copies. 39 * 40 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 41 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 42 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 43 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 44 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 45 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 46 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 47 */ 48 49 50 #include <sys/cdefs.h> 51 __KERNEL_RCSID(0, "$NetBSD: amdtemp.c,v 1.4 2008/05/20 14:45:22 cegger Exp $ "); 52 53 #include <sys/param.h> 54 #include <sys/systm.h> 55 #include <sys/device.h> 56 #include <sys/kmem.h> 57 #include <dev/sysmon/sysmonvar.h> 58 59 #include <machine/bus.h> 60 #include <machine/cpu.h> 61 #include <machine/specialreg.h> 62 63 #include <dev/pci/pcireg.h> 64 #include <dev/pci/pcivar.h> 65 #include <dev/pci/pcidevs.h> 66 67 /* 68 * AMD K8: 69 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/32559.pdf 70 * Family10h: 71 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/31116.PDF 72 */ 73 74 /* AMD Proessors, Function 3 -- Miscellaneous Control 75 */ 76 77 /* Function 3 Registers */ 78 #define THERMTRIP_STAT_R 0xe4 79 #define NORTHBRIDGE_CAP_R 0xe8 80 #define CPUID_FAMILY_MODEL_R 0xfc 81 82 /* 83 * AMD NPT Family 0Fh Processors, Function 3 -- Miscellaneous Control 84 */ 85 86 /* Bits within Thermtrip Status Register */ 87 #define K8_THERM_SENSE_SEL (1 << 6) 88 #define K8_THERM_SENSE_CORE_SEL (1 << 2) 89 90 /* Flip core and sensor selection bits */ 91 #define K8_T_SEL_C0(v) (v |= K8_THERM_SENSE_CORE_SEL) 92 #define K8_T_SEL_C1(v) (v &= ~(K8_THERM_SENSE_CORE_SEL)) 93 #define K8_T_SEL_S0(v) (v &= ~(K8_THERM_SENSE_SEL)) 94 #define K8_T_SEL_S1(v) (v |= K8_THERM_SENSE_SEL) 95 96 97 98 /* 99 * AMD Family 10h Processorcs, Function 3 -- Miscellaneous Control 100 */ 101 102 /* Function 3 Registers */ 103 #define F10_TEMPERATURE_CTL_R 0xa4 104 105 /* Bits within Reported Temperature Control Register */ 106 #define F10_TEMP_CURTEMP (1 << 21) 107 108 /* 109 * Revision Guide for AMD NPT Family 0Fh Processors, 110 * Publication # 33610, Revision 3.30, February 2008 111 */ 112 static const struct { 113 const char rev[5]; 114 const pcireg_t cpuid[5]; 115 } amdtemp_core[] = { 116 { "BH-F", { 0x00040FB0, 0x00040F80, 0, 0, 0 } }, /* F2 */ 117 { "DH-F", { 0x00040FF0, 0x00050FF0, 0x00040FC0, 0, 0 } }, /* F2, F3 */ 118 { "JH-F", { 0x00040F10, 0x00040F30, 0x000C0F10, 0, 0 } }, /* F2, F3 */ 119 { "BH-G", { 0x00060FB0, 0x00060F80, 0, 0, 0 } }, /* G1, G2 */ 120 { "DH-G", { 0x00070FF0, 0x00060FF0, 121 0x00060FC0, 0x00070FC0, 0 } } /* G1, G2 */ 122 }; 123 124 125 struct amdtemp_softc { 126 pci_chipset_tag_t sc_pc; 127 pcitag_t sc_pcitag; 128 129 struct sysmon_envsys *sc_sme; 130 envsys_data_t *sc_sensor; 131 132 char sc_rev; 133 int8_t sc_numsensors; 134 uint32_t sc_family; 135 }; 136 137 138 static int amdtemp_match(device_t, cfdata_t, void *); 139 static void amdtemp_attach(device_t, device_t, void *); 140 141 static void amdtemp_k8_init(struct amdtemp_softc *, pcireg_t); 142 static void amdtemp_k8_setup_sensors(struct amdtemp_softc *, int); 143 static void amdtemp_k8_refresh(struct sysmon_envsys *, envsys_data_t *); 144 145 static void amdtemp_family10_init(struct amdtemp_softc *); 146 static void amdtemp_family10_setup_sensors(struct amdtemp_softc *, int); 147 static void amdtemp_family10_refresh(struct sysmon_envsys *, envsys_data_t *); 148 149 CFATTACH_DECL_NEW(amdtemp, sizeof(struct amdtemp_softc), 150 amdtemp_match, amdtemp_attach, NULL, NULL); 151 152 static int 153 amdtemp_match(device_t parent, cfdata_t match, void *aux) 154 { 155 struct pci_attach_args *pa = aux; 156 pcireg_t cpu_signature; 157 uint32_t family; 158 159 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_AMD) 160 return 0; 161 162 switch (PCI_PRODUCT(pa->pa_id)) { 163 case PCI_PRODUCT_AMD_AMD64_MISC: 164 case PCI_PRODUCT_AMD_AMD64_F10_MISC: 165 case PCI_PRODUCT_AMD_AMD64_F11_MISC: 166 break; 167 default: 168 return 0; 169 } 170 171 cpu_signature = pci_conf_read(pa->pa_pc, pa->pa_tag, 172 CPUID_FAMILY_MODEL_R); 173 174 /* This CPUID northbridge register has been introduced 175 * in Revision F */ 176 if (cpu_signature == 0x0) 177 return 0; 178 179 family = CPUID2FAMILY(cpu_signature); 180 if (family == 0xf) 181 family += CPUID2EXTFAMILY(cpu_signature); 182 183 /* Not yet supported CPUs */ 184 if (family >= 0x12) 185 return 0; 186 187 return 2; /* supercede pchb(4) */ 188 } 189 190 static void 191 amdtemp_attach(device_t parent, device_t self, void *aux) 192 { 193 struct amdtemp_softc *sc = device_private(self); 194 struct pci_attach_args *pa = aux; 195 pcireg_t cpu_signature; 196 size_t len; 197 int error; 198 uint8_t i; 199 200 aprint_naive("\n"); 201 aprint_normal("\n"); 202 203 aprint_normal_dev(self, "AMD CPU Temperature Sensors"); 204 205 cpu_signature = pci_conf_read(pa->pa_pc, pa->pa_tag, 206 CPUID_FAMILY_MODEL_R); 207 208 /* If we hit this, then match routine is wrong. */ 209 KASSERT(cpu_signature != 0x0); 210 211 sc->sc_family = CPUID2FAMILY(cpu_signature) 212 + CPUID2EXTFAMILY(cpu_signature); 213 KASSERT(sc->sc_family >= 0xf); 214 215 sc->sc_pc = pa->pa_pc; 216 sc->sc_pcitag = pa->pa_tag; 217 218 switch (sc->sc_family) { 219 case 0xf: /* AMD K8 NPT */ 220 amdtemp_k8_init(sc, cpu_signature); 221 break; 222 223 case 0x10: /* AMD Barcelona/Phenom */ 224 case 0x11: /* AMD Griffin */ 225 amdtemp_family10_init(sc); 226 break; 227 228 default: 229 /* Not supported */ 230 return; 231 } 232 233 aprint_normal("\n"); 234 235 sc->sc_sme = sysmon_envsys_create(); 236 len = sizeof(envsys_data_t) * sc->sc_numsensors; 237 sc->sc_sensor = kmem_zalloc(len, KM_NOSLEEP); 238 if (!sc->sc_sensor) 239 goto bad2; 240 241 switch (sc->sc_family) { 242 case 0xf: 243 amdtemp_k8_setup_sensors(sc, device_unit(self)); 244 break; 245 case 0x10: 246 case 0x11: 247 amdtemp_family10_setup_sensors(sc, device_unit(self)); 248 break; 249 } 250 251 /* 252 * Set properties in sensors. 253 */ 254 for (i = 0; i < sc->sc_numsensors; i++) { 255 if (sysmon_envsys_sensor_attach(sc->sc_sme, 256 &sc->sc_sensor[i])) 257 goto bad; 258 } 259 260 /* 261 * Register the sysmon_envsys device. 262 */ 263 sc->sc_sme->sme_name = device_xname(self); 264 sc->sc_sme->sme_cookie = sc; 265 266 switch (sc->sc_family) { 267 case 0xf: 268 sc->sc_sme->sme_refresh = amdtemp_k8_refresh; 269 break; 270 case 0x10: 271 case 0x11: 272 sc->sc_sme->sme_refresh = amdtemp_family10_refresh; 273 break; 274 } 275 276 error = sysmon_envsys_register(sc->sc_sme); 277 if (error) { 278 aprint_error_dev(self, "unable to register with sysmon " 279 "(error=%d)\n", error); 280 goto bad; 281 } 282 283 if (!pmf_device_register(self, NULL, NULL)) 284 aprint_error_dev(self, "couldn't establish power handler\n"); 285 286 return; 287 288 bad: 289 kmem_free(sc->sc_sensor, len); 290 bad2: 291 sysmon_envsys_destroy(sc->sc_sme); 292 } 293 294 static void 295 amdtemp_k8_init(struct amdtemp_softc *sc, pcireg_t cpu_signature) 296 { 297 pcireg_t data; 298 uint32_t cmpcap; 299 uint8_t i, j; 300 301 aprint_normal(" (K8"); 302 303 for (i = 0; i < __arraycount(amdtemp_core) && sc->sc_rev == '\0'; i++) { 304 for (j = 0; amdtemp_core[i].cpuid[j] != 0; j++) { 305 if ((cpu_signature & ~0xf) 306 == amdtemp_core[i].cpuid[j]) 307 { 308 sc->sc_rev = amdtemp_core[i].rev[3]; 309 aprint_normal(": core rev %.4s%.1x", 310 amdtemp_core[i].rev, 311 CPUID2STEPPING(cpu_signature)); 312 } 313 } 314 } 315 316 if (sc->sc_rev == '\0') { 317 /* CPUID Family Model Register was introduced in 318 * Revision F */ 319 sc->sc_rev = 'G'; /* newer than E, assume G */ 320 aprint_normal(": cpuid 0x%x", cpu_signature); 321 } 322 323 aprint_normal(")"); 324 325 data = pci_conf_read(sc->sc_pc, sc->sc_pcitag, NORTHBRIDGE_CAP_R); 326 cmpcap = (data >> 12) & 0x3; 327 328 sc->sc_numsensors = cmpcap ? 4 : 2; 329 } 330 331 332 static void 333 amdtemp_k8_setup_sensors(struct amdtemp_softc *sc, int dv_unit) 334 { 335 uint8_t i; 336 337 /* There are two sensors per CPU core. So we use the 338 * device unit as socket counter to correctly enumerate 339 * the CPUs on multi-socket machines. 340 */ 341 dv_unit *= (sc->sc_numsensors / 2); 342 for (i = 0; i < sc->sc_numsensors; i++) { 343 sc->sc_sensor[i].units = ENVSYS_STEMP; 344 sc->sc_sensor[i].state = ENVSYS_SVALID; 345 346 snprintf(sc->sc_sensor[i].desc, sizeof(sc->sc_sensor[i].desc), 347 "CPU%u Sensor%u", dv_unit + (i / 2), i % 2); 348 } 349 } 350 351 352 static void 353 amdtemp_k8_refresh(struct sysmon_envsys *sme, envsys_data_t *edata) 354 { 355 struct amdtemp_softc *sc = sme->sme_cookie; 356 pcireg_t status, match, tmp; 357 uint32_t value; 358 359 status = pci_conf_read(sc->sc_pc, sc->sc_pcitag, THERMTRIP_STAT_R); 360 361 switch(edata->sensor) { /* sensor number */ 362 case 0: /* Core 0 Sensor 0 */ 363 K8_T_SEL_C0(status); 364 K8_T_SEL_S0(status); 365 break; 366 case 1: /* Core 0 Sensor 1 */ 367 K8_T_SEL_C0(status); 368 K8_T_SEL_S1(status); 369 break; 370 case 2: /* Core 1 Sensor 0 */ 371 K8_T_SEL_C1(status); 372 K8_T_SEL_S0(status); 373 break; 374 case 3: /* Core 1 Sensor 1 */ 375 K8_T_SEL_C1(status); 376 K8_T_SEL_S1(status); 377 break; 378 } 379 380 match = status & (K8_THERM_SENSE_CORE_SEL | K8_THERM_SENSE_SEL); 381 pci_conf_write(sc->sc_pc, sc->sc_pcitag, THERMTRIP_STAT_R, status); 382 status = pci_conf_read(sc->sc_pc, sc->sc_pcitag, THERMTRIP_STAT_R); 383 tmp = status & (K8_THERM_SENSE_CORE_SEL | K8_THERM_SENSE_SEL); 384 385 value = 0x3ff & (status >> 14); 386 if (sc->sc_rev != 'G') 387 value &= ~0x3; 388 389 edata->state = ENVSYS_SINVALID; 390 if ((tmp == match) && ((value & ~0x3) != 0)) { 391 edata->state = ENVSYS_SVALID; 392 edata->value_cur = (value * 250000 - 49000000) + 273150000; 393 } 394 } 395 396 397 static void 398 amdtemp_family10_init(struct amdtemp_softc *sc) 399 { 400 aprint_normal(" (Family10h / Family11h)"); 401 402 sc->sc_numsensors = 1; 403 } 404 405 static void 406 amdtemp_family10_setup_sensors(struct amdtemp_softc *sc, int dv_unit) 407 { 408 /* sanity check for future enhancements */ 409 KASSERT(sc->sc_numsensors == 1); 410 411 /* There's one sensor per memory controller (= socket) 412 * so we use the device unit as socket counter 413 * to correctly enumerate the CPUs 414 */ 415 sc->sc_sensor[0].units = ENVSYS_STEMP; 416 sc->sc_sensor[0].state = ENVSYS_SVALID; 417 418 snprintf(sc->sc_sensor[0].desc, sizeof(sc->sc_sensor[0].desc), 419 "CPU%u Sensor0", dv_unit); 420 } 421 422 423 static void 424 amdtemp_family10_refresh(struct sysmon_envsys *sme, envsys_data_t *edata) 425 { 426 struct amdtemp_softc *sc = sme->sme_cookie; 427 pcireg_t status; 428 uint32_t value; 429 430 status = pci_conf_read(sc->sc_pc, sc->sc_pcitag, F10_TEMPERATURE_CTL_R); 431 432 value = (status >> 21); 433 434 edata->state = ENVSYS_SVALID; 435 /* envsys(4) wants uK... convert from Celsius. */ 436 edata->value_cur = (value * 125000) + 273150000; 437 } 438