xref: /netbsd-src/sys/arch/x86/isa/isa_machdep.c (revision 7fa608457b817eca6e0977b37f758ae064f3c99c)
1 /*	$NetBSD: isa_machdep.c,v 1.18 2007/10/17 19:58:15 garbled Exp $	*/
2 
3 /*-
4  * Copyright (c) 1996, 1997, 1998 The NetBSD Foundation, Inc.
5  * All rights reserved.
6  *
7  * This code is derived from software contributed to The NetBSD Foundation
8  * by Charles M. Hannum and by Jason R. Thorpe of the Numerical Aerospace
9  * Simulation Facility, NASA Ames Research Center.
10  *
11  * Redistribution and use in source and binary forms, with or without
12  * modification, are permitted provided that the following conditions
13  * are met:
14  * 1. Redistributions of source code must retain the above copyright
15  *    notice, this list of conditions and the following disclaimer.
16  * 2. Redistributions in binary form must reproduce the above copyright
17  *    notice, this list of conditions and the following disclaimer in the
18  *    documentation and/or other materials provided with the distribution.
19  * 3. All advertising materials mentioning features or use of this software
20  *    must display the following acknowledgement:
21  *	This product includes software developed by the NetBSD
22  *	Foundation, Inc. and its contributors.
23  * 4. Neither the name of The NetBSD Foundation nor the names of its
24  *    contributors may be used to endorse or promote products derived
25  *    from this software without specific prior written permission.
26  *
27  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
28  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
29  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
30  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
31  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
32  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
33  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
34  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
35  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
36  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37  * POSSIBILITY OF SUCH DAMAGE.
38  */
39 
40 /*-
41  * Copyright (c) 1991 The Regents of the University of California.
42  * All rights reserved.
43  *
44  * This code is derived from software contributed to Berkeley by
45  * William Jolitz.
46  *
47  * Redistribution and use in source and binary forms, with or without
48  * modification, are permitted provided that the following conditions
49  * are met:
50  * 1. Redistributions of source code must retain the above copyright
51  *    notice, this list of conditions and the following disclaimer.
52  * 2. Redistributions in binary form must reproduce the above copyright
53  *    notice, this list of conditions and the following disclaimer in the
54  *    documentation and/or other materials provided with the distribution.
55  * 3. Neither the name of the University nor the names of its contributors
56  *    may be used to endorse or promote products derived from this software
57  *    without specific prior written permission.
58  *
59  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
60  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
61  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
62  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
63  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
64  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
65  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
66  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
67  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
68  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
69  * SUCH DAMAGE.
70  *
71  *	@(#)isa.c	7.2 (Berkeley) 5/13/91
72  */
73 
74 #include <sys/cdefs.h>
75 __KERNEL_RCSID(0, "$NetBSD: isa_machdep.c,v 1.18 2007/10/17 19:58:15 garbled Exp $");
76 
77 #include <sys/param.h>
78 #include <sys/systm.h>
79 #include <sys/kernel.h>
80 #include <sys/syslog.h>
81 #include <sys/device.h>
82 #include <sys/malloc.h>
83 #include <sys/proc.h>
84 #include <sys/mbuf.h>
85 
86 #include <machine/bus.h>
87 #include <machine/bus_private.h>
88 
89 #include <machine/pio.h>
90 #include <machine/cpufunc.h>
91 
92 #include <dev/isa/isareg.h>
93 #include <dev/isa/isavar.h>
94 
95 #include <uvm/uvm_extern.h>
96 
97 #include "ioapic.h"
98 
99 #if NIOAPIC > 0
100 #include <machine/i82093var.h>
101 #include <machine/mpbiosvar.h>
102 #endif
103 
104 static int _isa_dma_may_bounce(bus_dma_tag_t, bus_dmamap_t, int, int *);
105 
106 struct x86_bus_dma_tag isa_bus_dma_tag = {
107 	0,				/* _tag_needs_free */
108 	ISA_DMA_BOUNCE_THRESHOLD,	/* _bounce_thresh */
109 	0,				/* _bounce_alloc_lo */
110 	ISA_DMA_BOUNCE_THRESHOLD,	/* _bounce_alloc_hi */
111 	_isa_dma_may_bounce,
112 	_bus_dmamap_create,
113 	_bus_dmamap_destroy,
114 	_bus_dmamap_load,
115 	_bus_dmamap_load_mbuf,
116 	_bus_dmamap_load_uio,
117 	_bus_dmamap_load_raw,
118 	_bus_dmamap_unload,
119 	_bus_dmamap_sync,
120 	_bus_dmamem_alloc,
121 	_bus_dmamem_free,
122 	_bus_dmamem_map,
123 	_bus_dmamem_unmap,
124 	_bus_dmamem_mmap,
125 	_bus_dmatag_subregion,
126 	_bus_dmatag_destroy,
127 };
128 
129 #define	IDTVEC(name)	__CONCAT(X,name)
130 typedef void (vector) __P((void));
131 extern vector *IDTVEC(intr)[];
132 
133 #define	LEGAL_IRQ(x)	((x) >= 0 && (x) < NUM_LEGACY_IRQS && (x) != 2)
134 
135 int
136 isa_intr_alloc(isa_chipset_tag_t ic, int mask, int type, int *irq)
137 {
138 	extern kmutex_t x86_intr_lock;
139 	int i, tmp, bestirq, count;
140 	struct intrhand **p, *q;
141 	struct intrsource *isp;
142 	struct cpu_info *ci;
143 
144 	if (type == IST_NONE)
145 		panic("intr_alloc: bogus type");
146 
147 	ci = &cpu_info_primary;
148 
149 	bestirq = -1;
150 	count = -1;
151 
152 	/* some interrupts should never be dynamically allocated */
153 	mask &= 0xdef8;
154 
155 	/*
156 	 * XXX some interrupts will be used later (6 for fdc, 12 for pms).
157 	 * the right answer is to do "breadth-first" searching of devices.
158 	 */
159 	mask &= 0xefbf;
160 
161 	mutex_enter(&x86_intr_lock);
162 
163 	for (i = 0; i < NUM_LEGACY_IRQS; i++) {
164 		if (LEGAL_IRQ(i) == 0 || (mask & (1<<i)) == 0)
165 			continue;
166 		isp = ci->ci_isources[i];
167 		if (isp == NULL) {
168 			/*
169 			 * if nothing's using the irq, just return it
170 			 */
171 			*irq = i;
172 			mutex_exit(&x86_intr_lock);
173 			return (0);
174 		}
175 
176 		switch(isp->is_type) {
177 		case IST_EDGE:
178 		case IST_LEVEL:
179 			if (type != isp->is_type)
180 				continue;
181 			/*
182 			 * if the irq is shareable, count the number of other
183 			 * handlers, and if it's smaller than the last irq like
184 			 * this, remember it
185 			 *
186 			 * XXX We should probably also consider the
187 			 * interrupt level and stick IPL_TTY with other
188 			 * IPL_TTY, etc.
189 			 */
190 			for (p = &isp->is_handlers, tmp = 0; (q = *p) != NULL;
191 			     p = &q->ih_next, tmp++)
192 				;
193 			if ((bestirq == -1) || (count > tmp)) {
194 				bestirq = i;
195 				count = tmp;
196 			}
197 			break;
198 
199 		case IST_PULSE:
200 			/* this just isn't shareable */
201 			continue;
202 		}
203 	}
204 
205 	mutex_exit(&x86_intr_lock);
206 
207 	if (bestirq == -1)
208 		return (1);
209 
210 	*irq = bestirq;
211 
212 	return (0);
213 }
214 
215 const struct evcnt *
216 isa_intr_evcnt(isa_chipset_tag_t ic, int irq)
217 {
218 
219 	/* XXX for now, no evcnt parent reported */
220 	return NULL;
221 }
222 
223 void *
224 isa_intr_establish(
225     isa_chipset_tag_t ic,
226     int irq,
227     int type,
228     int level,
229     int (*ih_fun)(void *),
230     void *ih_arg
231 )
232 {
233 	struct pic *pic;
234 	int pin;
235 #if NIOAPIC > 0
236 	int mpih;
237 #endif
238 
239 	pin = irq;
240 	pic = &i8259_pic;
241 
242 #if NIOAPIC > 0
243 	if (mp_busses != NULL) {
244 		if (intr_find_mpmapping(mp_isa_bus, irq, &mpih) == 0 ||
245 		    intr_find_mpmapping(mp_eisa_bus, irq, &mpih) == 0) {
246 			if (!APIC_IRQ_ISLEGACY(mpih)) {
247 				pin = APIC_IRQ_PIN(mpih);
248 				pic = (struct pic *)
249 				    ioapic_find(APIC_IRQ_APIC(mpih));
250 				if (pic == NULL) {
251 					printf("isa_intr_establish: "
252 					       "unknown apic %d\n",
253 					    APIC_IRQ_APIC(mpih));
254 					return NULL;
255 				}
256 			}
257 		} else
258 			printf("isa_intr_establish: no MP mapping found\n");
259 	}
260 #endif
261 	return intr_establish(irq, pic, pin, type, level, ih_fun, ih_arg);
262 }
263 
264 /*
265  * Deregister an interrupt handler.
266  */
267 void
268 isa_intr_disestablish(isa_chipset_tag_t ic, void *arg)
269 {
270 	struct intrhand *ih = arg;
271 
272 	if (!LEGAL_IRQ(ih->ih_pin))
273 		panic("intr_disestablish: bogus irq");
274 
275 	intr_disestablish(ih);
276 }
277 
278 void
279 isa_attach_hook(struct device *parent, struct device *self,
280     struct isabus_attach_args *iba)
281 {
282 	extern struct x86_isa_chipset x86_isa_chipset;
283 	extern int isa_has_been_seen;
284 
285 	/*
286 	 * Notify others that might need to know that the ISA bus
287 	 * has now been attached.
288 	 */
289 	if (isa_has_been_seen)
290 		panic("isaattach: ISA bus already seen!");
291 	isa_has_been_seen = 1;
292 
293 	/*
294 	 * Since we can only have one ISA bus, we just use a single
295 	 * statically allocated ISA chipset structure.  Pass it up
296 	 * now.
297 	 */
298 	iba->iba_ic = &x86_isa_chipset;
299 }
300 
301 int
302 isa_mem_alloc(t, size, align, boundary, flags, addrp, bshp)
303 	bus_space_tag_t t;
304 	bus_size_t size, align;
305 	bus_addr_t boundary;
306 	int flags;
307 	bus_addr_t *addrp;
308 	bus_space_handle_t *bshp;
309 {
310 
311 	/*
312 	 * Allocate physical address space in the ISA hole.
313 	 */
314 	return (bus_space_alloc(t, IOM_BEGIN, IOM_END - 1, size, align,
315 	    boundary, flags, addrp, bshp));
316 }
317 
318 void
319 isa_mem_free(t, bsh, size)
320 	bus_space_tag_t t;
321 	bus_space_handle_t bsh;
322 	bus_size_t size;
323 {
324 
325 	bus_space_free(t, bsh, size);
326 }
327 
328 /*
329  * ISA only has 24-bits of address space.  This means
330  * we can't DMA to pages over 16M.  In order to DMA to
331  * arbitrary buffers, we use "bounce buffers" - pages
332  * in memory below the 16M boundary.  On DMA reads,
333  * DMA happens to the bounce buffers, and is copied into
334  * the caller's buffer.  On writes, data is copied into
335  * but bounce buffer, and the DMA happens from those
336  * pages.  To software using the DMA mapping interface,
337  * this looks simply like a data cache.
338  *
339  * If we have more than 16M of RAM in the system, we may
340  * need bounce buffers.  We check and remember that here.
341  *
342  * There are exceptions, however.  VLB devices can do
343  * 32-bit DMA, and indicate that here.
344  *
345  * ...or, there is an opposite case.  The most segments
346  * a transfer will require is (maxxfer / PAGE_SIZE) + 1.  If
347  * the caller can't handle that many segments (e.g. the
348  * ISA DMA controller), we may have to bounce it as well.
349  */
350 static int
351 _isa_dma_may_bounce(bus_dma_tag_t t, bus_dmamap_t map, int flags,
352     int *cookieflagsp)
353 {
354 	if ((flags & ISABUS_DMA_32BIT) != 0)
355 		map->_dm_bounce_thresh = 0;
356 
357 	if (((map->_dm_size / PAGE_SIZE) + 1) > map->_dm_segcnt)
358 		*cookieflagsp |= X86_DMA_MIGHT_NEED_BOUNCE;
359 	return 0;
360 }
361