1 /* $NetBSD: intr.h,v 1.12 2004/03/04 19:10:10 dbj Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum, and by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #ifndef _X86_INTR_H_ 40 #define _X86_INTR_H_ 41 42 #ifdef _KERNEL_OPT 43 #include "opt_multiprocessor.h" 44 #endif 45 46 #include <machine/intrdefs.h> 47 48 #ifndef _LOCORE 49 #include <machine/cpu.h> 50 #include <machine/pic.h> 51 52 /* 53 * Struct describing an interrupt source for a CPU. struct cpu_info 54 * has an array of MAX_INTR_SOURCES of these. The index in the array 55 * is equal to the stub number of the stubcode as present in vector.s 56 * 57 * The primary CPU's array of interrupt sources has its first 16 58 * entries reserved for legacy ISA irq handlers. This means that 59 * they have a 1:1 mapping for arrayindex:irq_num. This is not 60 * true for interrupts that come in through IO APICs, to find 61 * their source, go through ci->ci_isources[index].is_pic 62 * 63 * It's possible to always maintain a 1:1 mapping, but that means 64 * limiting the total number of interrupt sources to MAX_INTR_SOURCES 65 * (32), instead of 32 per CPU. It also would mean that having multiple 66 * IO APICs which deliver interrupts from an equal pin number would 67 * overlap if they were to be sent to the same CPU. 68 */ 69 70 struct intrstub { 71 void *ist_entry; 72 void *ist_recurse; 73 void *ist_resume; 74 }; 75 76 struct intrsource { 77 int is_maxlevel; /* max. IPL for this source */ 78 int is_pin; /* IRQ for legacy; pin for IO APIC */ 79 struct intrhand *is_handlers; /* handler chain */ 80 struct pic *is_pic; /* originating PIC */ 81 void *is_recurse; /* entry for spllower */ 82 void *is_resume; /* entry for doreti */ 83 struct evcnt is_evcnt; /* interrupt counter */ 84 char is_evname[32]; /* event counter name */ 85 int is_flags; /* see below */ 86 int is_type; /* level, edge */ 87 int is_idtvec; 88 int is_minlevel; 89 }; 90 91 #define IS_LEGACY 0x0001 /* legacy ISA irq source */ 92 #define IS_IPI 0x0002 93 #define IS_LOG 0x0004 94 95 96 /* 97 * Interrupt handler chains. *_intr_establish() insert a handler into 98 * the list. The handler is called with its (single) argument. 99 */ 100 101 struct intrhand { 102 int (*ih_fun)(void *); 103 void *ih_arg; 104 int ih_level; 105 struct intrhand *ih_next; 106 int ih_pin; 107 int ih_slot; 108 struct cpu_info *ih_cpu; 109 }; 110 111 #define IMASK(ci,level) (ci)->ci_imask[(level)] 112 #define IUNMASK(ci,level) (ci)->ci_iunmask[(level)] 113 114 extern void Xspllower(int); 115 116 static __inline int splraise(int); 117 static __inline void spllower(int); 118 static __inline void softintr(int); 119 120 /* 121 * Convert spl level to local APIC level 122 */ 123 #define APIC_LEVEL(l) ((l) << 4) 124 125 /* 126 * compiler barrier: prevent reordering of instructions. 127 * XXX something similar will move to <sys/cdefs.h> 128 * or thereabouts. 129 * This prevents the compiler from reordering code around 130 * this "instruction", acting as a sequence point for code generation. 131 */ 132 133 #define __splbarrier() __asm __volatile("":::"memory") 134 135 /* 136 * Add a mask to cpl, and return the old value of cpl. 137 */ 138 static __inline int 139 splraise(int nlevel) 140 { 141 int olevel; 142 struct cpu_info *ci = curcpu(); 143 144 olevel = ci->ci_ilevel; 145 if (nlevel > olevel) 146 ci->ci_ilevel = nlevel; 147 __splbarrier(); 148 return (olevel); 149 } 150 151 /* 152 * Restore a value to cpl (unmasking interrupts). If any unmasked 153 * interrupts are pending, call Xspllower() to process them. 154 */ 155 static __inline void 156 spllower(int nlevel) 157 { 158 struct cpu_info *ci = curcpu(); 159 160 __splbarrier(); 161 /* 162 * Since this should only lower the interrupt level, 163 * the XOR below should only show interrupts that 164 * are being unmasked. 165 */ 166 ci->ci_ilevel = nlevel; 167 if (ci->ci_ipending & IUNMASK(ci,nlevel)) 168 Xspllower(nlevel); 169 } 170 171 /* 172 * Hardware interrupt masks 173 */ 174 #define splbio() splraise(IPL_BIO) 175 #define splnet() splraise(IPL_NET) 176 #define spltty() splraise(IPL_TTY) 177 #define splaudio() splraise(IPL_AUDIO) 178 #define splclock() splraise(IPL_CLOCK) 179 #define splstatclock() splclock() 180 #define splserial() splraise(IPL_SERIAL) 181 #define splipi() splraise(IPL_IPI) 182 183 #define spllpt() spltty() 184 185 #define SPL_ASSERT_BELOW(x) KDASSERT(curcpu()->ci_ilevel < (x)) 186 #define spllpt() spltty() 187 188 /* 189 * Software interrupt masks 190 * 191 * NOTE: spllowersoftclock() is used by hardclock() to lower the priority from 192 * clock to softclock before it calls softclock(). 193 */ 194 #define spllowersoftclock() spllower(IPL_SOFTCLOCK) 195 196 #define splsoftclock() splraise(IPL_SOFTCLOCK) 197 #define splsoftnet() splraise(IPL_SOFTNET) 198 #define splsoftserial() splraise(IPL_SOFTSERIAL) 199 200 /* 201 * Miscellaneous 202 */ 203 #define splvm() splraise(IPL_VM) 204 #define splhigh() splraise(IPL_HIGH) 205 #define spl0() spllower(IPL_NONE) 206 #define splsched() splraise(IPL_SCHED) 207 #define spllock() splhigh() 208 #define splx(x) spllower(x) 209 210 /* 211 * Software interrupt registration 212 * 213 * We hand-code this to ensure that it's atomic. 214 * 215 * XXX always scheduled on the current CPU. 216 */ 217 static __inline void 218 softintr(int sir) 219 { 220 struct cpu_info *ci = curcpu(); 221 222 __asm __volatile("lock ; orl %1, %0" : 223 "=m"(ci->ci_ipending) : "ir" (1 << sir)); 224 } 225 226 /* 227 * XXX 228 */ 229 #define setsoftnet() softintr(SIR_NET) 230 231 /* 232 * Stub declarations. 233 */ 234 235 extern void Xsoftclock(void); 236 extern void Xsoftnet(void); 237 extern void Xsoftserial(void); 238 239 extern struct intrstub i8259_stubs[]; 240 extern struct intrstub ioapic_edge_stubs[]; 241 extern struct intrstub ioapic_level_stubs[]; 242 243 struct cpu_info; 244 245 extern char idt_allocmap[]; 246 247 struct pcibus_attach_args; 248 249 void intr_default_setup(void); 250 int x86_nmi(void); 251 void intr_calculatemasks(struct cpu_info *); 252 int intr_allocate_slot_cpu(struct cpu_info *, struct pic *, int, int *); 253 int intr_allocate_slot(struct pic *, int, int, int, struct cpu_info **, int *, 254 int *); 255 void *intr_establish(int, struct pic *, int, int, int, int (*)(void *), void *); 256 void intr_disestablish(struct intrhand *); 257 void intr_add_pcibus(struct pcibus_attach_args *); 258 const char *intr_string(int); 259 void cpu_intr_init(struct cpu_info *); 260 int intr_find_mpmapping(int, int, int *); 261 #ifdef INTRDEBUG 262 void intr_printconfig(void); 263 #endif 264 265 #ifdef MULTIPROCESSOR 266 int x86_send_ipi(struct cpu_info *, int); 267 void x86_broadcast_ipi(int); 268 void x86_multicast_ipi(int, int); 269 void x86_ipi_handler(void); 270 void x86_intlock(struct intrframe *); 271 void x86_intunlock(struct intrframe *); 272 void x86_softintlock(void); 273 void x86_softintunlock(void); 274 275 extern void (*ipifunc[X86_NIPI])(struct cpu_info *); 276 #endif 277 278 #endif /* !_LOCORE */ 279 280 /* 281 * Generic software interrupt support. 282 */ 283 284 #define X86_SOFTINTR_SOFTCLOCK 0 285 #define X86_SOFTINTR_SOFTNET 1 286 #define X86_SOFTINTR_SOFTSERIAL 2 287 #define X86_NSOFTINTR 3 288 289 #ifndef _LOCORE 290 #include <sys/queue.h> 291 292 struct x86_soft_intrhand { 293 TAILQ_ENTRY(x86_soft_intrhand) 294 sih_q; 295 struct x86_soft_intr *sih_intrhead; 296 void (*sih_fn)(void *); 297 void *sih_arg; 298 int sih_pending; 299 }; 300 301 struct x86_soft_intr { 302 TAILQ_HEAD(, x86_soft_intrhand) 303 softintr_q; 304 int softintr_ssir; 305 struct simplelock softintr_slock; 306 }; 307 308 #define x86_softintr_lock(si, s) \ 309 do { \ 310 (s) = splhigh(); \ 311 simple_lock(&si->softintr_slock); \ 312 } while (/*CONSTCOND*/ 0) 313 314 #define x86_softintr_unlock(si, s) \ 315 do { \ 316 simple_unlock(&si->softintr_slock); \ 317 splx((s)); \ 318 } while (/*CONSTCOND*/ 0) 319 320 void *softintr_establish(int, void (*)(void *), void *); 321 void softintr_disestablish(void *); 322 void softintr_init(void); 323 void softintr_dispatch(int); 324 325 #define softintr_schedule(arg) \ 326 do { \ 327 struct x86_soft_intrhand *__sih = (arg); \ 328 struct x86_soft_intr *__si = __sih->sih_intrhead; \ 329 int __s; \ 330 \ 331 x86_softintr_lock(__si, __s); \ 332 if (__sih->sih_pending == 0) { \ 333 TAILQ_INSERT_TAIL(&__si->softintr_q, __sih, sih_q); \ 334 __sih->sih_pending = 1; \ 335 softintr(__si->softintr_ssir); \ 336 } \ 337 x86_softintr_unlock(__si, __s); \ 338 } while (/*CONSTCOND*/ 0) 339 #endif /* _LOCORE */ 340 341 #endif /* !_X86_INTR_H_ */ 342