1 /* $NetBSD: intr.h,v 1.1 2003/02/26 21:26:10 fvdl Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum, and by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #ifndef _X86_INTR_H_ 40 #define _X86_INTR_H_ 41 42 #include <machine/intrdefs.h> 43 44 #ifndef _LOCORE 45 #include <machine/cpu.h> 46 #include <machine/pic.h> 47 48 /* 49 * Struct describing an interrupt source for a CPU. struct cpu_info 50 * has an array of MAX_INTR_SOURCES of these. The index in the array 51 * is equal to the stub number of the stubcode as present in vector.s 52 * 53 * The primary CPU's array of interrupt sources has its first 16 54 * entries reserved for legacy ISA irq handlers. This means that 55 * they have a 1:1 mapping for arrayindex:irq_num. This is not 56 * true for interrupts that come in through IO APICs, to find 57 * their source, go through ci->ci_isources[index].is_pic 58 * 59 * It's possible to always maintain a 1:1 mapping, but that means 60 * limiting the total number of interrupt sources to MAX_INTR_SOURCES 61 * (32), instead of 32 per CPU. It also would mean that having multiple 62 * IO APICs which deliver interrupts from an equal pin number would 63 * overlap if they were to be sent to the same CPU. 64 */ 65 66 struct intrstub { 67 void *ist_entry; 68 void *ist_recurse; 69 void *ist_resume; 70 }; 71 72 struct intrsource { 73 int is_maxlevel; /* max. IPL for this source */ 74 int is_pin; /* IRQ for legacy; pin for IO APIC */ 75 struct intrhand *is_handlers; /* handler chain */ 76 struct pic *is_pic; /* originating PIC */ 77 void *is_recurse; /* entry for spllower */ 78 void *is_resume; /* entry for doreti */ 79 struct evcnt is_evcnt; /* interrupt counter */ 80 char is_evname[32]; /* event counter name */ 81 int is_flags; /* see below */ 82 int is_type; /* level, edge */ 83 int is_idtvec; 84 int is_minlevel; 85 }; 86 87 #define IS_LEGACY 0x0001 /* legacy ISA irq source */ 88 #define IS_IPI 0x0002 89 #define IS_LOG 0x0004 90 91 92 /* 93 * Interrupt handler chains. *_intr_establish() insert a handler into 94 * the list. The handler is called with its (single) argument. 95 */ 96 97 struct intrhand { 98 int (*ih_fun)(void *); 99 void *ih_arg; 100 int ih_level; 101 struct intrhand *ih_next; 102 int ih_pin; 103 int ih_slot; 104 struct cpu_info *ih_cpu; 105 }; 106 107 #define IMASK(ci,level) (ci)->ci_imask[(level)] 108 #define IUNMASK(ci,level) (ci)->ci_iunmask[(level)] 109 110 extern void Xspllower __P((int)); 111 112 static __inline int splraise __P((int)); 113 static __inline void spllower __P((int)); 114 static __inline void softintr __P((int)); 115 116 /* 117 * Convert spl level to local APIC level 118 */ 119 #define APIC_LEVEL(l) ((l) << 4) 120 121 /* 122 * compiler barrier: prevent reordering of instructions. 123 * XXX something similar will move to <sys/cdefs.h> 124 * or thereabouts. 125 * This prevents the compiler from reordering code around 126 * this "instruction", acting as a sequence point for code generation. 127 */ 128 129 #define __splbarrier() __asm __volatile("":::"memory") 130 131 /* 132 * Add a mask to cpl, and return the old value of cpl. 133 */ 134 static __inline int 135 splraise(int nlevel) 136 { 137 int olevel; 138 struct cpu_info *ci = curcpu(); 139 140 olevel = ci->ci_ilevel; 141 if (nlevel > olevel) 142 ci->ci_ilevel = nlevel; 143 __splbarrier(); 144 return (olevel); 145 } 146 147 /* 148 * Restore a value to cpl (unmasking interrupts). If any unmasked 149 * interrupts are pending, call Xspllower() to process them. 150 */ 151 static __inline void 152 spllower(int nlevel) 153 { 154 struct cpu_info *ci = curcpu(); 155 156 __splbarrier(); 157 /* 158 * Since this should only lower the interrupt level, 159 * the XOR below should only show interrupts that 160 * are being unmasked. 161 */ 162 if (ci->ci_ipending & IUNMASK(ci,nlevel)) 163 Xspllower(nlevel); 164 else 165 ci->ci_ilevel = nlevel; 166 } 167 168 /* 169 * Hardware interrupt masks 170 */ 171 #define splbio() splraise(IPL_BIO) 172 #define splnet() splraise(IPL_NET) 173 #define spltty() splraise(IPL_TTY) 174 #define splaudio() splraise(IPL_AUDIO) 175 #define splclock() splraise(IPL_CLOCK) 176 #define splstatclock() splclock() 177 #define splserial() splraise(IPL_SERIAL) 178 #define splipi() splraise(IPL_IPI) 179 180 #define spllpt() spltty() 181 182 #define SPL_ASSERT_BELOW(x) KDASSERT(curcpu()->ci_ilevel < (x)) 183 #define spllpt() spltty() 184 185 /* 186 * Software interrupt masks 187 * 188 * NOTE: splsoftclock() is used by hardclock() to lower the priority from 189 * clock to softclock before it calls softclock(). 190 */ 191 #define spllowersoftclock() spllower(IPL_SOFTCLOCK) 192 193 #define splsoftclock() splraise(IPL_SOFTCLOCK) 194 #define splsoftnet() splraise(IPL_SOFTNET) 195 #define splsoftserial() splraise(IPL_SOFTSERIAL) 196 197 /* 198 * Miscellaneous 199 */ 200 #define splvm() splraise(IPL_IMP) 201 #define splhigh() splraise(IPL_HIGH) 202 #define spl0() spllower(IPL_NONE) 203 #define splsched() splraise(IPL_SCHED) 204 #define spllock() splhigh() 205 #define splx(x) spllower(x) 206 207 /* 208 * Software interrupt registration 209 * 210 * We hand-code this to ensure that it's atomic. 211 * 212 * XXX always scheduled on the current CPU. 213 */ 214 static __inline void 215 softintr(int sir) 216 { 217 struct cpu_info *ci = curcpu(); 218 219 __asm __volatile("lock ; orl %1, %0" : 220 "=m"(ci->ci_ipending) : "ir" (1 << sir)); 221 } 222 223 /* 224 * XXX 225 */ 226 #define setsoftnet() softintr(SIR_NET) 227 228 /* 229 * Stub declarations. 230 */ 231 232 extern void Xsoftclock(void); 233 extern void Xsoftnet(void); 234 extern void Xsoftserial(void); 235 236 extern struct intrstub i8259_stubs[]; 237 extern struct intrstub ioapic_stubs[]; 238 239 struct cpu_info; 240 241 extern char idt_allocmap[]; 242 243 void intr_default_setup(void); 244 int x86_nmi(void); 245 void intr_calculatemasks(struct cpu_info *); 246 int intr_allocate_slot_cpu(struct cpu_info *, struct pic *, int, int *); 247 int intr_allocate_slot(struct pic *, int, int, int, struct cpu_info **, int *, 248 int *); 249 void *intr_establish(int, struct pic *, int, int, int, int (*)(void *), void *); 250 void intr_disestablish(struct intrhand *); 251 void cpu_intr_init(struct cpu_info *); 252 int intr_find_mpmapping(int bus, int pin, int *handle); 253 #ifdef INTRDEBUG 254 void intr_printconfig(void); 255 #endif 256 257 #ifdef MULTIPROCESSOR 258 int x86_send_ipi(struct cpu_info *, int); 259 void x86_broadcast_ipi(int); 260 void x86_multicast_ipi(int, int); 261 void x86_ipi_handler(void); 262 void x86_intlock(struct intrframe); 263 void x86_intunlock(struct intrframe); 264 void x86_softintlock(void); 265 void x86_softintunlock(void); 266 267 extern void (*ipifunc[X86_NIPI])(struct cpu_info *); 268 #endif 269 270 #endif /* !_LOCORE */ 271 272 /* 273 * Generic software interrupt support. 274 */ 275 276 #define X86_SOFTINTR_SOFTCLOCK 0 277 #define X86_SOFTINTR_SOFTNET 1 278 #define X86_SOFTINTR_SOFTSERIAL 2 279 #define X86_NSOFTINTR 3 280 281 #ifndef _LOCORE 282 #include <sys/queue.h> 283 284 struct x86_soft_intrhand { 285 TAILQ_ENTRY(x86_soft_intrhand) 286 sih_q; 287 struct x86_soft_intr *sih_intrhead; 288 void (*sih_fn)(void *); 289 void *sih_arg; 290 int sih_pending; 291 }; 292 293 struct x86_soft_intr { 294 TAILQ_HEAD(, x86_soft_intrhand) 295 softintr_q; 296 int softintr_ssir; 297 struct simplelock softintr_slock; 298 }; 299 300 #define x86_softintr_lock(si, s) \ 301 do { \ 302 (s) = splhigh(); \ 303 simple_lock(&si->softintr_slock); \ 304 } while (/*CONSTCOND*/ 0) 305 306 #define x86_softintr_unlock(si, s) \ 307 do { \ 308 simple_unlock(&si->softintr_slock); \ 309 splx((s)); \ 310 } while (/*CONSTCOND*/ 0) 311 312 void *softintr_establish(int, void (*)(void *), void *); 313 void softintr_disestablish(void *); 314 void softintr_init(void); 315 void softintr_dispatch(int); 316 317 #define softintr_schedule(arg) \ 318 do { \ 319 struct x86_soft_intrhand *__sih = (arg); \ 320 struct x86_soft_intr *__si = __sih->sih_intrhead; \ 321 int __s; \ 322 \ 323 x86_softintr_lock(__si, __s); \ 324 if (__sih->sih_pending == 0) { \ 325 TAILQ_INSERT_TAIL(&__si->softintr_q, __sih, sih_q); \ 326 __sih->sih_pending = 1; \ 327 softintr(__si->softintr_ssir); \ 328 } \ 329 x86_softintr_unlock(__si, __s); \ 330 } while (/*CONSTCOND*/ 0) 331 #endif /* _LOCORE */ 332 333 #endif /* !_X86_INTR_H_ */ 334