1 /* $NetBSD: intr.h,v 1.28 2007/10/17 19:58:15 garbled Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 2001, 2006, 2007 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum, and by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #ifndef _X86_INTR_H_ 40 #define _X86_INTR_H_ 41 42 #include <machine/intrdefs.h> 43 44 #ifndef _LOCORE 45 #include <machine/pic.h> 46 47 /* 48 * Struct describing an interrupt source for a CPU. struct cpu_info 49 * has an array of MAX_INTR_SOURCES of these. The index in the array 50 * is equal to the stub number of the stubcode as present in vector.s 51 * 52 * The primary CPU's array of interrupt sources has its first 16 53 * entries reserved for legacy ISA irq handlers. This means that 54 * they have a 1:1 mapping for arrayindex:irq_num. This is not 55 * true for interrupts that come in through IO APICs, to find 56 * their source, go through ci->ci_isources[index].is_pic 57 * 58 * It's possible to always maintain a 1:1 mapping, but that means 59 * limiting the total number of interrupt sources to MAX_INTR_SOURCES 60 * (32), instead of 32 per CPU. It also would mean that having multiple 61 * IO APICs which deliver interrupts from an equal pin number would 62 * overlap if they were to be sent to the same CPU. 63 */ 64 65 struct intrstub { 66 void *ist_entry; 67 void *ist_recurse; 68 void *ist_resume; 69 }; 70 71 struct intrsource { 72 int is_maxlevel; /* max. IPL for this source */ 73 int is_pin; /* IRQ for legacy; pin for IO APIC */ 74 struct intrhand *is_handlers; /* handler chain */ 75 struct pic *is_pic; /* originating PIC */ 76 void *is_recurse; /* entry for spllower */ 77 void *is_resume; /* entry for doreti */ 78 struct evcnt is_evcnt; /* interrupt counter */ 79 char is_evname[32]; /* event counter name */ 80 int is_flags; /* see below */ 81 int is_type; /* level, edge */ 82 int is_idtvec; 83 int is_minlevel; 84 }; 85 86 #define IS_LEGACY 0x0001 /* legacy ISA irq source */ 87 #define IS_IPI 0x0002 88 #define IS_LOG 0x0004 89 90 /* 91 * Interrupt handler chains. *_intr_establish() insert a handler into 92 * the list. The handler is called with its (single) argument. 93 */ 94 95 struct intrhand { 96 int (*ih_fun)(void *); 97 void *ih_arg; 98 int ih_level; 99 int (*ih_realfun)(void *); 100 void *ih_realarg; 101 struct intrhand *ih_next; 102 int ih_pin; 103 int ih_slot; 104 struct cpu_info *ih_cpu; 105 }; 106 107 #define IMASK(ci,level) (ci)->ci_imask[(level)] 108 #define IUNMASK(ci,level) (ci)->ci_iunmask[(level)] 109 110 void Xspllower(int); 111 void spllower(int); 112 int splraise(int); 113 void softintr(int); 114 115 /* 116 * Convert spl level to local APIC level 117 */ 118 119 #define APIC_LEVEL(l) ((l) << 4) 120 121 /* 122 * Miscellaneous 123 */ 124 125 #define SPL_ASSERT_BELOW(x) KDASSERT(curcpu()->ci_ilevel < (x)) 126 #define spl0() spllower(IPL_NONE) 127 #define splx(x) spllower(x) 128 129 typedef uint8_t ipl_t; 130 typedef struct { 131 ipl_t _ipl; 132 } ipl_cookie_t; 133 134 static inline ipl_cookie_t 135 makeiplcookie(ipl_t ipl) 136 { 137 138 return (ipl_cookie_t){._ipl = ipl}; 139 } 140 141 static inline int 142 splraiseipl(ipl_cookie_t icookie) 143 { 144 145 return splraise(icookie._ipl); 146 } 147 148 #include <sys/spl.h> 149 150 /* 151 * XXX 152 */ 153 154 #define setsoftnet() softintr(SIR_NET) 155 156 /* 157 * Stub declarations. 158 */ 159 160 void Xsoftclock(void); 161 void Xsoftnet(void); 162 void Xsoftserial(void); 163 164 extern struct intrstub i8259_stubs[]; 165 extern struct intrstub ioapic_edge_stubs[]; 166 extern struct intrstub ioapic_level_stubs[]; 167 168 struct cpu_info; 169 170 extern char idt_allocmap[]; 171 172 struct pcibus_attach_args; 173 174 void intr_default_setup(void); 175 int x86_nmi(void); 176 void intr_calculatemasks(struct cpu_info *); 177 int intr_allocate_slot_cpu(struct cpu_info *, struct pic *, int, int *); 178 int intr_allocate_slot(struct pic *, int, int, int, struct cpu_info **, int *, 179 int *); 180 void *intr_establish(int, struct pic *, int, int, int, int (*)(void *), void *); 181 void intr_disestablish(struct intrhand *); 182 void intr_add_pcibus(struct pcibus_attach_args *); 183 const char *intr_string(int); 184 void cpu_intr_init(struct cpu_info *); 185 int intr_find_mpmapping(int, int, int *); 186 struct pic *intr_findpic(int); 187 #ifdef INTRDEBUG 188 void intr_printconfig(void); 189 #endif 190 191 int x86_send_ipi(struct cpu_info *, int); 192 void x86_broadcast_ipi(int); 193 void x86_multicast_ipi(int, int); 194 void x86_ipi_handler(void); 195 void x86_softintlock(void); 196 void x86_softintunlock(void); 197 198 extern void (*ipifunc[X86_NIPI])(struct cpu_info *); 199 200 #endif /* !_LOCORE */ 201 202 /* 203 * Generic software interrupt support. 204 */ 205 206 #define X86_SOFTINTR_SOFTCLOCK 0 207 #define X86_SOFTINTR_SOFTNET 1 208 #define X86_SOFTINTR_SOFTSERIAL 2 209 #define X86_NSOFTINTR 3 210 211 #ifndef _LOCORE 212 #include <sys/queue.h> 213 214 struct x86_soft_intrhand { 215 TAILQ_ENTRY(x86_soft_intrhand) 216 sih_q; 217 struct x86_soft_intr *sih_intrhead; 218 void (*sih_fn)(void *); 219 void *sih_arg; 220 int sih_pending; 221 }; 222 223 struct x86_soft_intr { 224 TAILQ_HEAD(, x86_soft_intrhand) 225 softintr_q; 226 int softintr_ssir; 227 struct simplelock softintr_slock; 228 }; 229 230 #define x86_softintr_lock(si, s) \ 231 do { \ 232 (s) = splhigh(); \ 233 simple_lock(&si->softintr_slock); \ 234 } while (/*CONSTCOND*/ 0) 235 236 #define x86_softintr_unlock(si, s) \ 237 do { \ 238 simple_unlock(&si->softintr_slock); \ 239 splx((s)); \ 240 } while (/*CONSTCOND*/ 0) 241 242 void *softintr_establish(int, void (*)(void *), void *); 243 void softintr_disestablish(void *); 244 void softintr_init(void); 245 void softintr_dispatch(int); 246 void softintr_schedule(void *arg); 247 248 #endif /* _LOCORE */ 249 250 #endif /* !_X86_INTR_H_ */ 251