1 /* $NetBSD: i82093reg.h,v 1.3 2011/08/17 14:55:11 dyoung Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by RedBack Networks Inc. 9 * 10 * Author: Bill Sommerfeld 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * Typically, the first apic lives here. 36 */ 37 #define IOAPIC_BASE_DEFAULT 0xfec00000 38 39 #define IOAPIC_MSIADDR_BASE 0xfee00000 40 #define IOAPIC_MSIADDR_DSTID_MASK __BITS(19, 12) 41 #define IOAPIC_MSIADDR_RSVD0_MASK __BITS(11, 4) 42 #define IOAPIC_MSIADDR_RH __BIT(3) 43 #define IOAPIC_MSIADDR_DM __BIT(2) 44 #define IOAPIC_MSIADDR_RSVD1_MASK __BITS(1, 0) 45 46 #define IOAPIC_MSIDATA_VECTOR_MASK __BITS(7, 0) 47 #define IOAPIC_MSIDATA_DM_MASK __BITS(10, 8) 48 #define IOAPIC_MSIDATA_DM_FIXED __SHIFTIN(0, IOAPIC_MSIDATA_DM_MASK) 49 #define IOAPIC_MSIDATA_DM_LOPRI __SHIFTIN(1, IOAPIC_MSIDATA_DM_MASK) 50 #define IOAPIC_MSIDATA_DM_SMI __SHIFTIN(2, IOAPIC_MSIDATA_DM_MASK) 51 #define IOAPIC_MSIDATA_DM_RSVD0 __SHIFTIN(3, IOAPIC_MSIDATA_DM_MASK) 52 #define IOAPIC_MSIDATA_DM_NMI __SHIFTIN(4, IOAPIC_MSIDATA_DM_MASK) 53 #define IOAPIC_MSIDATA_DM_INIT __SHIFTIN(5, IOAPIC_MSIDATA_DM_MASK) 54 #define IOAPIC_MSIDATA_DM_RSVD1 __SHIFTIN(6, IOAPIC_MSIDATA_DM_MASK) 55 #define IOAPIC_MSIDATA_DM_EXTINT __SHIFTIN(7, IOAPIC_MSIDATA_DM_MASK) 56 #define IOAPIC_MSIDATA_RSVD0_MASK __BITS(13, 11) 57 #define IOAPIC_MSIDATA_LEVEL_MASK __BIT(14) 58 #define IOAPIC_MSIDATA_LEVEL_DEASSERT __SHIFTIN(0, IOAPIC_MSIDATA_LEVEL_MASK) 59 #define IOAPIC_MSIDATA_LEVEL_ASSERT __SHIFTIN(1, IOAPIC_MSIDATA_LEVEL_MASK) 60 #define IOAPIC_MSIDATA_TRGMODE_MASK __BIT(15) 61 #define IOAPIC_MSIDATA_TRGMODE_EDGE \ 62 __SHIFTIN(0, IOAPIC_MSIDATA_TRGMODE_MASK) 63 #define IOAPIC_MSIDATA_TRGMODE_LEVEL \ 64 __SHIFTIN(1, IOAPIC_MSIDATA_TRGMODE_MASK) 65 #define IOAPIC_MSIDATA_RSVD1_MASK __BITS(31, 16) 66 67 /* 68 * Memory-space registers. 69 */ 70 71 /* 72 * The externally visible registers are all 32 bits wide; 73 * store the register number of interest in IOAPIC_REG, and store/fetch 74 * the real value in IOAPIC_DATA. 75 */ 76 77 78 79 #define IOAPIC_REG 0x0000 80 #define IOAPIC_DATA 0x0010 81 82 /* 83 * Internal I/O APIC registers. 84 */ 85 86 #define IOAPIC_ID 0x00 87 88 #define IOAPIC_ID_SHIFT 24 89 #define IOAPIC_ID_MASK 0x0f000000 90 91 /* Version, and maximum interrupt pin number. */ 92 93 #define IOAPIC_VER 0x01 94 95 #define IOAPIC_VER_SHIFT 0 96 #define IOAPIC_VER_MASK 0x000000ff 97 98 #define IOAPIC_MAX_SHIFT 16 99 #define IOAPIC_MAX_MASK 0x00ff0000 100 101 /* 102 * Arbitration ID. Same format as IOAPIC_ID register. 103 */ 104 #define IOAPIC_ARB 0x02 105 106 /* 107 * Redirection table registers. 108 */ 109 110 #define IOAPIC_REDHI(pin) (0x11 + ((pin)<<1)) 111 #define IOAPIC_REDLO(pin) (0x10 + ((pin)<<1)) 112 113 #define IOAPIC_REDHI_DEST_SHIFT 24 /* destination. */ 114 #define IOAPIC_REDHI_DEST_MASK 0xff000000 115 116 #define IOAPIC_REDLO_MASK 0x00010000 /* 0=enabled; 1=masked */ 117 118 #define IOAPIC_REDLO_LEVEL 0x00008000 /* 0=edge, 1=level */ 119 #define IOAPIC_REDLO_RIRR 0x00004000 /* remote IRR; read only */ 120 #define IOAPIC_REDLO_ACTLO 0x00002000 /* 0=act. hi; 1=act. lo */ 121 #define IOAPIC_REDLO_DELSTS 0x00001000 /* 0=idle; 1=send pending */ 122 #define IOAPIC_REDLO_DSTMOD 0x00000800 /* 0=physical; 1=logical */ 123 124 #define IOAPIC_REDLO_DEL_MASK 0x00000700 /* del. mode mask */ 125 #define IOAPIC_REDLO_DEL_SHIFT 8 126 127 #define IOAPIC_REDLO_DEL_FIXED 0 128 #define IOAPIC_REDLO_DEL_LOPRI 1 129 #define IOAPIC_REDLO_DEL_SMI 2 130 #define IOAPIC_REDLO_DEL_NMI 4 131 #define IOAPIC_REDLO_DEL_INIT 5 132 #define IOAPIC_REDLO_DEL_EXTINT 7 133 134 #define IOAPIC_REDLO_VECTOR_MASK 0x000000ff /* delivery vector */ 135 136 #define IMCR_ADDR 0x22 137 #define IMCR_DATA 0x23 138 139 #define IMCR_REGISTER 0x70 140 #define IMCR_PIC 0x00 141 #define IMCR_APIC 0x01 142